From e9ee6bea1eb88e73bed98adadda314998103b424 Mon Sep 17 00:00:00 2001 From: Vijayavardhan Vennapusa Date: Fri, 28 Jul 2017 11:23:47 +0530 Subject: [PATCH] dwc3-msm: Add delay between consecutive register reads in while loop Add some delay between two consecutive register reads in while loop so that to avoid traffic congestion on NOCs. Change-Id: I6efb8c91e0d07160ccce593a23898b2259cb1ebf Signed-off-by: Vijayavardhan Vennapusa --- drivers/usb/dwc3/dwc3-msm.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/usb/dwc3/dwc3-msm.c b/drivers/usb/dwc3/dwc3-msm.c index 70db070b05d8..09574025f214 100644 --- a/drivers/usb/dwc3/dwc3-msm.c +++ b/drivers/usb/dwc3/dwc3-msm.c @@ -1239,7 +1239,7 @@ static void gsi_set_clear_dbell(struct usb_ep *ep, */ static bool gsi_check_ready_to_suspend(struct usb_ep *ep, bool f_suspend) { - u32 timeout = 1500; + u32 timeout = 500; u32 reg = 0; struct dwc3_ep *dep = to_dwc3_ep(ep); struct dwc3 *dwc = dep->dwc; @@ -1252,6 +1252,7 @@ static bool gsi_check_ready_to_suspend(struct usb_ep *ep, bool f_suspend) "Unable to suspend GSI ch. WR_CTRL_STATE != 0\n"); return false; } + usleep_range(20, 22); } /* Check for U3 only if we are not handling Function Suspend */ if (!f_suspend) { @@ -1933,6 +1934,7 @@ static int dwc3_msm_prepare_suspend(struct dwc3_msm *mdwc) reg = dwc3_msm_read_reg(mdwc->base, PWR_EVNT_IRQ_STAT_REG); if (reg & PWR_EVNT_LPM_IN_L2_MASK) break; + usleep_range(20, 30); } if (!(reg & PWR_EVNT_LPM_IN_L2_MASK)) dev_err(mdwc->dev, "could not transition HS PHY to L2\n");