clk: msm: clock-gpu-cobalt: Correct the CRC enable sequence
Correct the sequence to turn on the GPU_GX gdsc as part of enabling the GFX CRC. CRs-Fixed: 1018785 Change-Id: I64d0abe7091f81f85e83747f09ece4bc524a4057 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
This commit is contained in:
Deepak Katragadda
Kyle Yan
parent
b65caeaa32
commit
9739f5e9e3
1 changed files with 66 additions and 53 deletions
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@ -448,6 +448,71 @@ static struct mux_clk gpucc_gcc_dbg_clk = {
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},
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};
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static void enable_gfx_crc(void)
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{
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u32 regval;
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/* Set graphics clock at a safe frequency */
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clk_set_rate(&gpucc_gfx3d_clk.c, gfx3d_clk_src.c.fmax[2]);
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/* Turn on the GPU_CX GDSC */
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regval = readl_relaxed(virt_base_gfx + GPU_CX_GDSCR_OFFSET);
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regval &= ~SW_COLLAPSE_MASK;
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writel_relaxed(regval, virt_base_gfx + GPU_CX_GDSCR_OFFSET);
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/* Wait for 10usecs to let the GDSC turn ON */
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mb();
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udelay(10);
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/* Turn on the Graphics rail */
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if (regulator_enable(vdd_gpucc.regulator[0]))
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pr_warn("Enabling the graphics rail during CRC sequence failed!\n");
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/* Turn on the GPU_GX GDSC */
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writel_relaxed(0x1, virt_base_gfx + GPU_GX_BCR);
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/*
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* BLK_ARES should be kept asserted for 1us before being de-asserted.
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*/
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wmb();
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udelay(1);
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writel_relaxed(0x0, virt_base_gfx + GPU_GX_BCR);
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regval = readl_relaxed(virt_base_gfx + GPUCC_GX_DOMAIN_MISC);
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regval |= BIT(4);
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writel_relaxed(regval, virt_base_gfx + GPUCC_GX_DOMAIN_MISC);
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/* Keep reset asserted for at-least 1us before continuing. */
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wmb();
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udelay(1);
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regval &= ~BIT(4);
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writel_relaxed(regval, virt_base_gfx + GPUCC_GX_DOMAIN_MISC);
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/* Make sure GMEM_RESET is de-asserted before continuing. */
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wmb();
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regval &= ~BIT(0);
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writel_relaxed(regval, virt_base_gfx + GPUCC_GX_DOMAIN_MISC);
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/* All previous writes should be done at this point */
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wmb();
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regval = readl_relaxed(virt_base_gfx + GPU_GX_GDSCR_OFFSET);
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regval &= ~SW_COLLAPSE_MASK;
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writel_relaxed(regval, virt_base_gfx + GPU_GX_GDSCR_OFFSET);
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/* Wait for 10usecs to let the GDSC turn ON */
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mb();
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udelay(10);
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/* Enable the graphics clock */
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clk_prepare_enable(&gpucc_gfx3d_clk.c);
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/* Enabling MND RC in Bypass mode */
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writel_relaxed(0x00015010, virt_base_gfx + CRC_MND_CFG_OFFSET);
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writel_relaxed(0x00800000, virt_base_gfx + CRC_SID_FSM_OFFSET);
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/* Wait for 16 cycles before continuing */
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udelay(1);
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clk_set_rate(&gpucc_gfx3d_clk.c,
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gfx3d_clk_src.c.fmax[gfx3d_clk_src.c.num_fmax - 1]);
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/* Disable the graphics clock */
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clk_disable_unprepare(&gpucc_gfx3d_clk.c);
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/* Turn off the gpu_cx and gpu_gx GDSCs */
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regval = readl_relaxed(virt_base_gfx + GPU_GX_GDSCR_OFFSET);
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regval |= SW_COLLAPSE_MASK;
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writel_relaxed(regval, virt_base_gfx + GPU_GX_GDSCR_OFFSET);
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regulator_disable(vdd_gpucc.regulator[0]);
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regval = readl_relaxed(virt_base_gfx + GPU_CX_GDSCR_OFFSET);
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regval |= SW_COLLAPSE_MASK;
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writel_relaxed(regval, virt_base_gfx + GPU_CX_GDSCR_OFFSET);
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}
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static struct mux_clk gfxcc_dbg_clk = {
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.ops = &mux_reg_ops,
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.en_mask = BIT(16),
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@ -595,7 +660,6 @@ int msm_gfxcc_cobalt_probe(struct platform_device *pdev)
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struct device_node *of_node = pdev->dev.of_node;
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int rc;
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struct regulator *reg;
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u32 regval;
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bool is_vq = 0;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cc_base");
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@ -659,58 +723,7 @@ int msm_gfxcc_cobalt_probe(struct platform_device *pdev)
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if (rc)
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return rc;
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/* CRC ENABLE SEQUENCE */
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clk_set_rate(&gpucc_gfx3d_clk.c, gfx3d_clk_src.c.fmax[2]);
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/* Turn on the GPU_CX GDSC */
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regval = readl_relaxed(virt_base_gfx + GPU_CX_GDSCR_OFFSET);
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regval &= ~SW_COLLAPSE_MASK;
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writel_relaxed(regval, virt_base_gfx + GPU_CX_GDSCR_OFFSET);
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/* Wait for 10usecs to let the GDSC turn ON */
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mb();
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udelay(10);
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/* Turn on the GPU_GX GDSC */
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writel_relaxed(0x1, virt_base_gfx + GPU_GX_BCR);
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/*
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* BLK_ARES should be kept asserted for 1us before being de-asserted.
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*/
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wmb();
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udelay(1);
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writel_relaxed(0x0, virt_base_gfx + GPU_GX_BCR);
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regval = readl_relaxed(virt_base_gfx + GPUCC_GX_DOMAIN_MISC);
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regval |= BIT(4);
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writel_relaxed(regval, virt_base_gfx + GPUCC_GX_DOMAIN_MISC);
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/* Keep reset asserted for at-least 1us before continuing. */
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wmb();
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udelay(1);
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regval &= ~BIT(4);
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writel_relaxed(regval, virt_base_gfx + GPUCC_GX_DOMAIN_MISC);
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/* Make sure GMEM_RESET is de-asserted before continuing. */
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wmb();
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regval = readl_relaxed(virt_base_gfx + GPU_GX_GDSCR_OFFSET);
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regval &= ~SW_COLLAPSE_MASK;
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writel_relaxed(regval, virt_base_gfx + GPU_GX_GDSCR_OFFSET);
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/* Wait for 10usecs to let the GDSC turn ON */
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mb();
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udelay(10);
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/* Enable the graphics clock */
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clk_prepare_enable(&gpucc_gfx3d_clk.c);
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/* Enabling MND RC in Bypass mode */
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writel_relaxed(0x00015010, virt_base_gfx + CRC_MND_CFG_OFFSET);
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writel_relaxed(0x00800000, virt_base_gfx + CRC_SID_FSM_OFFSET);
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/* Wait for 16 cycles before continuing */
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udelay(1);
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clk_set_rate(&gpucc_gfx3d_clk.c,
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gfx3d_clk_src.c.fmax[gfx3d_clk_src.c.num_fmax - 1]);
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/* Disable the graphics clock */
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clk_disable_unprepare(&gpucc_gfx3d_clk.c);
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/* Turn off the gpu_cx and gpu_gx GDSCs */
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regval = readl_relaxed(virt_base_gfx + GPU_GX_GDSCR_OFFSET);
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regval |= SW_COLLAPSE_MASK;
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writel_relaxed(regval, virt_base_gfx + GPU_GX_GDSCR_OFFSET);
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regval = readl_relaxed(virt_base_gfx + GPU_CX_GDSCR_OFFSET);
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regval |= SW_COLLAPSE_MASK;
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writel_relaxed(regval, virt_base_gfx + GPU_CX_GDSCR_OFFSET);
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/* END OF CRC ENABLE SEQUENCE */
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enable_gfx_crc();
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/*
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* Force periph logic to be ON since after NAP, the value of the perf
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