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staging: comedi: ni_stc.h: rename M_Offset_* symbols

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Renamme these CamelCase symbols.

Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Reviewed-by: Ian Abbott <abbotti@mev.co.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
H Hartley Sweeten 2015-05-01 14:58:34 -07:00 • committed by Greg Kroah-Hartman
parent b6cd5c228e
commit 975b6d25c0
2 changed files with 110 additions and 114 deletions
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115
drivers/staging/comedi/drivers/ni_mio_common.c
View file

@ -322,12 +322,11 @@ static const struct mio_regmap m_series_stc_write_regmap[] = {
[G_Command_Register(1)] = { 0x10e, 2 }, [G_Command_Register(1)] = { 0x10e, 2 },
[AI_Command_1_Register] = { 0x110, 2 }, [AI_Command_1_Register] = { 0x110, 2 },
[AO_Command_1_Register] = { 0x112, 2 }, [AO_Command_1_Register] = { 0x112, 2 },
[DIO_Output_Register] = { 0, 0 }, /* DOES NOT MAP CLEANLY */
/* /*
* DIO_Output_Register maps to: * DIO_Output_Register maps to:
* { M_Offset_Static_Digital_Output, 4 } * { NI_M_DIO_REG, 4 } and { NI_M_SCXI_SER_DO_REG, 1 }
* { M_Offset_SCXI_Serial_Data_Out, 1 }
*/ */
[DIO_Output_Register] = { 0, 0 }, /* DOES NOT MAP CLEANLY */
[DIO_Control_Register] = { 0, 0 }, /* DOES NOT MAP CLEANLY */ [DIO_Control_Register] = { 0, 0 }, /* DOES NOT MAP CLEANLY */
[AI_Mode_1_Register] = { 0x118, 2 }, [AI_Mode_1_Register] = { 0x118, 2 },
[AI_Mode_2_Register] = { 0x11a, 2 }, [AI_Mode_2_Register] = { 0x11a, 2 },
@ -633,7 +632,7 @@ static inline void ni_set_cdo_dma_channel(struct comedi_device *dev,
(ni_stc_dma_channel_select_bitfield(mite_channel) << (ni_stc_dma_channel_select_bitfield(mite_channel) <<
CDO_DMA_Select_Shift) & CDO_DMA_Select_Mask; CDO_DMA_Select_Shift) & CDO_DMA_Select_Mask;
} }
ni_writeb(dev, devpriv->cdio_dma_select_reg, M_Offset_CDIO_DMA_Select); ni_writeb(dev, devpriv->cdio_dma_select_reg, NI_M_CDIO_DMA_SEL_REG);
mmiowb(); mmiowb();
spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags); spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
} }
@ -853,8 +852,8 @@ static void ni_clear_ai_fifo(struct comedi_device *dev)
} else { } else {
ni_stc_writew(dev, 1, ADC_FIFO_Clear); ni_stc_writew(dev, 1, ADC_FIFO_Clear);
if (devpriv->is_625x) { if (devpriv->is_625x) {
ni_writeb(dev, 0, M_Offset_Static_AI_Control(0)); ni_writeb(dev, 0, NI_M_STATIC_AI_CTRL_REG(0));
ni_writeb(dev, 1, M_Offset_Static_AI_Control(0)); ni_writeb(dev, 1, NI_M_STATIC_AI_CTRL_REG(0));
#if 0 #if 0
/* the NI example code does 3 convert pulses for 625x boards, /* the NI example code does 3 convert pulses for 625x boards,
but that appears to be wrong in practice. */ but that appears to be wrong in practice. */
@ -1777,9 +1776,9 @@ static void ni_m_series_load_channelgain_list(struct comedi_device *dev,
bypass_bits |= MSeries_AI_Bypass_Dither_Bit; bypass_bits |= MSeries_AI_Bypass_Dither_Bit;
/* don't use 2's complement encoding */ /* don't use 2's complement encoding */
bypass_bits |= MSeries_AI_Bypass_Polarity_Bit; bypass_bits |= MSeries_AI_Bypass_Polarity_Bit;
ni_writel(dev, bypass_bits, M_Offset_AI_Config_FIFO_Bypass); ni_writel(dev, bypass_bits, NI_M_AI_CFG_BYPASS_FIFO_REG);
} else { } else {
ni_writel(dev, 0, M_Offset_AI_Config_FIFO_Bypass); ni_writel(dev, 0, NI_M_AI_CFG_BYPASS_FIFO_REG);
} }
for (i = 0; i < n_chan; i++) { for (i = 0; i < n_chan; i++) {
unsigned config_bits = 0; unsigned config_bits = 0;
@ -1816,7 +1815,7 @@ static void ni_m_series_load_channelgain_list(struct comedi_device *dev,
config_bits |= MSeries_AI_Config_Dither_Bit; config_bits |= MSeries_AI_Config_Dither_Bit;
/* don't use 2's complement encoding */ /* don't use 2's complement encoding */
config_bits |= MSeries_AI_Config_Polarity_Bit; config_bits |= MSeries_AI_Config_Polarity_Bit;
ni_writew(dev, config_bits, M_Offset_AI_Config_FIFO_Data); ni_writew(dev, config_bits, NI_M_AI_CFG_FIFO_DATA_REG);
} }
ni_prime_channelgain_list(dev); ni_prime_channelgain_list(dev);
} }
@ -2050,7 +2049,7 @@ static int ni_ai_insn_read(struct comedi_device *dev,
return -ETIME; return -ETIME;
} }
if (devpriv->is_m_series) { if (devpriv->is_m_series) {
dl = ni_readl(dev, M_Offset_AI_FIFO_Data); dl = ni_readl(dev, NI_M_AI_FIFO_DATA_REG);
dl &= mask; dl &= mask;
data[n] = dl; data[n] = dl;
} else { } else {
@ -2665,8 +2664,8 @@ static int ni_m_series_ao_config_chanlist(struct comedi_device *dev,
for (i = 0; i < s->n_chan; ++i) { for (i = 0; i < s->n_chan; ++i) {
devpriv->ao_conf[i] &= ~MSeries_AO_Update_Timed_Bit; devpriv->ao_conf[i] &= ~MSeries_AO_Update_Timed_Bit;
ni_writeb(dev, devpriv->ao_conf[i], ni_writeb(dev, devpriv->ao_conf[i],
M_Offset_AO_Config_Bank(i)); NI_M_AO_CFG_BANK_REG(i));
ni_writeb(dev, 0xf, M_Offset_AO_Waveform_Order(i)); ni_writeb(dev, 0xf, NI_M_AO_WAVEFORM_ORDER_REG(i));
} }
} }
for (i = 0; i < n_chans; i++) { for (i = 0; i < n_chans; i++) {
@ -2680,23 +2679,21 @@ static int ni_m_series_ao_config_chanlist(struct comedi_device *dev,
switch (krange->max - krange->min) { switch (krange->max - krange->min) {
case 20000000: case 20000000:
conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits; conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
ni_writeb(dev, 0, ni_writeb(dev, 0, NI_M_AO_REF_ATTENUATION_REG(chan));
M_Offset_AO_Reference_Attenuation(chan));
break; break;
case 10000000: case 10000000:
conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits; conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
ni_writeb(dev, 0, ni_writeb(dev, 0, NI_M_AO_REF_ATTENUATION_REG(chan));
M_Offset_AO_Reference_Attenuation(chan));
break; break;
case 4000000: case 4000000:
conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits; conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
ni_writeb(dev, MSeries_Attenuate_x5_Bit, ni_writeb(dev, MSeries_Attenuate_x5_Bit,
M_Offset_AO_Reference_Attenuation(chan)); NI_M_AO_REF_ATTENUATION_REG(chan));
break; break;
case 2000000: case 2000000:
conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits; conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
ni_writeb(dev, MSeries_Attenuate_x5_Bit, ni_writeb(dev, MSeries_Attenuate_x5_Bit,
M_Offset_AO_Reference_Attenuation(chan)); NI_M_AO_REF_ATTENUATION_REG(chan));
break; break;
default: default:
dev_err(dev->class_dev, dev_err(dev->class_dev,
@ -2717,9 +2714,9 @@ static int ni_m_series_ao_config_chanlist(struct comedi_device *dev,
} }
if (timed) if (timed)
conf |= MSeries_AO_Update_Timed_Bit; conf |= MSeries_AO_Update_Timed_Bit;
ni_writeb(dev, conf, M_Offset_AO_Config_Bank(chan)); ni_writeb(dev, conf, NI_M_AO_CFG_BANK_REG(chan));
devpriv->ao_conf[chan] = conf; devpriv->ao_conf[chan] = conf;
ni_writeb(dev, i, M_Offset_AO_Waveform_Order(chan)); ni_writeb(dev, i, NI_M_AO_WAVEFORM_ORDER_REG(chan));
} }
return invert; return invert;
} }
@ -2795,7 +2792,7 @@ static int ni_ao_insn_write(struct comedi_device *dev,
reg = DACx_Direct_Data_671x(chan); reg = DACx_Direct_Data_671x(chan);
} else if (devpriv->is_m_series) { } else if (devpriv->is_m_series) {
reg = M_Offset_DAC_Direct_Data(chan); reg = NI_M_DAC_DIRECT_DATA_REG(chan);
} else { } else {
reg = (chan) ? DAC1_Direct_Data : DAC0_Direct_Data; reg = (chan) ? DAC1_Direct_Data : DAC0_Direct_Data;
} }
@ -3324,7 +3321,7 @@ static int ni_m_series_dio_insn_config(struct comedi_device *dev,
if (ret) if (ret)
return ret; return ret;
ni_writel(dev, s->io_bits, M_Offset_DIO_Direction); ni_writel(dev, s->io_bits, NI_M_DIO_DIR_REG);
return insn->n; return insn->n;
} }
@ -3335,9 +3332,9 @@ static int ni_m_series_dio_insn_bits(struct comedi_device *dev,
unsigned int *data) unsigned int *data)
{ {
if (comedi_dio_update_state(s, data)) if (comedi_dio_update_state(s, data))
ni_writel(dev, s->state, M_Offset_Static_Digital_Output); ni_writel(dev, s->state, NI_M_DIO_REG);
data[1] = ni_readl(dev, M_Offset_Static_Digital_Input); data[1] = ni_readl(dev, NI_M_DIO_REG);
return insn->n; return insn->n;
} }
@ -3444,11 +3441,11 @@ static int ni_cdo_inttrig(struct comedi_device *dev,
#endif #endif
/* /*
* XXX not sure what interrupt C group does * XXX not sure what interrupt C group does
* ni_writeb(dev, Interrupt_Group_C_Enable_Bit, * wait for dma to fill output fifo
* M_Offset_Interrupt_C_Enable); wait for dma to fill output fifo * ni_writeb(dev, Interrupt_Group_C_Enable_Bit, NI_M_INTC_ENA_REG);
*/ */
for (i = 0; i < timeout; ++i) { for (i = 0; i < timeout; ++i) {
if (ni_readl(dev, M_Offset_CDIO_Status) & CDO_FIFO_Full_Bit) if (ni_readl(dev, NI_M_CDIO_STATUS_REG) & CDO_FIFO_Full_Bit)
break; break;
udelay(10); udelay(10);
} }
@ -3459,7 +3456,7 @@ static int ni_cdo_inttrig(struct comedi_device *dev,
} }
ni_writel(dev, CDO_Arm_Bit | CDO_Error_Interrupt_Enable_Set_Bit | ni_writel(dev, CDO_Arm_Bit | CDO_Error_Interrupt_Enable_Set_Bit |
CDO_Empty_FIFO_Interrupt_Enable_Set_Bit, CDO_Empty_FIFO_Interrupt_Enable_Set_Bit,
M_Offset_CDIO_Command); NI_M_CDIO_CMD_REG);
return retval; return retval;
} }
@ -3469,7 +3466,7 @@ static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
unsigned cdo_mode_bits = CDO_FIFO_Mode_Bit | CDO_Halt_On_Error_Bit; unsigned cdo_mode_bits = CDO_FIFO_Mode_Bit | CDO_Halt_On_Error_Bit;
int retval; int retval;
ni_writel(dev, CDO_Reset_Bit, M_Offset_CDIO_Command); ni_writel(dev, CDO_Reset_Bit, NI_M_CDIO_CMD_REG);
switch (cmd->scan_begin_src) { switch (cmd->scan_begin_src) {
case TRIG_EXT: case TRIG_EXT:
cdo_mode_bits |= cdo_mode_bits |=
@ -3482,11 +3479,11 @@ static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
} }
if (cmd->scan_begin_arg & CR_INVERT) if (cmd->scan_begin_arg & CR_INVERT)
cdo_mode_bits |= CDO_Polarity_Bit; cdo_mode_bits |= CDO_Polarity_Bit;
ni_writel(dev, cdo_mode_bits, M_Offset_CDO_Mode); ni_writel(dev, cdo_mode_bits, NI_M_CDO_MODE_REG);
if (s->io_bits) { if (s->io_bits) {
ni_writel(dev, s->state, M_Offset_CDO_FIFO_Data); ni_writel(dev, s->state, NI_M_CDO_FIFO_DATA_REG);
ni_writel(dev, CDO_SW_Update_Bit, M_Offset_CDIO_Command); ni_writel(dev, CDO_SW_Update_Bit, NI_M_CDIO_CMD_REG);
ni_writel(dev, s->io_bits, M_Offset_CDO_Mask_Enable); ni_writel(dev, s->io_bits, NI_M_CDO_MASK_ENA_REG);
} else { } else {
dev_err(dev->class_dev, dev_err(dev->class_dev,
"attempted to run digital output command with no lines configured as outputs\n"); "attempted to run digital output command with no lines configured as outputs\n");
@ -3506,12 +3503,12 @@ static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
ni_writel(dev, CDO_Disarm_Bit | CDO_Error_Interrupt_Enable_Clear_Bit | ni_writel(dev, CDO_Disarm_Bit | CDO_Error_Interrupt_Enable_Clear_Bit |
CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit | CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit |
CDO_FIFO_Request_Interrupt_Enable_Clear_Bit, CDO_FIFO_Request_Interrupt_Enable_Clear_Bit,
M_Offset_CDIO_Command); NI_M_CDIO_CMD_REG);
/* /*
* XXX not sure what interrupt C group does ni_writeb(dev, 0, * XXX not sure what interrupt C group does
* M_Offset_Interrupt_C_Enable); * ni_writeb(dev, 0, NI_M_INTC_ENA_REG);
*/ */
ni_writel(dev, 0, M_Offset_CDO_Mask_Enable); ni_writel(dev, 0, NI_M_CDO_MASK_ENA_REG);
ni_release_cdo_mite_channel(dev); ni_release_cdo_mite_channel(dev);
return 0; return 0;
} }
@ -3542,16 +3539,16 @@ static void handle_cdio_interrupt(struct comedi_device *dev)
spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
#endif #endif
cdio_status = ni_readl(dev, M_Offset_CDIO_Status); cdio_status = ni_readl(dev, NI_M_CDIO_STATUS_REG);
if (cdio_status & (CDO_Overrun_Bit | CDO_Underflow_Bit)) { if (cdio_status & (CDO_Overrun_Bit | CDO_Underflow_Bit)) {
/* XXX just guessing this is needed and does something useful */ /* XXX just guessing this is needed and does something useful */
ni_writel(dev, CDO_Error_Interrupt_Confirm_Bit, ni_writel(dev, CDO_Error_Interrupt_Confirm_Bit,
M_Offset_CDIO_Command); NI_M_CDIO_CMD_REG);
s->async->events |= COMEDI_CB_OVERFLOW; s->async->events |= COMEDI_CB_OVERFLOW;
} }
if (cdio_status & CDO_FIFO_Empty_Bit) { if (cdio_status & CDO_FIFO_Empty_Bit) {
ni_writel(dev, CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit, ni_writel(dev, CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit,
M_Offset_CDIO_Command); NI_M_CDIO_CMD_REG);
/* s->async->events |= COMEDI_CB_EOA; */ /* s->async->events |= COMEDI_CB_EOA; */
} }
comedi_handle_events(dev, s); comedi_handle_events(dev, s);
@ -4033,7 +4030,7 @@ static int ni_m_series_pwm_config(struct comedi_device *dev,
} }
ni_writel(dev, MSeries_Cal_PWM_High_Time_Bits(up_count) | ni_writel(dev, MSeries_Cal_PWM_High_Time_Bits(up_count) |
MSeries_Cal_PWM_Low_Time_Bits(down_count), MSeries_Cal_PWM_Low_Time_Bits(down_count),
M_Offset_Cal_PWM); NI_M_CAL_PWM_REG);
devpriv->pwm_up_count = up_count; devpriv->pwm_up_count = up_count;
devpriv->pwm_down_count = down_count; devpriv->pwm_down_count = down_count;
return 5; return 5;
@ -4398,7 +4395,7 @@ static int ni_m_series_set_pfi_routing(struct comedi_device *dev,
val &= ~MSeries_PFI_Output_Select_Mask(chan); val &= ~MSeries_PFI_Output_Select_Mask(chan);
val |= MSeries_PFI_Output_Select_Bits(chan, source); val |= MSeries_PFI_Output_Select_Bits(chan, source);
ni_writew(dev, val, M_Offset_PFI_Output_Select(index)); ni_writew(dev, val, NI_M_PFI_OUT_SEL_REG(index));
devpriv->pfi_output_select_reg[index] = val; devpriv->pfi_output_select_reg[index] = val;
return 2; return 2;
@ -4433,10 +4430,10 @@ static int ni_config_filter(struct comedi_device *dev,
if (!devpriv->is_m_series) if (!devpriv->is_m_series)
return -ENOTSUPP; return -ENOTSUPP;
bits = ni_readl(dev, M_Offset_PFI_Filter); bits = ni_readl(dev, NI_M_PFI_FILTER_REG);
bits &= ~MSeries_PFI_Filter_Select_Mask(pfi_channel); bits &= ~MSeries_PFI_Filter_Select_Mask(pfi_channel);
bits |= MSeries_PFI_Filter_Select_Bits(pfi_channel, filter); bits |= MSeries_PFI_Filter_Select_Bits(pfi_channel, filter);
ni_writel(dev, bits, M_Offset_PFI_Filter); ni_writel(dev, bits, NI_M_PFI_FILTER_REG);
return 0; return 0;
} }
@ -4489,9 +4486,9 @@ static int ni_pfi_insn_bits(struct comedi_device *dev,
return -ENOTSUPP; return -ENOTSUPP;
if (comedi_dio_update_state(s, data)) if (comedi_dio_update_state(s, data))
ni_writew(dev, s->state, M_Offset_PFI_DO); ni_writew(dev, s->state, NI_M_PFI_DO_REG);
data[1] = ni_readw(dev, M_Offset_PFI_DI); data[1] = ni_readw(dev, NI_M_PFI_DI_REG);
return insn->n; return insn->n;
} }
@ -4750,16 +4747,16 @@ static int ni_mseries_set_pll_master_clock(struct comedi_device *dev,
return retval; return retval;
} }
ni_writew(dev, devpriv->clock_and_fout2, M_Offset_Clock_and_Fout2); ni_writew(dev, devpriv->clock_and_fout2, NI_M_CLK_FOUT2_REG);
pll_control_bits |= pll_control_bits |=
MSeries_PLL_Divisor_Bits(freq_divider) | MSeries_PLL_Divisor_Bits(freq_divider) |
MSeries_PLL_Multiplier_Bits(freq_multiplier); MSeries_PLL_Multiplier_Bits(freq_multiplier);
ni_writew(dev, pll_control_bits, M_Offset_PLL_Control); ni_writew(dev, pll_control_bits, NI_M_PLL_CTRL_REG);
devpriv->clock_source = source; devpriv->clock_source = source;
/* it seems to typically take a few hundred microseconds for PLL to lock */ /* it seems to typically take a few hundred microseconds for PLL to lock */
for (i = 0; i < timeout; ++i) { for (i = 0; i < timeout; ++i) {
if (ni_readw(dev, M_Offset_PLL_Status) & MSeries_PLL_Locked_Bit) if (ni_readw(dev, NI_M_PLL_STATUS_REG) & MSeries_PLL_Locked_Bit)
break; break;
udelay(1); udelay(1);
} }
@ -4787,8 +4784,8 @@ static int ni_set_master_clock(struct comedi_device *dev,
~(MSeries_Timebase1_Select_Bit | ~(MSeries_Timebase1_Select_Bit |
MSeries_Timebase3_Select_Bit); MSeries_Timebase3_Select_Bit);
ni_writew(dev, devpriv->clock_and_fout2, ni_writew(dev, devpriv->clock_and_fout2,
M_Offset_Clock_and_Fout2); NI_M_CLK_FOUT2_REG);
ni_writew(dev, 0, M_Offset_PLL_Control); ni_writew(dev, 0, NI_M_PLL_CTRL_REG);
} }
devpriv->clock_source = source; devpriv->clock_source = source;
} else { } else {
@ -5333,8 +5330,8 @@ static int ni_E_init(struct comedi_device *dev,
/* reset DIO and set all channels to inputs */ /* reset DIO and set all channels to inputs */
ni_writel(dev, CDO_Reset_Bit | CDI_Reset_Bit, ni_writel(dev, CDO_Reset_Bit | CDI_Reset_Bit,
M_Offset_CDIO_Command); NI_M_CDIO_CMD_REG);
ni_writel(dev, s->io_bits, M_Offset_DIO_Direction); ni_writel(dev, s->io_bits, NI_M_DIO_DIR_REG);
} else { } else {
s->insn_bits = ni_dio_insn_bits; s->insn_bits = ni_dio_insn_bits;
s->insn_config = ni_dio_insn_config; s->insn_config = ni_dio_insn_config;
@ -5368,7 +5365,7 @@ static int ni_E_init(struct comedi_device *dev,
/* internal PWM output used for AI nonlinearity calibration */ /* internal PWM output used for AI nonlinearity calibration */
s->insn_config = ni_m_series_pwm_config; s->insn_config = ni_m_series_pwm_config;
ni_writel(dev, 0x0, M_Offset_Cal_PWM); ni_writel(dev, 0x0, NI_M_CAL_PWM_REG);
} else if (devpriv->is_6143) { } else if (devpriv->is_6143) {
/* internal PWM output used for AI nonlinearity calibration */ /* internal PWM output used for AI nonlinearity calibration */
s->insn_config = ni_6143_pwm_config; s->insn_config = ni_6143_pwm_config;
@ -5403,10 +5400,10 @@ static int ni_E_init(struct comedi_device *dev,
s->n_chan = 16; s->n_chan = 16;
s->insn_bits = ni_pfi_insn_bits; s->insn_bits = ni_pfi_insn_bits;
ni_writew(dev, s->state, M_Offset_PFI_DO); ni_writew(dev, s->state, NI_M_PFI_DO_REG);
for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) { for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) {
ni_writew(dev, devpriv->pfi_output_select_reg[i], ni_writew(dev, devpriv->pfi_output_select_reg[i],
M_Offset_PFI_Output_Select(i)); NI_M_PFI_OUT_SEL_REG(i));
} }
} else { } else {
s->n_chan = 10; s->n_chan = 10;
@ -5525,11 +5522,11 @@ static int ni_E_init(struct comedi_device *dev,
for (channel = 0; channel < board->n_aochan; ++channel) { for (channel = 0; channel < board->n_aochan; ++channel) {
ni_writeb(dev, 0xf, ni_writeb(dev, 0xf,
M_Offset_AO_Waveform_Order(channel)); NI_M_AO_WAVEFORM_ORDER_REG(channel));
ni_writeb(dev, 0x0, ni_writeb(dev, 0x0,
M_Offset_AO_Reference_Attenuation(channel)); NI_M_AO_REF_ATTENUATION_REG(channel));
} }
ni_writeb(dev, 0x0, M_Offset_AO_Calibration); ni_writeb(dev, 0x0, NI_M_AO_CALIB_REG);
} }
return 0; return 0;

95
drivers/staging/comedi/drivers/ni_stc.h
View file

@ -924,54 +924,53 @@ static const struct comedi_lrange range_ni_E_ao_ext;
* M-Series specific registers not handled by the DAQ-STC and GPCT register * M-Series specific registers not handled by the DAQ-STC and GPCT register
* remapping. * remapping.
*/ */
#define M_Offset_CDIO_DMA_Select 0x007 #define NI_M_CDIO_DMA_SEL_REG 0x007
#define M_Offset_SCXI_Status 0x007 #define NI_M_SCXI_STATUS_REG 0x007
#define M_Offset_AI_AO_Select 0x009 #define NI_M_AI_AO_SEL_REG 0x009
#define M_Offset_G0_G1_Select 0x00b #define NI_M_G0_G1_SEL_REG 0x00b
#define M_Offset_Misc_Command 0x00f #define NI_M_MISC_CMD_REG 0x00f
#define M_Offset_SCXI_Serial_Data_Out 0x011 #define NI_M_SCXI_SER_DO_REG 0x011
#define M_Offset_SCXI_Control 0x013 #define NI_M_SCXI_CTRL_REG 0x013
#define M_Offset_SCXI_Output_Enable 0x015 #define NI_M_SCXI_OUT_ENA_REG 0x015
#define M_Offset_AI_FIFO_Data 0x01c #define NI_M_AI_FIFO_DATA_REG 0x01c
#define M_Offset_Static_Digital_Output 0x024 #define NI_M_DIO_REG 0x024
#define M_Offset_Static_Digital_Input 0x024 #define NI_M_DIO_DIR_REG 0x028
#define M_Offset_DIO_Direction 0x028 #define NI_M_CAL_PWM_REG 0x040
#define M_Offset_Cal_PWM 0x040 #define NI_M_GEN_PWM_REG(x) (0x044 + ((x) * 2))
#define M_Offset_Gen_PWM(x) (0x044 + ((x) * 2)) #define NI_M_AI_CFG_FIFO_DATA_REG 0x05e
#define M_Offset_AI_Config_FIFO_Data 0x05e #define NI_M_INTC_ENA_REG 0x088
#define M_Offset_Interrupt_C_Enable 0x088 #define NI_M_INTC_STATUS_REG 0x088
#define M_Offset_Interrupt_C_Status 0x088 #define NI_M_ATRIG_CTRL_REG 0x08c
#define M_Offset_Analog_Trigger_Control 0x08c #define NI_M_AO_SER_INT_ENA_REG 0x0a0
#define M_Offset_AO_Serial_Interrupt_Enable 0x0a0 #define NI_M_AO_SER_INT_ACK_REG 0x0a1
#define M_Offset_AO_Serial_Interrupt_Ack 0x0a1 #define NI_M_AO_SER_INT_STATUS_REG 0x0a1
#define M_Offset_AO_Serial_Interrupt_Status 0x0a1 #define NI_M_AO_CALIB_REG 0x0a3
#define M_Offset_AO_Calibration 0x0a3 #define NI_M_AO_FIFO_DATA_REG 0x0a4
#define M_Offset_AO_FIFO_Data 0x0a4 #define NI_M_PFI_FILTER_REG 0x0b0
#define M_Offset_PFI_Filter 0x0b0 #define NI_M_RTSI_FILTER_REG 0x0b4
#define M_Offset_RTSI_Filter 0x0b4 #define NI_M_SCXI_LEGACY_COMPAT_REG 0x0bc
#define M_Offset_SCXI_Legacy_Compatibility 0x0bc #define NI_M_DAC_DIRECT_DATA_REG(x) (0x0c0 + ((x) * 4))
#define M_Offset_DAC_Direct_Data(x) (0x0c0 + ((x) * 4)) #define NI_M_AO_WAVEFORM_ORDER_REG(x) (0x0c2 + ((x) * 4))
#define M_Offset_AO_Waveform_Order(x) (0x0c2 + ((x) * 4)) #define NI_M_AO_CFG_BANK_REG(x) (0x0c3 + ((x) * 4))
#define M_Offset_AO_Config_Bank(x) (0x0c3 + ((x) * 4)) #define NI_M_RTSI_SHARED_MUX_REG 0x1a2
#define M_Offset_RTSI_Shared_MUX 0x1a2 #define NI_M_CLK_FOUT2_REG 0x1c4
#define M_Offset_Clock_and_Fout2 0x1c4 #define NI_M_PLL_CTRL_REG 0x1c6
#define M_Offset_PLL_Control 0x1c6 #define NI_M_PLL_STATUS_REG 0x1c8
#define M_Offset_PLL_Status 0x1c8 #define NI_M_PFI_OUT_SEL_REG(x) (0x1d0 + ((x) * 2))
#define M_Offset_PFI_Output_Select(x) (0x1d0 + ((x) * 2)) #define NI_M_PFI_DI_REG 0x1dc
#define M_Offset_PFI_DI 0x1dc #define NI_M_PFI_DO_REG 0x1de
#define M_Offset_PFI_DO 0x1de #define NI_M_AI_CFG_BYPASS_FIFO_REG 0x218
#define M_Offset_AI_Config_FIFO_Bypass 0x218 #define NI_M_SCXI_DIO_ENA_REG 0x21c
#define M_Offset_SCXI_DIO_Enable 0x21c #define NI_M_CDI_FIFO_DATA_REG 0x220
#define M_Offset_CDI_FIFO_Data 0x220 #define NI_M_CDO_FIFO_DATA_REG 0x220
#define M_Offset_CDO_FIFO_Data 0x220 #define NI_M_CDIO_STATUS_REG 0x224
#define M_Offset_CDIO_Status 0x224 #define NI_M_CDIO_CMD_REG 0x224
#define M_Offset_CDIO_Command 0x224 #define NI_M_CDI_MODE_REG 0x228
#define M_Offset_CDI_Mode 0x228 #define NI_M_CDO_MODE_REG 0x22c
#define M_Offset_CDO_Mode 0x22c #define NI_M_CDI_MASK_ENA_REG 0x230
#define M_Offset_CDI_Mask_Enable 0x230 #define NI_M_CDO_MASK_ENA_REG 0x234
#define M_Offset_CDO_Mask_Enable 0x234 #define NI_M_STATIC_AI_CTRL_REG(x) ((x) ? (0x260 + (x)) : 0x064)
#define M_Offset_Static_AI_Control(x) ((x) ? (0x260 + (x)) : 0x064) #define NI_M_AO_REF_ATTENUATION_REG(x) (0x264 + (x))
#define M_Offset_AO_Reference_Attenuation(x) (0x264 + (x))
enum MSeries_AI_Config_FIFO_Data_Bits { enum MSeries_AI_Config_FIFO_Data_Bits {
MSeries_AI_Config_Channel_Type_Mask = 0x7 << 6, MSeries_AI_Config_Channel_Type_Mask = 0x7 << 6,