staging: comedi: ni_stc.h: rename M_Offset_* symbols
Renamme these CamelCase symbols. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Reviewed-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
H Hartley Sweeten
Greg Kroah-Hartman
parent
b6cd5c228e
commit
975b6d25c0
2 changed files with 110 additions and 114 deletions
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@ -322,12 +322,11 @@ static const struct mio_regmap m_series_stc_write_regmap[] = {
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[G_Command_Register(1)] = { 0x10e, 2 },
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[AI_Command_1_Register] = { 0x110, 2 },
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[AO_Command_1_Register] = { 0x112, 2 },
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[DIO_Output_Register] = { 0, 0 }, /* DOES NOT MAP CLEANLY */
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/*
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* DIO_Output_Register maps to:
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* { M_Offset_Static_Digital_Output, 4 }
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* { M_Offset_SCXI_Serial_Data_Out, 1 }
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* { NI_M_DIO_REG, 4 } and { NI_M_SCXI_SER_DO_REG, 1 }
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*/
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[DIO_Output_Register] = { 0, 0 }, /* DOES NOT MAP CLEANLY */
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[DIO_Control_Register] = { 0, 0 }, /* DOES NOT MAP CLEANLY */
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[AI_Mode_1_Register] = { 0x118, 2 },
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[AI_Mode_2_Register] = { 0x11a, 2 },
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@ -633,7 +632,7 @@ static inline void ni_set_cdo_dma_channel(struct comedi_device *dev,
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(ni_stc_dma_channel_select_bitfield(mite_channel) <<
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CDO_DMA_Select_Shift) & CDO_DMA_Select_Mask;
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}
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ni_writeb(dev, devpriv->cdio_dma_select_reg, M_Offset_CDIO_DMA_Select);
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ni_writeb(dev, devpriv->cdio_dma_select_reg, NI_M_CDIO_DMA_SEL_REG);
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mmiowb();
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spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
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}
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@ -853,8 +852,8 @@ static void ni_clear_ai_fifo(struct comedi_device *dev)
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} else {
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ni_stc_writew(dev, 1, ADC_FIFO_Clear);
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if (devpriv->is_625x) {
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ni_writeb(dev, 0, M_Offset_Static_AI_Control(0));
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ni_writeb(dev, 1, M_Offset_Static_AI_Control(0));
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ni_writeb(dev, 0, NI_M_STATIC_AI_CTRL_REG(0));
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ni_writeb(dev, 1, NI_M_STATIC_AI_CTRL_REG(0));
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#if 0
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/* the NI example code does 3 convert pulses for 625x boards,
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but that appears to be wrong in practice. */
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@ -1777,9 +1776,9 @@ static void ni_m_series_load_channelgain_list(struct comedi_device *dev,
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bypass_bits |= MSeries_AI_Bypass_Dither_Bit;
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/* don't use 2's complement encoding */
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bypass_bits |= MSeries_AI_Bypass_Polarity_Bit;
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ni_writel(dev, bypass_bits, M_Offset_AI_Config_FIFO_Bypass);
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ni_writel(dev, bypass_bits, NI_M_AI_CFG_BYPASS_FIFO_REG);
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} else {
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ni_writel(dev, 0, M_Offset_AI_Config_FIFO_Bypass);
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ni_writel(dev, 0, NI_M_AI_CFG_BYPASS_FIFO_REG);
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}
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for (i = 0; i < n_chan; i++) {
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unsigned config_bits = 0;
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@ -1816,7 +1815,7 @@ static void ni_m_series_load_channelgain_list(struct comedi_device *dev,
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config_bits |= MSeries_AI_Config_Dither_Bit;
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/* don't use 2's complement encoding */
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config_bits |= MSeries_AI_Config_Polarity_Bit;
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ni_writew(dev, config_bits, M_Offset_AI_Config_FIFO_Data);
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ni_writew(dev, config_bits, NI_M_AI_CFG_FIFO_DATA_REG);
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}
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ni_prime_channelgain_list(dev);
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}
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@ -2050,7 +2049,7 @@ static int ni_ai_insn_read(struct comedi_device *dev,
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return -ETIME;
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}
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if (devpriv->is_m_series) {
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dl = ni_readl(dev, M_Offset_AI_FIFO_Data);
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dl = ni_readl(dev, NI_M_AI_FIFO_DATA_REG);
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dl &= mask;
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data[n] = dl;
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} else {
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@ -2665,8 +2664,8 @@ static int ni_m_series_ao_config_chanlist(struct comedi_device *dev,
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for (i = 0; i < s->n_chan; ++i) {
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devpriv->ao_conf[i] &= ~MSeries_AO_Update_Timed_Bit;
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ni_writeb(dev, devpriv->ao_conf[i],
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M_Offset_AO_Config_Bank(i));
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ni_writeb(dev, 0xf, M_Offset_AO_Waveform_Order(i));
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NI_M_AO_CFG_BANK_REG(i));
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ni_writeb(dev, 0xf, NI_M_AO_WAVEFORM_ORDER_REG(i));
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}
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}
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for (i = 0; i < n_chans; i++) {
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@ -2680,23 +2679,21 @@ static int ni_m_series_ao_config_chanlist(struct comedi_device *dev,
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switch (krange->max - krange->min) {
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case 20000000:
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conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
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ni_writeb(dev, 0,
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M_Offset_AO_Reference_Attenuation(chan));
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ni_writeb(dev, 0, NI_M_AO_REF_ATTENUATION_REG(chan));
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break;
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case 10000000:
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conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
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ni_writeb(dev, 0,
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M_Offset_AO_Reference_Attenuation(chan));
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ni_writeb(dev, 0, NI_M_AO_REF_ATTENUATION_REG(chan));
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break;
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case 4000000:
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conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
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ni_writeb(dev, MSeries_Attenuate_x5_Bit,
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M_Offset_AO_Reference_Attenuation(chan));
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NI_M_AO_REF_ATTENUATION_REG(chan));
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break;
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case 2000000:
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conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
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ni_writeb(dev, MSeries_Attenuate_x5_Bit,
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M_Offset_AO_Reference_Attenuation(chan));
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NI_M_AO_REF_ATTENUATION_REG(chan));
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break;
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default:
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dev_err(dev->class_dev,
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@ -2717,9 +2714,9 @@ static int ni_m_series_ao_config_chanlist(struct comedi_device *dev,
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}
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if (timed)
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conf |= MSeries_AO_Update_Timed_Bit;
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ni_writeb(dev, conf, M_Offset_AO_Config_Bank(chan));
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ni_writeb(dev, conf, NI_M_AO_CFG_BANK_REG(chan));
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devpriv->ao_conf[chan] = conf;
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ni_writeb(dev, i, M_Offset_AO_Waveform_Order(chan));
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ni_writeb(dev, i, NI_M_AO_WAVEFORM_ORDER_REG(chan));
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}
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return invert;
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}
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@ -2795,7 +2792,7 @@ static int ni_ao_insn_write(struct comedi_device *dev,
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reg = DACx_Direct_Data_671x(chan);
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} else if (devpriv->is_m_series) {
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reg = M_Offset_DAC_Direct_Data(chan);
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reg = NI_M_DAC_DIRECT_DATA_REG(chan);
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} else {
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reg = (chan) ? DAC1_Direct_Data : DAC0_Direct_Data;
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}
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@ -3324,7 +3321,7 @@ static int ni_m_series_dio_insn_config(struct comedi_device *dev,
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if (ret)
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return ret;
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ni_writel(dev, s->io_bits, M_Offset_DIO_Direction);
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ni_writel(dev, s->io_bits, NI_M_DIO_DIR_REG);
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return insn->n;
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}
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@ -3335,9 +3332,9 @@ static int ni_m_series_dio_insn_bits(struct comedi_device *dev,
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unsigned int *data)
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{
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if (comedi_dio_update_state(s, data))
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ni_writel(dev, s->state, M_Offset_Static_Digital_Output);
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ni_writel(dev, s->state, NI_M_DIO_REG);
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data[1] = ni_readl(dev, M_Offset_Static_Digital_Input);
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data[1] = ni_readl(dev, NI_M_DIO_REG);
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return insn->n;
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}
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@ -3442,13 +3439,13 @@ static int ni_cdo_inttrig(struct comedi_device *dev,
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if (retval < 0)
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return retval;
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#endif
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/*
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* XXX not sure what interrupt C group does
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* ni_writeb(dev, Interrupt_Group_C_Enable_Bit,
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* M_Offset_Interrupt_C_Enable); wait for dma to fill output fifo
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*/
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/*
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* XXX not sure what interrupt C group does
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* wait for dma to fill output fifo
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* ni_writeb(dev, Interrupt_Group_C_Enable_Bit, NI_M_INTC_ENA_REG);
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*/
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for (i = 0; i < timeout; ++i) {
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if (ni_readl(dev, M_Offset_CDIO_Status) & CDO_FIFO_Full_Bit)
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if (ni_readl(dev, NI_M_CDIO_STATUS_REG) & CDO_FIFO_Full_Bit)
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break;
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udelay(10);
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}
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@ -3459,7 +3456,7 @@ static int ni_cdo_inttrig(struct comedi_device *dev,
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}
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ni_writel(dev, CDO_Arm_Bit | CDO_Error_Interrupt_Enable_Set_Bit |
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CDO_Empty_FIFO_Interrupt_Enable_Set_Bit,
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M_Offset_CDIO_Command);
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NI_M_CDIO_CMD_REG);
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return retval;
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}
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@ -3469,7 +3466,7 @@ static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
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unsigned cdo_mode_bits = CDO_FIFO_Mode_Bit | CDO_Halt_On_Error_Bit;
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int retval;
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ni_writel(dev, CDO_Reset_Bit, M_Offset_CDIO_Command);
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ni_writel(dev, CDO_Reset_Bit, NI_M_CDIO_CMD_REG);
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switch (cmd->scan_begin_src) {
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case TRIG_EXT:
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cdo_mode_bits |=
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@ -3482,11 +3479,11 @@ static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
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}
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if (cmd->scan_begin_arg & CR_INVERT)
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cdo_mode_bits |= CDO_Polarity_Bit;
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ni_writel(dev, cdo_mode_bits, M_Offset_CDO_Mode);
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ni_writel(dev, cdo_mode_bits, NI_M_CDO_MODE_REG);
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if (s->io_bits) {
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ni_writel(dev, s->state, M_Offset_CDO_FIFO_Data);
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ni_writel(dev, CDO_SW_Update_Bit, M_Offset_CDIO_Command);
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ni_writel(dev, s->io_bits, M_Offset_CDO_Mask_Enable);
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ni_writel(dev, s->state, NI_M_CDO_FIFO_DATA_REG);
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ni_writel(dev, CDO_SW_Update_Bit, NI_M_CDIO_CMD_REG);
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ni_writel(dev, s->io_bits, NI_M_CDO_MASK_ENA_REG);
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} else {
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dev_err(dev->class_dev,
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"attempted to run digital output command with no lines configured as outputs\n");
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@ -3506,12 +3503,12 @@ static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
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ni_writel(dev, CDO_Disarm_Bit | CDO_Error_Interrupt_Enable_Clear_Bit |
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CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit |
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CDO_FIFO_Request_Interrupt_Enable_Clear_Bit,
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M_Offset_CDIO_Command);
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/*
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* XXX not sure what interrupt C group does ni_writeb(dev, 0,
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* M_Offset_Interrupt_C_Enable);
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*/
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ni_writel(dev, 0, M_Offset_CDO_Mask_Enable);
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NI_M_CDIO_CMD_REG);
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/*
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* XXX not sure what interrupt C group does
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* ni_writeb(dev, 0, NI_M_INTC_ENA_REG);
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*/
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ni_writel(dev, 0, NI_M_CDO_MASK_ENA_REG);
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ni_release_cdo_mite_channel(dev);
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return 0;
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}
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@ -3542,16 +3539,16 @@ static void handle_cdio_interrupt(struct comedi_device *dev)
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spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
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#endif
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cdio_status = ni_readl(dev, M_Offset_CDIO_Status);
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cdio_status = ni_readl(dev, NI_M_CDIO_STATUS_REG);
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if (cdio_status & (CDO_Overrun_Bit | CDO_Underflow_Bit)) {
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/* XXX just guessing this is needed and does something useful */
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ni_writel(dev, CDO_Error_Interrupt_Confirm_Bit,
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M_Offset_CDIO_Command);
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NI_M_CDIO_CMD_REG);
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s->async->events |= COMEDI_CB_OVERFLOW;
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}
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if (cdio_status & CDO_FIFO_Empty_Bit) {
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ni_writel(dev, CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit,
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M_Offset_CDIO_Command);
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NI_M_CDIO_CMD_REG);
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/* s->async->events |= COMEDI_CB_EOA; */
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}
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comedi_handle_events(dev, s);
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@ -4033,7 +4030,7 @@ static int ni_m_series_pwm_config(struct comedi_device *dev,
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}
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ni_writel(dev, MSeries_Cal_PWM_High_Time_Bits(up_count) |
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MSeries_Cal_PWM_Low_Time_Bits(down_count),
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M_Offset_Cal_PWM);
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NI_M_CAL_PWM_REG);
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devpriv->pwm_up_count = up_count;
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devpriv->pwm_down_count = down_count;
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return 5;
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@ -4398,7 +4395,7 @@ static int ni_m_series_set_pfi_routing(struct comedi_device *dev,
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val &= ~MSeries_PFI_Output_Select_Mask(chan);
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val |= MSeries_PFI_Output_Select_Bits(chan, source);
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ni_writew(dev, val, M_Offset_PFI_Output_Select(index));
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ni_writew(dev, val, NI_M_PFI_OUT_SEL_REG(index));
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devpriv->pfi_output_select_reg[index] = val;
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return 2;
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@ -4433,10 +4430,10 @@ static int ni_config_filter(struct comedi_device *dev,
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if (!devpriv->is_m_series)
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return -ENOTSUPP;
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bits = ni_readl(dev, M_Offset_PFI_Filter);
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bits = ni_readl(dev, NI_M_PFI_FILTER_REG);
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bits &= ~MSeries_PFI_Filter_Select_Mask(pfi_channel);
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bits |= MSeries_PFI_Filter_Select_Bits(pfi_channel, filter);
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ni_writel(dev, bits, M_Offset_PFI_Filter);
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ni_writel(dev, bits, NI_M_PFI_FILTER_REG);
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return 0;
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}
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@ -4489,9 +4486,9 @@ static int ni_pfi_insn_bits(struct comedi_device *dev,
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return -ENOTSUPP;
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if (comedi_dio_update_state(s, data))
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ni_writew(dev, s->state, M_Offset_PFI_DO);
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ni_writew(dev, s->state, NI_M_PFI_DO_REG);
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data[1] = ni_readw(dev, M_Offset_PFI_DI);
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data[1] = ni_readw(dev, NI_M_PFI_DI_REG);
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return insn->n;
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}
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@ -4750,16 +4747,16 @@ static int ni_mseries_set_pll_master_clock(struct comedi_device *dev,
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return retval;
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}
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ni_writew(dev, devpriv->clock_and_fout2, M_Offset_Clock_and_Fout2);
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ni_writew(dev, devpriv->clock_and_fout2, NI_M_CLK_FOUT2_REG);
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pll_control_bits |=
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MSeries_PLL_Divisor_Bits(freq_divider) |
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MSeries_PLL_Multiplier_Bits(freq_multiplier);
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ni_writew(dev, pll_control_bits, M_Offset_PLL_Control);
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ni_writew(dev, pll_control_bits, NI_M_PLL_CTRL_REG);
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devpriv->clock_source = source;
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/* it seems to typically take a few hundred microseconds for PLL to lock */
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for (i = 0; i < timeout; ++i) {
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if (ni_readw(dev, M_Offset_PLL_Status) & MSeries_PLL_Locked_Bit)
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if (ni_readw(dev, NI_M_PLL_STATUS_REG) & MSeries_PLL_Locked_Bit)
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break;
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udelay(1);
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}
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@ -4787,8 +4784,8 @@ static int ni_set_master_clock(struct comedi_device *dev,
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~(MSeries_Timebase1_Select_Bit |
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MSeries_Timebase3_Select_Bit);
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ni_writew(dev, devpriv->clock_and_fout2,
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M_Offset_Clock_and_Fout2);
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ni_writew(dev, 0, M_Offset_PLL_Control);
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NI_M_CLK_FOUT2_REG);
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ni_writew(dev, 0, NI_M_PLL_CTRL_REG);
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}
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devpriv->clock_source = source;
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} else {
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@ -5333,8 +5330,8 @@ static int ni_E_init(struct comedi_device *dev,
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/* reset DIO and set all channels to inputs */
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ni_writel(dev, CDO_Reset_Bit | CDI_Reset_Bit,
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M_Offset_CDIO_Command);
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ni_writel(dev, s->io_bits, M_Offset_DIO_Direction);
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NI_M_CDIO_CMD_REG);
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ni_writel(dev, s->io_bits, NI_M_DIO_DIR_REG);
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} else {
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s->insn_bits = ni_dio_insn_bits;
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s->insn_config = ni_dio_insn_config;
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@ -5368,7 +5365,7 @@ static int ni_E_init(struct comedi_device *dev,
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/* internal PWM output used for AI nonlinearity calibration */
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s->insn_config = ni_m_series_pwm_config;
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ni_writel(dev, 0x0, M_Offset_Cal_PWM);
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ni_writel(dev, 0x0, NI_M_CAL_PWM_REG);
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} else if (devpriv->is_6143) {
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/* internal PWM output used for AI nonlinearity calibration */
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s->insn_config = ni_6143_pwm_config;
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@ -5403,10 +5400,10 @@ static int ni_E_init(struct comedi_device *dev,
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s->n_chan = 16;
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s->insn_bits = ni_pfi_insn_bits;
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ni_writew(dev, s->state, M_Offset_PFI_DO);
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ni_writew(dev, s->state, NI_M_PFI_DO_REG);
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for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) {
|
||||
ni_writew(dev, devpriv->pfi_output_select_reg[i],
|
||||
M_Offset_PFI_Output_Select(i));
|
||||
NI_M_PFI_OUT_SEL_REG(i));
|
||||
}
|
||||
} else {
|
||||
s->n_chan = 10;
|
||||
|
|
@ -5525,11 +5522,11 @@ static int ni_E_init(struct comedi_device *dev,
|
|||
|
||||
for (channel = 0; channel < board->n_aochan; ++channel) {
|
||||
ni_writeb(dev, 0xf,
|
||||
M_Offset_AO_Waveform_Order(channel));
|
||||
NI_M_AO_WAVEFORM_ORDER_REG(channel));
|
||||
ni_writeb(dev, 0x0,
|
||||
M_Offset_AO_Reference_Attenuation(channel));
|
||||
NI_M_AO_REF_ATTENUATION_REG(channel));
|
||||
}
|
||||
ni_writeb(dev, 0x0, M_Offset_AO_Calibration);
|
||||
ni_writeb(dev, 0x0, NI_M_AO_CALIB_REG);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -924,54 +924,53 @@ static const struct comedi_lrange range_ni_E_ao_ext;
|
|||
* M-Series specific registers not handled by the DAQ-STC and GPCT register
|
||||
* remapping.
|
||||
*/
|
||||
#define M_Offset_CDIO_DMA_Select 0x007
|
||||
#define M_Offset_SCXI_Status 0x007
|
||||
#define M_Offset_AI_AO_Select 0x009
|
||||
#define M_Offset_G0_G1_Select 0x00b
|
||||
#define M_Offset_Misc_Command 0x00f
|
||||
#define M_Offset_SCXI_Serial_Data_Out 0x011
|
||||
#define M_Offset_SCXI_Control 0x013
|
||||
#define M_Offset_SCXI_Output_Enable 0x015
|
||||
#define M_Offset_AI_FIFO_Data 0x01c
|
||||
#define M_Offset_Static_Digital_Output 0x024
|
||||
#define M_Offset_Static_Digital_Input 0x024
|
||||
#define M_Offset_DIO_Direction 0x028
|
||||
#define M_Offset_Cal_PWM 0x040
|
||||
#define M_Offset_Gen_PWM(x) (0x044 + ((x) * 2))
|
||||
#define M_Offset_AI_Config_FIFO_Data 0x05e
|
||||
#define M_Offset_Interrupt_C_Enable 0x088
|
||||
#define M_Offset_Interrupt_C_Status 0x088
|
||||
#define M_Offset_Analog_Trigger_Control 0x08c
|
||||
#define M_Offset_AO_Serial_Interrupt_Enable 0x0a0
|
||||
#define M_Offset_AO_Serial_Interrupt_Ack 0x0a1
|
||||
#define M_Offset_AO_Serial_Interrupt_Status 0x0a1
|
||||
#define M_Offset_AO_Calibration 0x0a3
|
||||
#define M_Offset_AO_FIFO_Data 0x0a4
|
||||
#define M_Offset_PFI_Filter 0x0b0
|
||||
#define M_Offset_RTSI_Filter 0x0b4
|
||||
#define M_Offset_SCXI_Legacy_Compatibility 0x0bc
|
||||
#define M_Offset_DAC_Direct_Data(x) (0x0c0 + ((x) * 4))
|
||||
#define M_Offset_AO_Waveform_Order(x) (0x0c2 + ((x) * 4))
|
||||
#define M_Offset_AO_Config_Bank(x) (0x0c3 + ((x) * 4))
|
||||
#define M_Offset_RTSI_Shared_MUX 0x1a2
|
||||
#define M_Offset_Clock_and_Fout2 0x1c4
|
||||
#define M_Offset_PLL_Control 0x1c6
|
||||
#define M_Offset_PLL_Status 0x1c8
|
||||
#define M_Offset_PFI_Output_Select(x) (0x1d0 + ((x) * 2))
|
||||
#define M_Offset_PFI_DI 0x1dc
|
||||
#define M_Offset_PFI_DO 0x1de
|
||||
#define M_Offset_AI_Config_FIFO_Bypass 0x218
|
||||
#define M_Offset_SCXI_DIO_Enable 0x21c
|
||||
#define M_Offset_CDI_FIFO_Data 0x220
|
||||
#define M_Offset_CDO_FIFO_Data 0x220
|
||||
#define M_Offset_CDIO_Status 0x224
|
||||
#define M_Offset_CDIO_Command 0x224
|
||||
#define M_Offset_CDI_Mode 0x228
|
||||
#define M_Offset_CDO_Mode 0x22c
|
||||
#define M_Offset_CDI_Mask_Enable 0x230
|
||||
#define M_Offset_CDO_Mask_Enable 0x234
|
||||
#define M_Offset_Static_AI_Control(x) ((x) ? (0x260 + (x)) : 0x064)
|
||||
#define M_Offset_AO_Reference_Attenuation(x) (0x264 + (x))
|
||||
#define NI_M_CDIO_DMA_SEL_REG 0x007
|
||||
#define NI_M_SCXI_STATUS_REG 0x007
|
||||
#define NI_M_AI_AO_SEL_REG 0x009
|
||||
#define NI_M_G0_G1_SEL_REG 0x00b
|
||||
#define NI_M_MISC_CMD_REG 0x00f
|
||||
#define NI_M_SCXI_SER_DO_REG 0x011
|
||||
#define NI_M_SCXI_CTRL_REG 0x013
|
||||
#define NI_M_SCXI_OUT_ENA_REG 0x015
|
||||
#define NI_M_AI_FIFO_DATA_REG 0x01c
|
||||
#define NI_M_DIO_REG 0x024
|
||||
#define NI_M_DIO_DIR_REG 0x028
|
||||
#define NI_M_CAL_PWM_REG 0x040
|
||||
#define NI_M_GEN_PWM_REG(x) (0x044 + ((x) * 2))
|
||||
#define NI_M_AI_CFG_FIFO_DATA_REG 0x05e
|
||||
#define NI_M_INTC_ENA_REG 0x088
|
||||
#define NI_M_INTC_STATUS_REG 0x088
|
||||
#define NI_M_ATRIG_CTRL_REG 0x08c
|
||||
#define NI_M_AO_SER_INT_ENA_REG 0x0a0
|
||||
#define NI_M_AO_SER_INT_ACK_REG 0x0a1
|
||||
#define NI_M_AO_SER_INT_STATUS_REG 0x0a1
|
||||
#define NI_M_AO_CALIB_REG 0x0a3
|
||||
#define NI_M_AO_FIFO_DATA_REG 0x0a4
|
||||
#define NI_M_PFI_FILTER_REG 0x0b0
|
||||
#define NI_M_RTSI_FILTER_REG 0x0b4
|
||||
#define NI_M_SCXI_LEGACY_COMPAT_REG 0x0bc
|
||||
#define NI_M_DAC_DIRECT_DATA_REG(x) (0x0c0 + ((x) * 4))
|
||||
#define NI_M_AO_WAVEFORM_ORDER_REG(x) (0x0c2 + ((x) * 4))
|
||||
#define NI_M_AO_CFG_BANK_REG(x) (0x0c3 + ((x) * 4))
|
||||
#define NI_M_RTSI_SHARED_MUX_REG 0x1a2
|
||||
#define NI_M_CLK_FOUT2_REG 0x1c4
|
||||
#define NI_M_PLL_CTRL_REG 0x1c6
|
||||
#define NI_M_PLL_STATUS_REG 0x1c8
|
||||
#define NI_M_PFI_OUT_SEL_REG(x) (0x1d0 + ((x) * 2))
|
||||
#define NI_M_PFI_DI_REG 0x1dc
|
||||
#define NI_M_PFI_DO_REG 0x1de
|
||||
#define NI_M_AI_CFG_BYPASS_FIFO_REG 0x218
|
||||
#define NI_M_SCXI_DIO_ENA_REG 0x21c
|
||||
#define NI_M_CDI_FIFO_DATA_REG 0x220
|
||||
#define NI_M_CDO_FIFO_DATA_REG 0x220
|
||||
#define NI_M_CDIO_STATUS_REG 0x224
|
||||
#define NI_M_CDIO_CMD_REG 0x224
|
||||
#define NI_M_CDI_MODE_REG 0x228
|
||||
#define NI_M_CDO_MODE_REG 0x22c
|
||||
#define NI_M_CDI_MASK_ENA_REG 0x230
|
||||
#define NI_M_CDO_MASK_ENA_REG 0x234
|
||||
#define NI_M_STATIC_AI_CTRL_REG(x) ((x) ? (0x260 + (x)) : 0x064)
|
||||
#define NI_M_AO_REF_ATTENUATION_REG(x) (0x264 + (x))
|
||||
|
||||
enum MSeries_AI_Config_FIFO_Data_Bits {
|
||||
MSeries_AI_Config_Channel_Type_Mask = 0x7 << 6,
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue