crypto: msm: disable aead alg related apis temporarily
Just temporarily disable aead alg related apis for 4.4 upgrade. 4.4 upstream cryto driver has a lot of changes on aead related APIS and data structures, and hw crypto driver can not be compiled on 4.4. Signed-off-by: Zhen Kong <zkong@codeaurora.org>
This commit is contained in:
Zhen Kong
David Keitel
parent
1db07b7a79
commit
97a7e8fcc4
3 changed files with 35 additions and 18 deletions
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@ -207,7 +207,7 @@ static int count_sg(struct scatterlist *sg, int nbytes)
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{
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int i;
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for (i = 0; nbytes > 0; i++, sg = scatterwalk_sg_next(sg))
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for (i = 0; nbytes > 0; i++, sg = sg_next(sg))
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nbytes -= sg->length;
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return i;
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}
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@ -219,7 +219,7 @@ static int qce_dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
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for (i = 0; i < nents; ++i) {
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dma_map_sg(dev, sg, 1, direction);
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sg = scatterwalk_sg_next(sg);
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sg = sg_next(sg);
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}
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return nents;
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@ -232,7 +232,7 @@ static int qce_dma_unmap_sg(struct device *dev, struct scatterlist *sg,
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for (i = 0; i < nents; ++i) {
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dma_unmap_sg(dev, sg, 1, direction);
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sg = scatterwalk_sg_next(sg);
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sg = sg_next(sg);
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}
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return nents;
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@ -2035,6 +2035,7 @@ static int _qce_unlock_other_pipes(struct qce_device *pce_dev, int req_info)
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static inline void qce_free_req_info(struct qce_device *pce_dev, int req_info,
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bool is_complete);
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#if 0
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static int _aead_complete(struct qce_device *pce_dev, int req_info)
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{
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struct aead_request *areq;
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@ -2124,6 +2125,7 @@ static int _aead_complete(struct qce_device *pce_dev, int req_info)
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}
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return 0;
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};
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#endif
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static int _sha_complete(struct qce_device *pce_dev, int req_info)
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{
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@ -2450,7 +2452,7 @@ static int _qce_sps_add_sg_data(struct qce_device *pce_dev,
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addr += data_cnt;
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len -= data_cnt;
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}
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sg_src = scatterwalk_sg_next(sg_src);
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sg_src = sg_next(sg_src);
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}
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return 0;
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}
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@ -2936,9 +2938,11 @@ static void _qce_req_complete(struct qce_device *pce_dev, unsigned int req_info)
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case QCE_XFER_HASHING:
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_sha_complete(pce_dev, req_info);
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break;
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#if 0
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case QCE_XFER_AEAD:
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_aead_complete(pce_dev, req_info);
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break;
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#endif
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case QCE_XFER_F8:
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_f8_complete(pce_dev, req_info);
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break;
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@ -4569,7 +4573,7 @@ static int select_mode(struct qce_device *pce_dev,
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return 0;
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}
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#if 0
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static int _qce_aead_ccm_req(void *handle, struct qce_req *q_req)
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{
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struct qce_device *pce_dev = (struct qce_device *) handle;
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@ -4782,6 +4786,7 @@ bad:
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return rc;
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}
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#endif
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static int _qce_suspend(void *handle)
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{
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@ -4844,6 +4849,7 @@ static int _qce_resume(void *handle)
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struct qce_pm_table qce_pm_table = {_qce_suspend, _qce_resume};
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EXPORT_SYMBOL(qce_pm_table);
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#if 0
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int qce_aead_req(void *handle, struct qce_req *q_req)
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{
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struct qce_device *pce_dev = (struct qce_device *)handle;
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@ -5053,6 +5059,7 @@ bad:
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return rc;
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}
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EXPORT_SYMBOL(qce_aead_req);
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#endif
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int qce_ablk_cipher_req(void *handle, struct qce_req *c_req)
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{
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@ -691,7 +691,7 @@ static int qcrypto_count_sg(struct scatterlist *sg, int nbytes)
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{
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int i;
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for (i = 0; nbytes > 0 && sg != NULL; i++, sg = scatterwalk_sg_next(sg))
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for (i = 0; nbytes > 0 && sg != NULL; i++, sg = sg_next(sg))
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nbytes -= sg->length;
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return i;
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@ -708,7 +708,7 @@ static size_t qcrypto_sg_copy_from_buffer(struct scatterlist *sgl,
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buf += len;
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buflen -= len;
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offset += len;
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sgl = scatterwalk_sg_next(sgl);
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sgl = sg_next(sgl);
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}
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return offset;
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@ -725,7 +725,7 @@ static size_t qcrypto_sg_copy_to_buffer(struct scatterlist *sgl,
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buf += len;
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buflen -= len;
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offset += len;
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sgl = scatterwalk_sg_next(sgl);
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sgl = sg_next(sgl);
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}
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return offset;
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@ -887,6 +887,7 @@ static int _qcrypto_cra_aes_ablkcipher_init(struct crypto_tfm *tfm)
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return _qcrypto_cra_ablkcipher_init(tfm);
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};
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#if 0
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static int _qcrypto_cra_aead_sha1_init(struct crypto_tfm *tfm)
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{
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int rc;
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@ -930,6 +931,7 @@ static int _qcrypto_cra_aead_rfc4309_ccm_init(struct crypto_tfm *tfm)
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ctx->auth_alg = QCE_HASH_AES_CMAC;
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return rc;
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}
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#endif
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static void _qcrypto_cra_ablkcipher_exit(struct crypto_tfm *tfm)
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{
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@ -1606,7 +1608,7 @@ static void _qce_ablk_cipher_complete(void *cookie, unsigned char *icb,
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req_done(pqcrypto_req_control);
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};
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#if 0
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static void _qce_aead_complete(void *cookie, unsigned char *icv,
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unsigned char *iv, int ret)
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{
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@ -1728,6 +1730,7 @@ static void _qce_aead_complete(void *cookie, unsigned char *icv,
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pqcrypto_req_control->arsp->res = ret;
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req_done(pqcrypto_req_control);
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}
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#endif
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static int aead_ccm_set_msg_len(u8 *block, unsigned int msglen, int csize)
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{
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@ -1942,6 +1945,7 @@ static int _qcrypto_process_ahash(struct crypto_engine *pengine,
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return ret;
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}
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#if 0
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static int _qcrypto_process_aead(struct crypto_engine *pengine,
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struct qcrypto_req_control *pqcrypto_req_control)
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{
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@ -2145,6 +2149,7 @@ static int _qcrypto_process_aead(struct crypto_engine *pengine,
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return ret;
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}
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#endif
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static struct crypto_engine *_qcrypto_static_assign_engine(
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struct crypto_priv *cp)
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@ -2284,9 +2289,11 @@ again:
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case CRYPTO_ALG_TYPE_AHASH:
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ret = _qcrypto_process_ahash(pengine, pqcrypto_req_control);
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break;
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#if 0
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case CRYPTO_ALG_TYPE_AEAD:
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ret = _qcrypto_process_aead(pengine, pqcrypto_req_control);
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break;
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#endif
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default:
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ret = -EINVAL;
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};
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@ -2853,7 +2860,7 @@ static int _qcrypto_dec_aes_xts(struct ablkcipher_request *req)
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return _qcrypto_queue_req(cp, ctx->pengine, &req->base);
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};
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#if 0
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static int _qcrypto_aead_decrypt_aes_ccm(struct aead_request *req)
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{
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struct qcrypto_cipher_req_ctx *rctx;
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@ -3259,6 +3266,7 @@ static int _qcrypto_aead_givencrypt_3des_cbc(struct aead_givcrypt_request *req)
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pstat->aead_sha256_3des_enc++;
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return _qcrypto_queue_req(cp, ctx->pengine, &areq->base);
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}
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#endif
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static int _sha_init(struct ahash_request *req)
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{
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@ -3523,7 +3531,7 @@ static int _sha_update(struct ahash_request *req, uint32_t sha_block_size)
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if ((len + sg_last->length) > nbytes)
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break;
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len += sg_last->length;
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sg_last = scatterwalk_sg_next(sg_last);
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sg_last = sg_next(sg_last);
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}
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if (rctx->trailing_buf_len) {
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if (cp->ce_support.aligned_only) {
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@ -4463,7 +4471,7 @@ static struct crypto_alg _qcrypto_ablk_cipher_xts_algo = {
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},
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},
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};
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#if 0
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static struct crypto_alg _qcrypto_aead_sha1_hmac_algos[] = {
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{
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.cra_name = "authenc(hmac(sha1),cbc(aes))",
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@ -4670,7 +4678,7 @@ static struct crypto_alg _qcrypto_aead_rfc4309_ccm_algo = {
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}
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}
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};
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#endif
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static int _qcrypto_probe(struct platform_device *pdev)
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{
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@ -4891,6 +4899,7 @@ static int _qcrypto_probe(struct platform_device *pdev)
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}
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/* register crypto aead (hmac-sha1) algorithms the device supports */
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#if 0
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if (cp->ce_support.sha1_hmac_20 || cp->ce_support.sha1_hmac
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|| cp->ce_support.sha_hmac) {
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for (i = 0; i < ARRAY_SIZE(_qcrypto_aead_sha1_hmac_algos);
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@ -4966,7 +4975,7 @@ static int _qcrypto_probe(struct platform_device *pdev)
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}
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}
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}
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#endif
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if ((cp->ce_support.sha_hmac) || (cp->platform_support.sha_hmac)) {
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/* register crypto hmac algorithms the device supports */
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for (i = 0; i < ARRAY_SIZE(_qcrypto_sha_hmac_algos); i++) {
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@ -5009,6 +5018,7 @@ static int _qcrypto_probe(struct platform_device *pdev)
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* Register crypto cipher (aes-ccm) algorithms the
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* device supports
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*/
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#if 0
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if (cp->ce_support.aes_ccm) {
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struct qcrypto_alg *q_alg;
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@ -5070,7 +5080,7 @@ static int _qcrypto_probe(struct platform_device *pdev)
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q_alg->cipher_alg.cra_driver_name);
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}
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}
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#endif
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mutex_unlock(&cp->engine_lock);
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@ -27,16 +27,16 @@
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int qcrypto_cipher_set_device(struct ablkcipher_request *req, unsigned int dev);
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int qcrypto_ahash_set_device(struct ahash_request *req, unsigned int dev);
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int qcrypto_aead_set_device(struct aead_request *req, unsigned int dev);
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/*int qcrypto_aead_set_device(struct aead_request *req, unsigned int dev);*/
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int qcrypto_cipher_set_flag(struct ablkcipher_request *req, unsigned int flags);
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int qcrypto_ahash_set_flag(struct ahash_request *req, unsigned int flags);
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int qcrypto_aead_set_flag(struct aead_request *req, unsigned int flags);
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/*int qcrypto_aead_set_flag(struct aead_request *req, unsigned int flags);*/
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int qcrypto_cipher_clear_flag(struct ablkcipher_request *req,
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unsigned int flags);
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int qcrypto_ahash_clear_flag(struct ahash_request *req, unsigned int flags);
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int qcrypto_aead_clear_flag(struct aead_request *req, unsigned int flags);
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/*int qcrypto_aead_clear_flag(struct aead_request *req, unsigned int flags);*/
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struct crypto_engine_entry {
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u32 hw_instance;
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