From 0d5d87098926b7e9501529556cd90e4fd8ca189d Mon Sep 17 00:00:00 2001 From: Xiaojun Sang Date: Wed, 16 Nov 2016 15:10:20 +0800 Subject: [PATCH 01/51] ASoC: qdsp6v2: prevent null pointer dereference for _vol_cmds In case of memory allocation failure, _vol_cmd_cnt is not reset. In _volume_cmds_free, null pointer dereference would happen for _vol_cmds[i]. To prevent it, reset _vol_cmd_cnt when memory allocation fails. CRs-Fixed: 1089598 Change-Id: Icb998549cdb999c6db2fd52aef505f200e630da5 Signed-off-by: Xiaojun Sang --- sound/soc/msm/qdsp6v2/msm-dts-eagle.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/sound/soc/msm/qdsp6v2/msm-dts-eagle.c b/sound/soc/msm/qdsp6v2/msm-dts-eagle.c index 7a23a170be67..dfa4bb23c45d 100644 --- a/sound/soc/msm/qdsp6v2/msm-dts-eagle.c +++ b/sound/soc/msm/qdsp6v2/msm-dts-eagle.c @@ -234,7 +234,8 @@ static s32 _volume_cmds_alloc1(s32 size) if (_vol_cmds) { _vol_cmds_d = kzalloc(_vol_cmd_cnt * sizeof(struct vol_cmds_d), GFP_KERNEL); - } + } else + _vol_cmd_cnt = 0; if (_vol_cmds_d) return 0; _volume_cmds_free(); From 767cab94938f4b25fdb370f1c025ab8f32007cdd Mon Sep 17 00:00:00 2001 From: Patrick Daly Date: Thu, 13 Oct 2016 20:03:50 -0700 Subject: [PATCH 02/51] iommu: iommu-debug: Allow full dma_addr_t sized address for atos Iommu addresses are unsigned numbers. Therefore use the unsigned variants of the kstrto*_from_user functions. Change-Id: I9a34d522a8dc7e2efca95b5a1ccb6a7a2e260b42 Reported-by: Jordan Crouse Signed-off-by: Patrick Daly --- drivers/iommu/iommu-debug.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/iommu-debug.c b/drivers/iommu/iommu-debug.c index 7b0c1ae5a48d..a2b89c9d347a 100644 --- a/drivers/iommu/iommu-debug.c +++ b/drivers/iommu/iommu-debug.c @@ -454,13 +454,13 @@ static inline void iommu_debug_destroy_tracking(void) { } #ifdef CONFIG_64BIT #define kstrtoux kstrtou64 -#define kstrtox_from_user kstrtoll_from_user +#define kstrtox_from_user kstrtoull_from_user #define kstrtosize_t kstrtoul #else #define kstrtoux kstrtou32 -#define kstrtox_from_user kstrtoint_from_user +#define kstrtox_from_user kstrtouint_from_user #define kstrtosize_t kstrtouint #endif From 0d0dfec04b7b3531f5cc1b5e3f57d7ca1c20ae0f Mon Sep 17 00:00:00 2001 From: Patrick Daly Date: Wed, 23 Nov 2016 15:04:24 -0800 Subject: [PATCH 03/51] iommu: io-pgtable-arm: Use correct bitmask for pgd entry Ensure that the bits larger than cfg->ias are masked out before mapping an address in a pagetable. This is required in order to map a sign-extended address into TTBR1; for other use cases the bits above cfg->ias are expected to be zero. Change-Id: I2463cef7e0238cf887dcc682977375eb08d6973b Signed-off-by: Patrick Daly --- drivers/iommu/io-pgtable-arm.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c index 3333f15f7f16..1cd1a18dd037 100644 --- a/drivers/iommu/io-pgtable-arm.c +++ b/drivers/iommu/io-pgtable-arm.c @@ -69,9 +69,12 @@ #define ARM_LPAE_PGD_IDX(l,d) \ ((l) == ARM_LPAE_START_LVL(d) ? ilog2(ARM_LPAE_PAGES_PER_PGD(d)) : 0) +#define ARM_LPAE_LVL_MASK(l, d) \ + ((l) == ARM_LPAE_START_LVL(d) ? (1 << (d)->pgd_bits) - 1 : \ + (1 << (d)->bits_per_level) - 1) #define ARM_LPAE_LVL_IDX(a,l,d) \ (((u64)(a) >> ARM_LPAE_LVL_SHIFT(l,d)) & \ - ((1 << ((d)->bits_per_level + ARM_LPAE_PGD_IDX(l,d))) - 1)) + ARM_LPAE_LVL_MASK(l, d)) /* Calculate the block/page mapping size at level l for pagetable in d. */ #define ARM_LPAE_BLOCK_SIZE(l,d) \ @@ -197,6 +200,7 @@ struct arm_lpae_io_pgtable { struct io_pgtable iop; int levels; + unsigned int pgd_bits; size_t pgd_size; unsigned long pg_shift; unsigned long bits_per_level; @@ -913,6 +917,7 @@ arm_lpae_alloc_pgtable(struct io_pgtable_cfg *cfg) /* Calculate the actual size of our pgd (without concatenation) */ pgd_bits = va_bits - (data->bits_per_level * (data->levels - 1)); + data->pgd_bits = pgd_bits; data->pgd_size = 1UL << (pgd_bits + ilog2(sizeof(arm_lpae_iopte))); data->iop.ops = (struct io_pgtable_ops) { From 414d28c327cf7b339e202d20bc2797405a00f576 Mon Sep 17 00:00:00 2001 From: David Dai Date: Wed, 30 Nov 2016 12:47:01 -0800 Subject: [PATCH 04/51] msm: msm_bus: Reverse QoS Clocks Disabling Order Reverse the order in which the clocks needed for QoS programming are being disabled. This is done to resolve certain clocks being stuck on due to SlaveReady FSM enabled. Change-Id: I2d414689ad7ec2167b3974ae0f40338075609046 Signed-off-by: David Dai --- drivers/soc/qcom/msm_bus/msm_bus_fabric_adhoc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/soc/qcom/msm_bus/msm_bus_fabric_adhoc.c b/drivers/soc/qcom/msm_bus/msm_bus_fabric_adhoc.c index fdb84b634254..06657a666f2e 100644 --- a/drivers/soc/qcom/msm_bus/msm_bus_fabric_adhoc.c +++ b/drivers/soc/qcom/msm_bus/msm_bus_fabric_adhoc.c @@ -515,12 +515,12 @@ static int msm_bus_disable_node_qos_clk(struct msm_bus_node_device_type *node) goto exit_disable_node_qos_clk; } - for (i = 0; i < node->num_node_qos_clks; i++) + for (i = node->num_node_qos_clks - 1; i >= 0; i--) ret = disable_nodeclk(&node->node_qos_clks[i]); bus_node = to_msm_bus_node(node->node_info->bus_device); - for (i = 0; i < bus_node->num_node_qos_clks; i++) + for (i = bus_node->num_node_qos_clks - 1; i >= 0; i--) ret = disable_nodeclk(&bus_node->node_qos_clks[i]); exit_disable_node_qos_clk: From 232554ded3f435276a9d3135c27167808167bfea Mon Sep 17 00:00:00 2001 From: Deepak Kushwah Date: Thu, 1 Dec 2016 13:59:38 +0530 Subject: [PATCH 05/51] msm: vidc: Fix kw issues Currently we are using the argument passed to the function to fill the array values as is without checking for the sanity. This commit will add a sanity check on function argument to avoid array index out of bound access. Change-Id: I5f23f036441a67a3f3828cc432ea57c1c06bc8ae CRs-Fixed: 1096134 Signed-off-by: Deepak Kushwah --- drivers/media/platform/msm/vidc/msm_vidc.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/media/platform/msm/vidc/msm_vidc.c b/drivers/media/platform/msm/vidc/msm_vidc.c index 7bc1fe1af26d..908bd961905b 100644 --- a/drivers/media/platform/msm/vidc/msm_vidc.c +++ b/drivers/media/platform/msm/vidc/msm_vidc.c @@ -318,6 +318,10 @@ err_invalid_input: static inline void populate_buf_info(struct buffer_info *binfo, struct v4l2_buffer *b, u32 i) { + if (i >= VIDEO_MAX_PLANES) { + dprintk(VIDC_ERR, "%s: Invalid input\n", __func__); + return; + } binfo->type = b->type; binfo->fd[i] = b->m.planes[i].reserved[0]; binfo->buff_off[i] = b->m.planes[i].reserved[1]; From 3522bcb2dd97919b98a5ed3a396345c301b15abf Mon Sep 17 00:00:00 2001 From: Aditya Bavanari Date: Wed, 9 Nov 2016 18:49:36 +0530 Subject: [PATCH 06/51] ASoc: msm: Add changes to support multiple meta key value pairs Add changes to get the cal_block on the basis of meta key and set the license in core with the obtained cal_block CRs-Fixed: 1093003 Change-Id: I7c931ca0ad4eed4da9252a05ee426d2ef4bd10b1 Signed-off-by: Aditya Bavanari --- sound/soc/msm/qdsp6v2/q6core.c | 44 +++++++++++++++++++++------------- 1 file changed, 27 insertions(+), 17 deletions(-) diff --git a/sound/soc/msm/qdsp6v2/q6core.c b/sound/soc/msm/qdsp6v2/q6core.c index cc7616f1d897..9782fa26a2e9 100644 --- a/sound/soc/msm/qdsp6v2/q6core.c +++ b/sound/soc/msm/qdsp6v2/q6core.c @@ -193,6 +193,31 @@ void ocm_core_open(void) pr_err("%s: Unable to register CORE\n", __func__); } +struct cal_block_data *cal_utils_get_cal_block_by_key( + struct cal_type_data *cal_type, uint32_t key) +{ + struct list_head *ptr, *next; + struct cal_block_data *cal_block = NULL; + struct audio_cal_info_metainfo *metainfo; + + list_for_each_safe(ptr, next, + &cal_type->cal_blocks) { + + cal_block = list_entry(ptr, + struct cal_block_data, list); + metainfo = (struct audio_cal_info_metainfo *) + cal_block->cal_info; + if (metainfo->nKey != key) { + pr_debug("%s: metainfo key mismatch!!! found:%x, needed:%x\n", + __func__, metainfo->nKey, key); + } else { + pr_debug("%s: metainfo key match found", __func__); + return cal_block; + } + } + return NULL; +} + int32_t core_set_license(uint32_t key, uint32_t module_id) { struct avcs_cmd_set_license *cmd_setl = NULL; @@ -210,8 +235,8 @@ int32_t core_set_license(uint32_t key, uint32_t module_id) } mutex_lock(&((q6core_lcl.cal_data[META_CAL])->lock)); - cal_block = - cal_utils_get_only_cal_block(q6core_lcl.cal_data[META_CAL]); + cal_block = cal_utils_get_cal_block_by_key( + q6core_lcl.cal_data[META_CAL], key); if (cal_block == NULL || cal_block->cal_data.kvaddr == NULL || cal_block->cal_data.size <= 0) { @@ -219,21 +244,6 @@ int32_t core_set_license(uint32_t key, uint32_t module_id) rc = -EINVAL; goto cal_data_unlock; } - metainfo = (struct audio_cal_info_metainfo *)cal_block->cal_info; - if (metainfo == NULL) { - pr_err("%s: No metainfo!!!", __func__); - rc = -EINVAL; - goto cal_data_unlock; - } - if (metainfo->nKey != key) { - pr_err("%s: metainfo key mismatch!!! found:%x, needed:%x\n", - __func__, metainfo->nKey, key); - rc = -EINVAL; - goto cal_data_unlock; - } else if (key == 0) { - pr_err("%s: metainfo key is %d a invalid key", __func__, key); - goto cal_data_unlock; - } packet_size = sizeof(struct avcs_cmd_set_license) + cal_block->cal_data.size; From a0b2898fbcffd6b16491aeb46b34f778e1c19b85 Mon Sep 17 00:00:00 2001 From: Subhash Jadavani Date: Wed, 30 Nov 2016 18:28:20 -0800 Subject: [PATCH 07/51] scsi: ufs: fix shutdown race condition New requests coming after/in parallel to shutdown are being returned with DID_ERROR, but this causes the request to be requeued and retried. These requests are getting pulled by the shutdown context since the PON request is inserted at the head of the queue and the queue is run for processing. The queuecommand in ufs driver allows requests in the context of shutdown as PON has to be sent to the device, but this retried regular request also ends up getting submitted after PON which fails and causes issues in err handling. Fix this by not relying on the context but looking for the target lun of the request. Allow only requests directed towards well known device lun (where PON will be sent) and block all other requests. Also make sure we mark the shutdown processing first before taking the write lock so that we can appropriately fail the regular request. Change-Id: Iaa442e8e92310ea0761c27af8fda57ffcadadb3d Signed-off-by: Subhash Jadavani Signed-off-by: Venkat Gopalakrishnan --- drivers/scsi/ufs/ufshcd.c | 32 ++++++++++++++++---------------- drivers/scsi/ufs/ufshcd.h | 1 - 2 files changed, 16 insertions(+), 17 deletions(-) diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c index 06defae6d5ba..2c86606ecd2e 100644 --- a/drivers/scsi/ufs/ufshcd.c +++ b/drivers/scsi/ufs/ufshcd.c @@ -2697,10 +2697,9 @@ static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id) * Lock is predominantly held by shutdown context thus, ensuring * that no requests from any other context may sneak through. */ -static void ufshcd_get_write_lock(struct ufs_hba *hba) +static inline void ufshcd_get_write_lock(struct ufs_hba *hba) { down_write(&hba->lock); - hba->issuing_task = current; } /** @@ -2710,18 +2709,19 @@ static void ufshcd_get_write_lock(struct ufs_hba *hba) * * Returns 1 if acquired, < 0 on contention * - * After shutdown's initiated, allow requests only from shutdown - * context. The sync between scaling & issue is maintained + * After shutdown's initiated, allow requests only directed to the + * well known device lun. The sync between scaling & issue is maintained * as is and this restructuring syncs shutdown with these too. */ -static int ufshcd_get_read_lock(struct ufs_hba *hba) +static int ufshcd_get_read_lock(struct ufs_hba *hba, u64 lun) { int err = 0; err = down_read_trylock(&hba->lock); if (err > 0) goto out; - if (hba->issuing_task == current) + /* let requests for well known device lun to go through */ + if (ufshcd_scsi_to_upiu_lun(lun) == UFS_UPIU_UFS_DEVICE_WLUN) return 0; else if (!ufshcd_is_shutdown_ongoing(hba)) return -EAGAIN; @@ -2729,7 +2729,6 @@ static int ufshcd_get_read_lock(struct ufs_hba *hba) return -EPERM; out: - hba->issuing_task = current; return err; } @@ -2742,10 +2741,7 @@ out: */ static inline void ufshcd_put_read_lock(struct ufs_hba *hba) { - if (!ufshcd_is_shutdown_ongoing(hba)) { - hba->issuing_task = NULL; - up_read(&hba->lock); - } + up_read(&hba->lock); } /** @@ -2762,6 +2758,7 @@ static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) unsigned long flags; int tag; int err = 0; + bool has_read_lock = false; hba = shost_priv(host); @@ -2773,7 +2770,7 @@ static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) BUG(); } - err = ufshcd_get_read_lock(hba); + err = ufshcd_get_read_lock(hba, cmd->device->lun); if (unlikely(err < 0)) { if (err == -EPERM) { set_host_byte(cmd, DID_ERROR); @@ -2782,6 +2779,8 @@ static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) } if (err == -EAGAIN) return SCSI_MLQUEUE_HOST_BUSY; + } else if (err == 1) { + has_read_lock = true; } spin_lock_irqsave(hba->host->host_lock, flags); @@ -2922,7 +2921,8 @@ static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) out_unlock: spin_unlock_irqrestore(hba->host->host_lock, flags); out: - ufshcd_put_read_lock(hba); + if (has_read_lock) + ufshcd_put_read_lock(hba); return err; } @@ -8808,13 +8808,13 @@ int ufshcd_shutdown(struct ufs_hba *hba) pm_runtime_get_sync(hba->dev); ufshcd_hold_all(hba); /** - * (1) Acquire the lock to stop any more requests - * (2) Set state to shutting down + * (1) Set state to shutting down + * (2) Acquire the lock to stop any more requests * (3) Suspend clock scaling * (4) Wait for all issued requests to complete */ - ufshcd_get_write_lock(hba); ufshcd_mark_shutdown_ongoing(hba); + ufshcd_get_write_lock(hba); ufshcd_scsi_block_requests(hba); ufshcd_suspend_clkscaling(hba); ret = ufshcd_wait_for_doorbell_clr(hba, U64_MAX); diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h index c5eb21d8a0fe..81eab2cbb6cb 100644 --- a/drivers/scsi/ufs/ufshcd.h +++ b/drivers/scsi/ufs/ufshcd.h @@ -897,7 +897,6 @@ struct ufs_hba { /* sync b/w diff contexts */ struct rw_semaphore lock; - struct task_struct *issuing_task; unsigned long shutdown_in_prog; struct reset_control *core_reset; From 9f45a559c7f5ec309bba67fd4ed1bc7e7f0fd95e Mon Sep 17 00:00:00 2001 From: Xiaojun Sang Date: Tue, 8 Nov 2016 17:02:26 +0800 Subject: [PATCH 08/51] ARM: dts: msm: add sb_4_tx_vi to support VI recording at msm8998 Slimbus 4 carries V-sense and I-sense signal from speaker. For VI sense recording, sb_4_tx_vi is added. CRs-Fixed: 1087025 Change-Id: I49842df0af73a3124e734632dc3c314e6f5761a1 Signed-off-by: Xiaojun Sang --- arch/arm/boot/dts/qcom/msm-audio-lpass.dtsi | 5 +++++ arch/arm/boot/dts/qcom/msm8998-audio.dtsi | 8 ++++++-- 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom/msm-audio-lpass.dtsi b/arch/arm/boot/dts/qcom/msm-audio-lpass.dtsi index eb8a7a98b6b4..067f2c35eecd 100644 --- a/arch/arm/boot/dts/qcom/msm-audio-lpass.dtsi +++ b/arch/arm/boot/dts/qcom/msm-audio-lpass.dtsi @@ -187,6 +187,11 @@ qcom,msm-dai-q6-dev-id = <16393>; }; + sb_4_tx_vi: qcom,msm-dai-q6-sb-4-tx-vi { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <20233>; + }; + sb_5_tx: qcom,msm-dai-q6-sb-5-tx { compatible = "qcom,msm-dai-q6-dev"; qcom,msm-dai-q6-dev-id = <16395>; diff --git a/arch/arm/boot/dts/qcom/msm8998-audio.dtsi b/arch/arm/boot/dts/qcom/msm8998-audio.dtsi index 506e37c2349a..ac1103d73166 100644 --- a/arch/arm/boot/dts/qcom/msm8998-audio.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-audio.dtsi @@ -101,7 +101,8 @@ <&dai_tert_auxpcm>, <&dai_quat_auxpcm>, <&sb_0_rx>, <&sb_0_tx>, <&sb_1_rx>, <&sb_1_tx>, <&sb_2_rx>, <&sb_2_tx>, <&sb_3_rx>, <&sb_3_tx>, - <&sb_4_rx>, <&sb_4_tx>, <&sb_5_tx>, + <&sb_4_rx>, <&sb_4_tx>, <&sb_4_tx_vi>, + <&sb_5_tx>, <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, <&afe_proxy_tx>, <&incall_record_rx>, <&incall_record_tx>, <&incall_music_rx>, @@ -122,6 +123,7 @@ "msm-dai-q6-dev.16388", "msm-dai-q6-dev.16389", "msm-dai-q6-dev.16390", "msm-dai-q6-dev.16391", "msm-dai-q6-dev.16392", "msm-dai-q6-dev.16393", + "msm-dai-q6-dev.20233", "msm-dai-q6-dev.16395", "msm-dai-q6-dev.224", "msm-dai-q6-dev.225", "msm-dai-q6-dev.241", "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771", @@ -212,7 +214,8 @@ <&dai_tert_auxpcm>, <&dai_quat_auxpcm>, <&sb_0_rx>, <&sb_0_tx>, <&sb_1_rx>, <&sb_1_tx>, <&sb_2_rx>, <&sb_2_tx>, <&sb_3_rx>, <&sb_3_tx>, - <&sb_4_rx>, <&sb_4_tx>, <&sb_5_tx>, + <&sb_4_rx>, <&sb_4_tx>, <&sb_4_tx_vi>, + <&sb_5_tx>, <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, <&afe_proxy_tx>, <&incall_record_rx>, <&incall_record_tx>, <&incall_music_rx>, @@ -233,6 +236,7 @@ "msm-dai-q6-dev.16388", "msm-dai-q6-dev.16389", "msm-dai-q6-dev.16390", "msm-dai-q6-dev.16391", "msm-dai-q6-dev.16392", "msm-dai-q6-dev.16393", + "msm-dai-q6-dev.20233", "msm-dai-q6-dev.16395", "msm-dai-q6-dev.224", "msm-dai-q6-dev.225", "msm-dai-q6-dev.241", "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771", From 641fb2817f52b99bee9abec2a287b9da9bd4e3b1 Mon Sep 17 00:00:00 2001 From: Xiaojun Sang Date: Tue, 8 Nov 2016 17:27:57 +0800 Subject: [PATCH 09/51] ASoC: soc: qdsp6v2: add support for slimbus VI recording Add a new dailink for slimbus VI sense recording. SLIMBUS_TX_VI and SLIMBUS_4_TX can coexist. VI recording and speaker protection cannot work simultaneoulsy due to shared physical afe port. CRs-Fixed: 1087025 Change-Id: If074b7042e09d1e69147546461e6fa42d427350e Signed-off-by: Xiaojun Sang --- include/sound/apr_audio-v2.h | 1 + sound/soc/msm/qdsp6v2/msm-dai-q6-v2.c | 32 ++++++++++++++++++++++ sound/soc/msm/qdsp6v2/msm-pcm-routing-v2.c | 16 +++++++++-- sound/soc/msm/qdsp6v2/msm-pcm-routing-v2.h | 2 ++ sound/soc/msm/qdsp6v2/q6afe.c | 19 +++++++++++++ sound/soc/msm/qdsp6v2/q6audio-v2.c | 3 ++ 6 files changed, 71 insertions(+), 2 deletions(-) diff --git a/include/sound/apr_audio-v2.h b/include/sound/apr_audio-v2.h index e01e16e5cebe..06d952a07c2a 100644 --- a/include/sound/apr_audio-v2.h +++ b/include/sound/apr_audio-v2.h @@ -788,6 +788,7 @@ struct adm_cmd_connect_afe_port_v5 { #define SLIMBUS_3_TX 0x4007 #define SLIMBUS_4_RX 0x4008 #define SLIMBUS_4_TX 0x4009 +#define SLIMBUS_TX_VI 0x4f09 #define SLIMBUS_5_RX 0x400a #define SLIMBUS_5_TX 0x400b #define SLIMBUS_6_RX 0x400c diff --git a/sound/soc/msm/qdsp6v2/msm-dai-q6-v2.c b/sound/soc/msm/qdsp6v2/msm-dai-q6-v2.c index f1f2fd908eca..26cdd0fa7ad7 100644 --- a/sound/soc/msm/qdsp6v2/msm-dai-q6-v2.c +++ b/sound/soc/msm/qdsp6v2/msm-dai-q6-v2.c @@ -1757,6 +1757,7 @@ static int msm_dai_q6_hw_params(struct snd_pcm_substream *substream, case SLIMBUS_2_TX: case SLIMBUS_3_TX: case SLIMBUS_4_TX: + case SLIMBUS_TX_VI: case SLIMBUS_5_TX: case SLIMBUS_6_TX: case SLIMBUS_7_TX: @@ -1906,6 +1907,7 @@ static int msm_dai_q6_set_channel_map(struct snd_soc_dai *dai, case SLIMBUS_2_TX: case SLIMBUS_3_TX: case SLIMBUS_4_TX: + case SLIMBUS_TX_VI: case SLIMBUS_5_TX: case SLIMBUS_6_TX: case SLIMBUS_7_TX: @@ -2283,6 +2285,9 @@ static const struct snd_kcontrol_new sb_config_controls[] = { msm_dai_q6_cal_info_get, msm_dai_q6_cal_info_put), SOC_ENUM_EXT("SLIM_2_RX Format", sb_config_enum[0], + msm_dai_q6_sb_format_get, + msm_dai_q6_sb_format_put), + SOC_ENUM_EXT("SLIM_TX_VI Format", sb_config_enum[0], msm_dai_q6_sb_format_get, msm_dai_q6_sb_format_put) }; @@ -2336,6 +2341,11 @@ static int msm_dai_q6_dai_probe(struct snd_soc_dai *dai) snd_ctl_new1(&sb_config_controls[0], dai_data)); break; + case SLIMBUS_TX_VI: + rc = snd_ctl_add(dai->component->card->snd_card, + snd_ctl_new1(&sb_config_controls[3], + dai_data)); + break; case SLIMBUS_2_RX: rc = snd_ctl_add(dai->component->card->snd_card, snd_ctl_new1(&sb_config_controls[1], @@ -3216,6 +3226,25 @@ static struct snd_soc_dai_driver msm_dai_q6_slimbus_tx_dai[] = { .probe = msm_dai_q6_dai_probe, .remove = msm_dai_q6_dai_remove, }, + { + .capture = { + .stream_name = "Slimbus VI Capture", + .aif_name = "SLIMBUS_TX_VI", + .rates = SNDRV_PCM_RATE_8000_96000 | + SNDRV_PCM_RATE_192000, + .formats = SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S24_LE | + SNDRV_PCM_FMTBIT_S32_LE, + .channels_min = 1, + .channels_max = 4, + .rate_min = 8000, + .rate_max = 192000, + }, + .ops = &msm_dai_q6_ops, + .id = SLIMBUS_TX_VI, + .probe = msm_dai_q6_dai_probe, + .remove = msm_dai_q6_dai_remove, + }, { .capture = { .stream_name = "Slimbus5 Capture", @@ -4523,6 +4552,9 @@ register_slim_playback: case SLIMBUS_4_TX: strlcpy(stream_name, "Slimbus4 Capture", 80); goto register_slim_capture; + case SLIMBUS_TX_VI: + strlcpy(stream_name, "Slimbus VI Capture", 80); + goto register_slim_capture; case SLIMBUS_5_TX: strlcpy(stream_name, "Slimbus5 Capture", 80); goto register_slim_capture; diff --git a/sound/soc/msm/qdsp6v2/msm-pcm-routing-v2.c b/sound/soc/msm/qdsp6v2/msm-pcm-routing-v2.c index a456cc2ab857..d1cab40f2d14 100644 --- a/sound/soc/msm/qdsp6v2/msm-pcm-routing-v2.c +++ b/sound/soc/msm/qdsp6v2/msm-pcm-routing-v2.c @@ -80,14 +80,15 @@ enum { #define SLIMBUS_2_TX_TEXT "SLIMBUS_2_TX" #define SLIMBUS_3_TX_TEXT "SLIMBUS_3_TX" #define SLIMBUS_4_TX_TEXT "SLIMBUS_4_TX" +#define SLIMBUS_TX_VI_TEXT "SLIMBUS_TX_VI" #define SLIMBUS_5_TX_TEXT "SLIMBUS_5_TX" #define TERT_MI2S_TX_TEXT "TERT_MI2S_TX" #define LSM_FUNCTION_TEXT "LSM Function" static const char * const mad_audio_mux_text[] = { "None", SLIMBUS_0_TX_TEXT, SLIMBUS_1_TX_TEXT, SLIMBUS_2_TX_TEXT, - SLIMBUS_3_TX_TEXT, SLIMBUS_4_TX_TEXT, SLIMBUS_5_TX_TEXT, - TERT_MI2S_TX_TEXT + SLIMBUS_3_TX_TEXT, SLIMBUS_4_TX_TEXT, SLIMBUS_TX_VI_TEXT, + SLIMBUS_5_TX_TEXT, TERT_MI2S_TX_TEXT }; struct msm_pcm_route_bdai_pp_params { @@ -110,6 +111,9 @@ static int msm_routing_get_bit_width(unsigned int format) int bit_width; switch (format) { + case SNDRV_PCM_FORMAT_S32_LE: + bit_width = 32; + break; case SNDRV_PCM_FORMAT_S24_LE: case SNDRV_PCM_FORMAT_S24_3LE: bit_width = 24; @@ -495,6 +499,7 @@ struct msm_pcm_routing_bdai_data msm_bedais[MSM_BACKEND_DAI_MAX] = { LPASS_BE_INT6_MI2S_RX}, { AFE_PORT_ID_INT6_MI2S_TX, 0, 0, {0}, 0, 0, 0, 0, 0, LPASS_BE_INT6_MI2S_TX}, + { SLIMBUS_TX_VI, 0, 0, {0}, 0, 0, 0, 0, 0, LPASS_BE_SLIMBUS_TX_VI}, }; /* Track ASM playback & capture sessions of DAI */ @@ -4741,6 +4746,9 @@ static const struct snd_kcontrol_new mmul1_mixer_controls[] = { SOC_SINGLE_EXT("SLIM_4_TX", MSM_BACKEND_DAI_SLIMBUS_4_TX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_SINGLE_EXT("SLIM_TX_VI", MSM_BACKEND_DAI_SLIMBUS_TX_VI, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), SOC_SINGLE_EXT("SLIM_6_TX", MSM_BACKEND_DAI_SLIMBUS_6_TX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), @@ -8864,6 +8872,8 @@ static const struct snd_soc_dapm_widget msm_qdsp6_widgets[] = { 0, 0, 0, 0), SND_SOC_DAPM_AIF_IN("SLIMBUS_4_TX", "Slimbus4 Capture", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SLIMBUS_TX_VI", "Slimbus VI Capture", + 0, 0, 0, 0), SND_SOC_DAPM_AIF_IN("SENARY_TX", "Senary_mi2s Capture", 0, 0, 0, 0), SND_SOC_DAPM_AIF_IN("SLIMBUS_5_TX", "Slimbus5 Capture", 0, 0, 0, 0), @@ -9545,6 +9555,7 @@ static const struct snd_soc_dapm_route intercon[] = { {"MultiMedia4 Mixer", "VOC_REC_DL", "INCALL_RECORD_RX"}, {"MultiMedia8 Mixer", "VOC_REC_DL", "INCALL_RECORD_RX"}, {"MultiMedia1 Mixer", "SLIM_4_TX", "SLIMBUS_4_TX"}, + {"MultiMedia1 Mixer", "SLIM_TX_VI", "SLIMBUS_TX_VI"}, {"MultiMedia1 Mixer", "SLIM_6_TX", "SLIMBUS_6_TX"}, {"MultiMedia1 Mixer", "SLIM_7_TX", "SLIMBUS_7_TX"}, {"MultiMedia1 Mixer", "SLIM_8_TX", "SLIMBUS_8_TX"}, @@ -11281,6 +11292,7 @@ static const struct snd_soc_dapm_route intercon[] = { {"SLIMBUS_1_TX", NULL, "BE_IN" }, {"SLIMBUS_3_TX", NULL, "BE_IN" }, {"SLIMBUS_4_TX", NULL, "BE_IN" }, + {"SLIMBUS_TX_VI", NULL, "BE_IN" }, {"SLIMBUS_5_TX", NULL, "BE_IN" }, {"SLIMBUS_6_TX", NULL, "BE_IN" }, {"SLIMBUS_7_TX", NULL, "BE_IN" }, diff --git a/sound/soc/msm/qdsp6v2/msm-pcm-routing-v2.h b/sound/soc/msm/qdsp6v2/msm-pcm-routing-v2.h index d64fd640618e..0bb069154512 100644 --- a/sound/soc/msm/qdsp6v2/msm-pcm-routing-v2.h +++ b/sound/soc/msm/qdsp6v2/msm-pcm-routing-v2.h @@ -65,6 +65,7 @@ #define LPASS_BE_SLIMBUS_4_RX "SLIMBUS_4_RX" #define LPASS_BE_SLIMBUS_4_TX "SLIMBUS_4_TX" #define LPASS_BE_SLIMBUS_5_RX "SLIMBUS_5_RX" +#define LPASS_BE_SLIMBUS_TX_VI "SLIMBUS_TX_VI" #define LPASS_BE_SLIMBUS_5_TX "SLIMBUS_5_TX" #define LPASS_BE_SLIMBUS_6_RX "SLIMBUS_6_RX" #define LPASS_BE_SLIMBUS_6_TX "SLIMBUS_6_TX" @@ -355,6 +356,7 @@ enum { MSM_BACKEND_DAI_INT5_MI2S_TX, MSM_BACKEND_DAI_INT6_MI2S_RX, MSM_BACKEND_DAI_INT6_MI2S_TX, + MSM_BACKEND_DAI_SLIMBUS_TX_VI, MSM_BACKEND_DAI_MAX, }; diff --git a/sound/soc/msm/qdsp6v2/q6afe.c b/sound/soc/msm/qdsp6v2/q6afe.c index 75dc7cf059e3..b22903b15308 100644 --- a/sound/soc/msm/qdsp6v2/q6afe.c +++ b/sound/soc/msm/qdsp6v2/q6afe.c @@ -503,6 +503,7 @@ int afe_get_port_type(u16 port_id) case SLIMBUS_2_TX: case SLIMBUS_3_TX: case SLIMBUS_4_TX: + case SLIMBUS_TX_VI: case SLIMBUS_5_TX: case SLIMBUS_6_TX: case SLIMBUS_7_TX: @@ -607,6 +608,7 @@ int afe_sizeof_cfg_cmd(u16 port_id) case SLIMBUS_3_TX: case SLIMBUS_4_RX: case SLIMBUS_4_TX: + case SLIMBUS_TX_VI: case SLIMBUS_5_RX: case SLIMBUS_5_TX: case SLIMBUS_6_RX: @@ -2785,6 +2787,13 @@ static int __afe_port_start(u16 port_id, union afe_port_config *afe_config, return ret; } + /* + * Virtual SLIMBUS_TX_VI shares afe port with SLIMBUS_4_TX. + * port_id changes to physical port of SLIMBUS_4_TX. + */ + if (port_id == SLIMBUS_TX_VI) + port_id = SLIMBUS_4_TX; + if ((port_id == RT_PROXY_DAI_001_RX) || (port_id == RT_PROXY_DAI_002_TX)) { pr_debug("%s: before incrementing pcm_afe_instance %d"\ @@ -2950,6 +2959,7 @@ static int __afe_port_start(u16 port_id, union afe_port_config *afe_config, case SLIMBUS_3_TX: case SLIMBUS_4_RX: case SLIMBUS_4_TX: + case SLIMBUS_TX_VI: case SLIMBUS_5_RX: case SLIMBUS_5_TX: case SLIMBUS_6_RX: @@ -3143,6 +3153,7 @@ int afe_get_port_index(u16 port_id) case RT_PROXY_PORT_001_TX: return IDX_RT_PROXY_PORT_001_TX; case SLIMBUS_4_RX: return IDX_SLIMBUS_4_RX; case SLIMBUS_4_TX: return IDX_SLIMBUS_4_TX; + case SLIMBUS_TX_VI: return IDX_SLIMBUS_4_TX; case SLIMBUS_5_RX: return IDX_SLIMBUS_5_RX; case SLIMBUS_5_TX: return IDX_SLIMBUS_5_TX; case SLIMBUS_6_RX: return IDX_SLIMBUS_6_RX; @@ -5070,6 +5081,14 @@ int afe_close(int port_id) goto fail_cmd; } pr_debug("%s: port_id = 0x%x\n", __func__, port_id); + + /* + * Virtual SLIMBUS_TX_VI shares afe port with SLIMBUS_4_TX. + * port_id changes to physical port of SLIMBUS_4_TX. + */ + if (port_id == SLIMBUS_TX_VI) + port_id = SLIMBUS_4_TX; + if ((port_id == RT_PROXY_DAI_001_RX) || (port_id == RT_PROXY_DAI_002_TX)) { pr_debug("%s: before decrementing pcm_afe_instance %d\n", diff --git a/sound/soc/msm/qdsp6v2/q6audio-v2.c b/sound/soc/msm/qdsp6v2/q6audio-v2.c index 84e1178dc354..a4951dc77378 100644 --- a/sound/soc/msm/qdsp6v2/q6audio-v2.c +++ b/sound/soc/msm/qdsp6v2/q6audio-v2.c @@ -64,6 +64,7 @@ int q6audio_get_port_index(u16 port_id) case SLIMBUS_3_TX: return IDX_SLIMBUS_3_TX; case SLIMBUS_4_RX: return IDX_SLIMBUS_4_RX; case SLIMBUS_4_TX: return IDX_SLIMBUS_4_TX; + case SLIMBUS_TX_VI: return IDX_SLIMBUS_4_TX; case SLIMBUS_5_RX: return IDX_SLIMBUS_5_RX; case SLIMBUS_5_TX: return IDX_SLIMBUS_5_TX; case SLIMBUS_6_RX: return IDX_SLIMBUS_6_RX; @@ -311,6 +312,7 @@ int q6audio_get_port_id(u16 port_id) case SLIMBUS_3_TX: return AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_TX; case SLIMBUS_4_RX: return AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_RX; case SLIMBUS_4_TX: return AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_TX; + case SLIMBUS_TX_VI: return AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_TX; case SLIMBUS_5_RX: return AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_RX; case SLIMBUS_5_TX: return AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_TX; case SLIMBUS_6_RX: return AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_RX; @@ -688,6 +690,7 @@ int q6audio_validate_port(u16 port_id) case SLIMBUS_3_TX: case SLIMBUS_4_RX: case SLIMBUS_4_TX: + case SLIMBUS_TX_VI: case SLIMBUS_5_RX: case SLIMBUS_5_TX: case SLIMBUS_6_RX: From 713c5979d0a7daee762d97d62b548cceae70540a Mon Sep 17 00:00:00 2001 From: Xiaojun Sang Date: Tue, 8 Nov 2016 17:37:38 +0800 Subject: [PATCH 10/51] ASoC: soc: add a new dailink for VI recording SLIMBUS 4 TX is used for speaker protection. To enable VI recording without breaking speaker protection, a new dailink is added as non-hostless. CRs-Fixed: 1087025 Change-Id: I440b7826fb5fd4fbd55831c1e89b9b010f3b948c Signed-off-by: Xiaojun Sang --- sound/soc/msm/msm8998.c | 37 ++++++++++++++++++++++++++++++++++++- 1 file changed, 36 insertions(+), 1 deletion(-) diff --git a/sound/soc/msm/msm8998.c b/sound/soc/msm/msm8998.c index 1df839333d09..8f4f60a7c97b 100644 --- a/sound/soc/msm/msm8998.c +++ b/sound/soc/msm/msm8998.c @@ -2765,6 +2765,7 @@ static int msm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, break; case MSM_BACKEND_DAI_SLIMBUS_4_TX: + case MSM_BACKEND_DAI_SLIMBUS_TX_VI: param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, SNDRV_PCM_FORMAT_S32_LE); rate->min = rate->max = SAMPLING_RATE_8KHZ; @@ -3560,7 +3561,8 @@ static int msm_snd_hw_params(struct snd_pcm_substream *substream, /* For _tx3 case */ else if (dai_link->be_id == MSM_BACKEND_DAI_SLIMBUS_1_TX) user_set_tx_ch = slim_tx_cfg[1].channels; - else if (dai_link->be_id == MSM_BACKEND_DAI_SLIMBUS_4_TX) + else if (dai_link->be_id == MSM_BACKEND_DAI_SLIMBUS_4_TX || + dai_link->be_id == MSM_BACKEND_DAI_SLIMBUS_TX_VI) user_set_tx_ch = msm_vi_feed_tx_ch; else user_set_tx_ch = tx_ch_cnt; @@ -5259,6 +5261,22 @@ static struct snd_soc_dai_link msm_tasha_be_dai_links[] = { .ignore_pmdown_time = 1, .ignore_suspend = 1, }, + /* Slimbus VI Recording */ + { + .name = LPASS_BE_SLIMBUS_TX_VI, + .stream_name = "Slimbus VI Capture", + .cpu_dai_name = "msm-dai-q6-dev.20233", + .platform_name = "msm-pcm-routing", + .codec_name = "tasha_codec", + .codec_dai_name = "tasha_vifeedback", + .be_id = MSM_BACKEND_DAI_SLIMBUS_TX_VI, + .be_hw_params_fixup = msm_be_hw_params_fixup, + .ops = &msm_be_ops, + .ignore_suspend = 1, + .no_pcm = 1, + .dpcm_capture = 1, + .ignore_pmdown_time = 1, + }, }; static struct snd_soc_dai_link msm_tavil_be_dai_links[] = { @@ -5431,6 +5449,23 @@ static struct snd_soc_dai_link msm_tavil_be_dai_links[] = { .ignore_pmdown_time = 1, .ignore_suspend = 1, }, + + /* Slimbus VI Recording */ + { + .name = LPASS_BE_SLIMBUS_TX_VI, + .stream_name = "Slimbus VI Capture", + .cpu_dai_name = "msm-dai-q6-dev.20233", + .platform_name = "msm-pcm-routing", + .codec_name = "tavil_codec", + .codec_dai_name = "tavil_vifeedback", + .be_id = MSM_BACKEND_DAI_SLIMBUS_TX_VI, + .be_hw_params_fixup = msm_be_hw_params_fixup, + .ops = &msm_be_ops, + .ignore_suspend = 1, + .no_pcm = 1, + .dpcm_capture = 1, + .ignore_pmdown_time = 1, + }, }; static struct snd_soc_dai_link msm_wcn_be_dai_links[] = { From 254699d0266fe6cf4c5b03e16c2435535d20327a Mon Sep 17 00:00:00 2001 From: Chinmay Sawarkar Date: Mon, 5 Dec 2016 17:07:41 -0800 Subject: [PATCH 11/51] msm: vidc: Disable clocks in reverse order Clock must be disabled in the reverse order in which they are enabled. If enable/disable is unbalanced, we may trigger CLK warnings or instability. Change-Id: I4f0a0f21385c9fbf7df004dbf7abba9cb00a2448 CRs-Fixed: 1091417 Signed-off-by: Chinmay Sawarkar --- drivers/media/platform/msm/vidc/venus_boot.c | 4 ++-- drivers/media/platform/msm/vidc/venus_hfi.c | 11 +++++------ drivers/media/platform/msm/vidc/venus_hfi.h | 5 +++++ drivers/media/platform/msm/vidc/vmem/vmem.c | 4 ++-- 4 files changed, 14 insertions(+), 10 deletions(-) diff --git a/drivers/media/platform/msm/vidc/venus_boot.c b/drivers/media/platform/msm/vidc/venus_boot.c index 85c3e15edded..ea53c09ce9a1 100644 --- a/drivers/media/platform/msm/vidc/venus_boot.c +++ b/drivers/media/platform/msm/vidc/venus_boot.c @@ -137,11 +137,11 @@ static int venus_clock_prepare_enable(void) static void venus_clock_disable_unprepare(void) { - int i; struct msm_vidc_platform_resources *res = venus_data->resources; struct clock_info *cl; + int i = res->clock_set.count; - for (i = 0; i < res->clock_set.count; i++) { + for (i--; i >= 0; i--) { cl = &res->clock_set.clock_tbl[i]; clk_disable_unprepare(cl->clk); } diff --git a/drivers/media/platform/msm/vidc/venus_hfi.c b/drivers/media/platform/msm/vidc/venus_hfi.c index 520e71fdc272..eceb86b01a7c 100644 --- a/drivers/media/platform/msm/vidc/venus_hfi.c +++ b/drivers/media/platform/msm/vidc/venus_hfi.c @@ -3767,8 +3767,8 @@ static inline void __disable_unprepare_clks(struct venus_hfi_device *device) return; } - venus_hfi_for_each_clock(device, cl) { - usleep_range(100, 500); + venus_hfi_for_each_clock_reverse(device, cl) { + usleep_range(100, 500); dprintk(VIDC_DBG, "Clock: %s disable and unprepare\n", cl->name); clk_disable_unprepare(cl->clk); @@ -3778,7 +3778,7 @@ static inline void __disable_unprepare_clks(struct venus_hfi_device *device) static inline int __prepare_enable_clks(struct venus_hfi_device *device) { struct clock_info *cl = NULL, *cl_fail = NULL; - int rc = 0; + int rc = 0, c = 0; if (!device) { dprintk(VIDC_ERR, "Invalid params: %pK\n", device); return -EINVAL; @@ -3816,6 +3816,7 @@ static inline int __prepare_enable_clks(struct venus_hfi_device *device) goto fail_clk_enable; } + c++; dprintk(VIDC_DBG, "Clock: %s prepared and enabled\n", cl->name); } @@ -3824,9 +3825,7 @@ static inline int __prepare_enable_clks(struct venus_hfi_device *device) return rc; fail_clk_enable: - venus_hfi_for_each_clock(device, cl) { - if (cl_fail == cl) - break; + venus_hfi_for_each_clock_reverse_continue(device, cl, c) { usleep_range(100, 500); dprintk(VIDC_ERR, "Clock: %s disable and unprepare\n", cl->name); diff --git a/drivers/media/platform/msm/vidc/venus_hfi.h b/drivers/media/platform/msm/vidc/venus_hfi.h index 8ba763a3b61a..048f247fb0a4 100644 --- a/drivers/media/platform/msm/vidc/venus_hfi.h +++ b/drivers/media/platform/msm/vidc/venus_hfi.h @@ -187,6 +187,11 @@ struct vidc_iface_q_info { #define venus_hfi_for_each_clock_reverse(__device, __cinfo) \ venus_hfi_for_each_thing_reverse(__device, __cinfo, clock) +#define venus_hfi_for_each_clock_reverse_continue(__device, __rinfo, \ + __from) \ + venus_hfi_for_each_thing_reverse_continue(__device, __rinfo, \ + clock, __from) + /* Bus set helpers */ #define venus_hfi_for_each_bus(__device, __binfo) \ venus_hfi_for_each_thing(__device, __binfo, bus) diff --git a/drivers/media/platform/msm/vidc/vmem/vmem.c b/drivers/media/platform/msm/vidc/vmem/vmem.c index e86740fdc5ac..4e117d18751d 100644 --- a/drivers/media/platform/msm/vidc/vmem/vmem.c +++ b/drivers/media/platform/msm/vidc/vmem/vmem.c @@ -226,9 +226,9 @@ exit: static inline int __power_off(struct vmem *v) { - int c = 0; + int c = v->num_clocks; - for (c = 0; c < v->num_clocks; ++c) { + for (c--; c >= 0; --c) { clk_disable_unprepare(v->clocks[c].clk); pr_debug("Disabled clock %s\n", v->clocks[c].name); } From 126ffb778d3149bc63c5f86236866df435d39304 Mon Sep 17 00:00:00 2001 From: Subbaraman Narayanamurthy Date: Wed, 16 Nov 2016 19:30:01 -0800 Subject: [PATCH 12/51] leds: qpnp-wled: Handle OVP fault interrupt properly Sometimes, OVP fault interrupt fires as soon as WLED module is enabled. This does not really represent a harmful event. Hence add support to enable OVP fault interrupt 10 mS after enabling WLED module so that the soft start is completed. Keep the OVP fault interrupt disabled when the module is disabled. While at it, print the fault status from both OVP and short circuit interrupt handlers which might be useful. Change-Id: If3c264c6e3a2bf4b23069c0960b354f7967ecb4c Signed-off-by: Subbaraman Narayanamurthy --- drivers/leds/leds-qpnp-wled.c | 96 ++++++++++++++++++----------------- 1 file changed, 50 insertions(+), 46 deletions(-) diff --git a/drivers/leds/leds-qpnp-wled.c b/drivers/leds/leds-qpnp-wled.c index 9c14822c27b7..85b1133df4f5 100644 --- a/drivers/leds/leds-qpnp-wled.c +++ b/drivers/leds/leds-qpnp-wled.c @@ -27,17 +27,12 @@ #include #include -#define QPNP_IRQ_FLAGS (IRQF_TRIGGER_RISING | \ - IRQF_TRIGGER_FALLING | \ - IRQF_ONESHOT) - /* base addresses */ #define QPNP_WLED_CTRL_BASE "qpnp-wled-ctrl-base" #define QPNP_WLED_SINK_BASE "qpnp-wled-sink-base" /* ctrl registers */ -#define QPNP_WLED_INT_EN_SET(b) (b + 0x15) -#define QPNP_WLED_INT_EN_CLR(b) (b + 0x16) +#define QPNP_WLED_FAULT_STATUS(b) (b + 0x08) #define QPNP_WLED_EN_REG(b) (b + 0x46) #define QPNP_WLED_FDBK_OP_REG(b) (b + 0x48) #define QPNP_WLED_VREF_REG(b) (b + 0x49) @@ -114,8 +109,6 @@ #define QPNP_WLED_SWITCH_FREQ_OVERWRITE 0x80 #define QPNP_WLED_OVP_MASK GENMASK(1, 0) #define QPNP_WLED_TEST4_EN_VREF_UP 0x32 -#define QPNP_WLED_INT_EN_SET_OVP_EN 0x02 -#define QPNP_WLED_OVP_FLT_SLEEP_US 10 #define QPNP_WLED_TEST4_EN_IIND_UP 0x1 /* sink registers */ @@ -183,7 +176,7 @@ #define QPNP_WLED_MODULE_EN_REG(b) (b + 0x46) #define QPNP_WLED_MODULE_RDY_MASK 0x7F #define QPNP_WLED_MODULE_RDY_SHIFT 7 -#define QPNP_WLED_MODULE_EN_MASK 0x7F +#define QPNP_WLED_MODULE_EN_MASK BIT(7) #define QPNP_WLED_MODULE_EN_SHIFT 7 #define QPNP_WLED_DISP_SEL_MASK 0x7F #define QPNP_WLED_DISP_SEL_SHIFT 7 @@ -386,6 +379,7 @@ struct qpnp_wled { bool disp_type_amoled; bool en_ext_pfet_sc_pro; bool prev_state; + bool ovp_irq_disabled; }; /* helper to read a pmic register */ @@ -533,34 +527,29 @@ static int qpnp_wled_module_en(struct qpnp_wled *wled, u16 base_addr, bool state) { int rc; - u8 reg; - /* disable OVP fault interrupt */ - if (state) { - reg = QPNP_WLED_INT_EN_SET_OVP_EN; - rc = qpnp_wled_write_reg(wled, QPNP_WLED_INT_EN_CLR(base_addr), - reg); - if (rc) - return rc; - } - - rc = qpnp_wled_read_reg(wled, QPNP_WLED_MODULE_EN_REG(base_addr), ®); + rc = qpnp_wled_masked_write_reg(wled, + QPNP_WLED_MODULE_EN_REG(base_addr), + QPNP_WLED_MODULE_EN_MASK, + state << QPNP_WLED_MODULE_EN_SHIFT); if (rc < 0) return rc; - reg &= QPNP_WLED_MODULE_EN_MASK; - reg |= (state << QPNP_WLED_MODULE_EN_SHIFT); - rc = qpnp_wled_write_reg(wled, QPNP_WLED_MODULE_EN_REG(base_addr), reg); - if (rc) - return rc; - /* enable OVP fault interrupt */ - if (state && (wled->ovp_irq > 0)) { - udelay(QPNP_WLED_OVP_FLT_SLEEP_US); - reg = QPNP_WLED_INT_EN_SET_OVP_EN; - rc = qpnp_wled_write_reg(wled, QPNP_WLED_INT_EN_SET(base_addr), - reg); - if (rc) - return rc; + if (wled->ovp_irq > 0) { + if (state && wled->ovp_irq_disabled) { + /* + * Wait for at least 10ms before enabling OVP fault + * interrupt after enabling the module so that soft + * start is completed. Keep OVP interrupt disabled + * when the module is disabled. + */ + usleep_range(10000, 11000); + enable_irq(wled->ovp_irq); + wled->ovp_irq_disabled = false; + } else if (!state && !wled->ovp_irq_disabled) { + disable_irq(wled->ovp_irq); + wled->ovp_irq_disabled = true; + } } return 0; @@ -1027,26 +1016,44 @@ static int qpnp_wled_set_disp(struct qpnp_wled *wled, u16 base_addr) } /* ovp irq handler */ -static irqreturn_t qpnp_wled_ovp_irq(int irq, void *_wled) +static irqreturn_t qpnp_wled_ovp_irq_handler(int irq, void *_wled) { struct qpnp_wled *wled = _wled; + int rc; + u8 val; - dev_dbg(&wled->pdev->dev, "ovp detected\n"); + rc = qpnp_wled_read_reg(wled, + QPNP_WLED_FAULT_STATUS(wled->ctrl_base), &val); + if (rc < 0) { + pr_err("Error in reading WLED_FAULT_STATUS rc=%d\n", rc); + return IRQ_HANDLED; + } + pr_err("WLED OVP fault detected, fault_status= %x\n", val); return IRQ_HANDLED; } /* short circuit irq handler */ -static irqreturn_t qpnp_wled_sc_irq(int irq, void *_wled) +static irqreturn_t qpnp_wled_sc_irq_handler(int irq, void *_wled) { struct qpnp_wled *wled = _wled; + int rc; + u8 val; - dev_err(&wled->pdev->dev, - "Short circuit detected %d times\n", ++wled->sc_cnt); + rc = qpnp_wled_read_reg(wled, + QPNP_WLED_FAULT_STATUS(wled->ctrl_base), &val); + if (rc < 0) { + pr_err("Error in reading WLED_FAULT_STATUS rc=%d\n", rc); + return IRQ_HANDLED; + } + pr_err("WLED short circuit detected %d times fault_status=%x\n", + ++wled->sc_cnt, val); + mutex_lock(&wled->lock); qpnp_wled_module_en(wled, wled->ctrl_base, false); msleep(QPNP_WLED_SC_DLY_MS); qpnp_wled_module_en(wled, wled->ctrl_base, true); + mutex_unlock(&wled->lock); return IRQ_HANDLED; } @@ -1625,11 +1632,9 @@ static int qpnp_wled_config(struct qpnp_wled *wled) /* setup ovp and sc irqs */ if (wled->ovp_irq >= 0) { - rc = devm_request_threaded_irq(&wled->pdev->dev, - wled->ovp_irq, - NULL, qpnp_wled_ovp_irq, - QPNP_IRQ_FLAGS, - "qpnp_wled_ovp_irq", wled); + rc = devm_request_threaded_irq(&wled->pdev->dev, wled->ovp_irq, + NULL, qpnp_wled_ovp_irq_handler, IRQF_ONESHOT, + "qpnp_wled_ovp_irq", wled); if (rc < 0) { dev_err(&wled->pdev->dev, "Unable to request ovp(%d) IRQ(err:%d)\n", @@ -1641,9 +1646,8 @@ static int qpnp_wled_config(struct qpnp_wled *wled) if (wled->sc_irq >= 0) { wled->sc_cnt = 0; rc = devm_request_threaded_irq(&wled->pdev->dev, wled->sc_irq, - NULL, qpnp_wled_sc_irq, - QPNP_IRQ_FLAGS, - "qpnp_wled_sc_irq", wled); + NULL, qpnp_wled_sc_irq_handler, IRQF_ONESHOT, + "qpnp_wled_sc_irq", wled); if (rc < 0) { dev_err(&wled->pdev->dev, "Unable to request sc(%d) IRQ(err:%d)\n", From 48cf12d6e4f2df884ec32692e0bc918f6520b025 Mon Sep 17 00:00:00 2001 From: Rohit Kumar Date: Mon, 28 Nov 2016 12:23:18 +0530 Subject: [PATCH 13/51] ASoC: msm: qdsp6v2: Add mutex in afe_map_cal_data Add mutex_lock in afe_map_cal_data around afe_cmd_memory_map to avoid update of this_afe.status by afe_set_lpass_clk_cfg afe callback. This fixes the failure of afe_cmd_memory_map waitqueue to enter into sleep when wait_event_timeout is called as this_afe.status is already zero leading to invalid map_handle. CRs-Fixed: 1094151 Change-Id: I4833253803c162c98578ba7ce599ea1edafc1724 Signed-off-by: Rohit Kumar --- sound/soc/msm/qdsp6v2/q6afe.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/sound/soc/msm/qdsp6v2/q6afe.c b/sound/soc/msm/qdsp6v2/q6afe.c index 75dc7cf059e3..6fdf1b9dc2b6 100644 --- a/sound/soc/msm/qdsp6v2/q6afe.c +++ b/sound/soc/msm/qdsp6v2/q6afe.c @@ -6360,6 +6360,7 @@ static int afe_map_cal_data(int32_t cal_type, } + mutex_lock(&this_afe.afe_cmd_lock); atomic_set(&this_afe.mem_map_cal_index, cal_index); ret = afe_cmd_memory_map(cal_block->cal_data.paddr, cal_block->map_data.map_size); @@ -6372,10 +6373,12 @@ static int afe_map_cal_data(int32_t cal_type, __func__, &cal_block->cal_data.paddr, cal_block->map_data.map_size); + mutex_unlock(&this_afe.afe_cmd_lock); goto done; } cal_block->map_data.q6map_handle = atomic_read(&this_afe. mem_map_cal_handles[cal_index]); + mutex_unlock(&this_afe.afe_cmd_lock); done: return ret; } From fdacf60f19e9ce4326e61a9e5d5d1113d36b4525 Mon Sep 17 00:00:00 2001 From: Subbaraman Narayanamurthy Date: Wed, 16 Nov 2016 19:34:58 -0800 Subject: [PATCH 14/51] ARM: dts: msm: Specify the WLED interrupts properly for pmi8998/pm2falcon Currently, WLED short-circuit fault interrupt is not specified properly for pmi8998 and pm2falcon. Fix it. Also, specify the WLED over-voltage fault interrupt which is needed. Remove the address definitions of LAB and IBB which are not present in WLED driver anymore. Change-Id: Ia767b3f545fae04a08dc48c6d2bb5649b2ac4907 Signed-off-by: Subbaraman Narayanamurthy --- arch/arm/boot/dts/qcom/msm-pm2falcon.dtsi | 13 +++++-------- arch/arm/boot/dts/qcom/msm-pmi8998.dtsi | 15 ++++++--------- 2 files changed, 11 insertions(+), 17 deletions(-) diff --git a/arch/arm/boot/dts/qcom/msm-pm2falcon.dtsi b/arch/arm/boot/dts/qcom/msm-pm2falcon.dtsi index 79883db10d06..d254fccec077 100644 --- a/arch/arm/boot/dts/qcom/msm-pm2falcon.dtsi +++ b/arch/arm/boot/dts/qcom/msm-pm2falcon.dtsi @@ -222,15 +222,12 @@ pm2falcon_wled: qcom,leds@d800 { compatible = "qcom,qpnp-wled"; reg = <0xd800 0x100>, - <0xd900 0x100>, - <0xdc00 0x100>, - <0xde00 0x100>; + <0xd900 0x100>; reg-names = "qpnp-wled-ctrl-base", - "qpnp-wled-sink-base", - "qpnp-wled-ibb-base", - "qpnp-wled-lab-base"; - interrupts = <0x3 0xd8 0x2>; - interrupt-names = "sc-irq"; + "qpnp-wled-sink-base"; + interrupts = <0x3 0xd8 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x3 0xd8 0x2 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "ovp-irq", "sc-irq"; linux,name = "wled"; linux,default-trigger = "bkl-trigger"; qcom,fdbk-output = "auto"; diff --git a/arch/arm/boot/dts/qcom/msm-pmi8998.dtsi b/arch/arm/boot/dts/qcom/msm-pmi8998.dtsi index 725c129a28da..0dc9da9289e2 100644 --- a/arch/arm/boot/dts/qcom/msm-pmi8998.dtsi +++ b/arch/arm/boot/dts/qcom/msm-pmi8998.dtsi @@ -585,16 +585,12 @@ pmi8998_wled: qcom,leds@d800 { compatible = "qcom,qpnp-wled"; reg = <0xd800 0x100>, - <0xd900 0x100>, - <0xdc00 0x100>, - <0xde00 0x100>; + <0xd900 0x100>; reg-names = "qpnp-wled-ctrl-base", - "qpnp-wled-sink-base", - "qpnp-wled-ibb-base", - "qpnp-wled-lab-base"; - interrupts = <0x3 0xd8 0x2>; - interrupt-names = "sc-irq"; - status = "okay"; + "qpnp-wled-sink-base"; + interrupts = <0x3 0xd8 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x3 0xd8 0x2 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "ovp-irq", "sc-irq"; linux,name = "wled"; linux,default-trigger = "bkl-trigger"; qcom,fdbk-output = "auto"; @@ -614,6 +610,7 @@ qcom,en-ext-pfet-sc-pro; qcom,pmic-revid = <&pmi8998_revid>; qcom,loop-auto-gm-en; + status = "okay"; }; pmi8998_haptics: qcom,haptic@c000 { From 5f30ee1cc59c837f11081e71a4bd2a3910a86d13 Mon Sep 17 00:00:00 2001 From: Bhalchandra Gajare Date: Tue, 6 Dec 2016 17:34:35 -0800 Subject: [PATCH 15/51] ASoC: wcd-spi: fix clock disable request during shutdown It is possible that there could be pending delayed request to disable the clock while the manager driver has already raised shutdown event. In such cases, the delayed clock disable request will be made after shutdown, resulting in unclocked access on the SPI bus. Fix this by intercepting the shutdown event to flush the clock votes and disable the clock. CRs-Fixed: 1091032 Change-Id: I53a3a9aa540c10932eed7fa29ce7c6050504a9a0 Signed-off-by: Bhalchandra Gajare --- sound/soc/codecs/wcd-spi.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/sound/soc/codecs/wcd-spi.c b/sound/soc/codecs/wcd-spi.c index 70be9c98b481..614410c26a91 100644 --- a/sound/soc/codecs/wcd-spi.c +++ b/sound/soc/codecs/wcd-spi.c @@ -855,12 +855,22 @@ static int wdsp_spi_event_handler(struct device *dev, void *priv_data, void *data) { struct spi_device *spi = to_spi_device(dev); + struct wcd_spi_priv *wcd_spi = spi_get_drvdata(spi); int ret = 0; dev_dbg(&spi->dev, "%s: event type %d\n", __func__, event); switch (event) { + case WDSP_EVENT_POST_SHUTDOWN: + cancel_delayed_work_sync(&wcd_spi->clk_dwork); + WCD_SPI_MUTEX_LOCK(spi, wcd_spi->clk_mutex); + if (test_bit(WCD_SPI_CLK_STATE_ENABLED, &wcd_spi->status_mask)) + wcd_spi_clk_disable(spi); + wcd_spi->clk_users = 0; + WCD_SPI_MUTEX_UNLOCK(spi, wcd_spi->clk_mutex); + break; + case WDSP_EVENT_PRE_DLOAD_CODE: case WDSP_EVENT_PRE_DLOAD_DATA: ret = wcd_spi_clk_ctrl(spi, WCD_SPI_CLK_ENABLE, From 224cef96887dbadb06347502c82e35cbd55a24d1 Mon Sep 17 00:00:00 2001 From: Bhalchandra Gajare Date: Tue, 6 Dec 2016 17:30:36 -0800 Subject: [PATCH 16/51] ASoC: wcd934x-dsp-cntl: fix the reset sequence Currently, whenever the codec DSP is reset, the CPAR hardware block is not reset. This causes failure to boot DSP in good state. Update CPAR reset sequence to ensure CPAR is put to reset when not in use. CRs-fixed: 1091032 Change-Id: I77fea396fda6ee0eaaf0c68b11cf90f268ac1481 Signed-off-by: Bhalchandra Gajare --- sound/soc/codecs/wcd934x/wcd934x-dsp-cntl.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/sound/soc/codecs/wcd934x/wcd934x-dsp-cntl.c b/sound/soc/codecs/wcd934x/wcd934x-dsp-cntl.c index 9898c1fc7471..aa180fa3159f 100644 --- a/sound/soc/codecs/wcd934x/wcd934x-dsp-cntl.c +++ b/sound/soc/codecs/wcd934x/wcd934x-dsp-cntl.c @@ -401,6 +401,8 @@ static int wcd_cntl_clocks_enable(struct wcd_dsp_cntl *cntl) __func__, ret); goto done; } + /* Pull CPAR out of reset */ + snd_soc_update_bits(codec, WCD934X_CPE_SS_CPAR_CTL, 0x04, 0x00); /* Configure and Enable CPE FLL clock */ ret = wcd_cntl_cpe_fll_ctrl(cntl, true); @@ -422,6 +424,7 @@ err_cpe_clk: if (cntl->cdc_cb && cntl->cdc_cb->cdc_clk_en) cntl->cdc_cb->cdc_clk_en(codec, false); + snd_soc_update_bits(codec, WCD934X_CPE_SS_CPAR_CTL, 0x04, 0x04); WCD_CNTL_MUTEX_UNLOCK(codec, cntl->clk_mutex); return ret; } @@ -458,6 +461,9 @@ static int wcd_cntl_clocks_disable(struct wcd_dsp_cntl *cntl) ret = -EINVAL; cntl->is_clk_enabled = false; + + /* Put CPAR in reset */ + snd_soc_update_bits(codec, WCD934X_CPE_SS_CPAR_CTL, 0x04, 0x04); done: WCD_CNTL_MUTEX_UNLOCK(codec, cntl->clk_mutex); return ret; @@ -469,9 +475,9 @@ static void wcd_cntl_cpar_ctrl(struct wcd_dsp_cntl *cntl, struct snd_soc_codec *codec = cntl->codec; if (enable) - snd_soc_write(codec, WCD934X_CPE_SS_CPAR_CTL, 0x03); + snd_soc_update_bits(codec, WCD934X_CPE_SS_CPAR_CTL, 0x03, 0x03); else - snd_soc_write(codec, WCD934X_CPE_SS_CPAR_CTL, 0x00); + snd_soc_update_bits(codec, WCD934X_CPE_SS_CPAR_CTL, 0x03, 0x00); } static int wcd_cntl_enable_memory(struct wcd_dsp_cntl *cntl, From a1ea995e14850422d46216970a6cbb82c7ddd21d Mon Sep 17 00:00:00 2001 From: Jin Fu Date: Mon, 5 Dec 2016 19:28:20 +0800 Subject: [PATCH 17/51] ARM: dts: msm: add touch node for QTC800H in msm8998 QRD SKUK Add touch device tree node for QTC800H panel in msm8998 QRD SKUK board. Configure necessary power supply and gpio pins to enable touch panel. CRs-Fixed: 1097675 Change-Id: Ibbdb9857ea88ad65a6c3ac7c52925ab2d2c27797 Signed-off-by: Jin Fu --- arch/arm/boot/dts/qcom/msm8998-qrd-skuk.dtsi | 51 ++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm/boot/dts/qcom/msm8998-qrd-skuk.dtsi b/arch/arm/boot/dts/qcom/msm8998-qrd-skuk.dtsi index c09900597d87..f60fd10b92f8 100644 --- a/arch/arm/boot/dts/qcom/msm8998-qrd-skuk.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-qrd-skuk.dtsi @@ -153,6 +153,24 @@ qcom,wsa-devs = <&wsa881x_0211>, <&wsa881x_0213>; qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrLeft"; }; + + hbtp { + compatible = "qcom,hbtp-input"; + pinctrl-names = "pmx_ts_active","pmx_ts_suspend"; + pinctrl-0 = <&ts_rst_active>; + pinctrl-1 = <&ts_rst_suspend>; + vcc_ana-supply = <&pm8998_l28>; + vcc_dig-supply = <&pm8998_l6>; + qcom,afe-load = <20000>; + qcom,afe-vtg-min = <2850000>; + qcom,afe-vtg-max = <3000000>; + qcom,dig-load = <40000>; + qcom,dig-vtg-min = <1800000>; + qcom,dig-vtg-max = <1800000>; + qcom,fb-resume-delay-us = <10000>; + qcom,afe-power-on-delay-us = <1000>; + qcom,afe-power-off-delay-us = <6>; + }; }; &pmx_mdss { @@ -238,6 +256,39 @@ status = "okay"; }; +&tlmm { + /* add pingrp for touchscreen */ + pmx_ts_rst_active { + ts_rst_active: ts_rst_active { + mux { + pins = "gpio89"; + function = "gpio"; + }; + + config { + pins = "gpio89"; + drive-strength = <16>; + bias-pull-up; + }; + }; + }; + + pmx_ts_rst_suspend { + ts_rst_suspend: ts_rst_suspend { + mux { + pins = "gpio89"; + function = "gpio"; + }; + + config { + pins = "gpio89"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; +}; + &pm8998_vadc { chan@83 { label = "vph_pwr"; From eecdeb00e2fc24f56c27c4916b8ee5fdb1cf9c3e Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Mon, 5 Dec 2016 15:47:59 +0530 Subject: [PATCH 18/51] defconfig: Add support to enable MMCC clocks Multimedia clock controller is required to be enabled for clocks supported by multimedia clock controller clients. Change-Id: I7fa2748c113870a20f0e01ae98faf391d195003c Signed-off-by: Taniya Das --- arch/arm/configs/msmfalcon_defconfig | 1 + arch/arm64/configs/msmfalcon-perf_defconfig | 1 + arch/arm64/configs/msmfalcon_defconfig | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/arm/configs/msmfalcon_defconfig b/arch/arm/configs/msmfalcon_defconfig index b53d1bfec33e..cb1644d85ac6 100644 --- a/arch/arm/configs/msmfalcon_defconfig +++ b/arch/arm/configs/msmfalcon_defconfig @@ -472,6 +472,7 @@ CONFIG_SEEMP_CORE=y CONFIG_USB_BAM=y CONFIG_QCOM_CLK_SMD_RPM=y CONFIG_MSM_GPUCC_FALCON=y +CONFIG_MSM_MMCC_FALCON=y CONFIG_REMOTE_SPINLOCK_MSM=y CONFIG_ARM_SMMU=y CONFIG_IOMMU_DEBUG=y diff --git a/arch/arm64/configs/msmfalcon-perf_defconfig b/arch/arm64/configs/msmfalcon-perf_defconfig index 148cb523cbc9..4491b412294d 100644 --- a/arch/arm64/configs/msmfalcon-perf_defconfig +++ b/arch/arm64/configs/msmfalcon-perf_defconfig @@ -493,6 +493,7 @@ CONFIG_SEEMP_CORE=y CONFIG_USB_BAM=y CONFIG_QCOM_CLK_SMD_RPM=y CONFIG_MSM_GPUCC_FALCON=y +CONFIG_MSM_MMCC_FALCON=y CONFIG_REMOTE_SPINLOCK_MSM=y CONFIG_IOMMU_IO_PGTABLE_FAST=y CONFIG_ARM_SMMU=y diff --git a/arch/arm64/configs/msmfalcon_defconfig b/arch/arm64/configs/msmfalcon_defconfig index 26ad84e5ecca..2c03d3f9fca3 100644 --- a/arch/arm64/configs/msmfalcon_defconfig +++ b/arch/arm64/configs/msmfalcon_defconfig @@ -502,6 +502,7 @@ CONFIG_SEEMP_CORE=y CONFIG_USB_BAM=y CONFIG_QCOM_CLK_SMD_RPM=y CONFIG_MSM_GPUCC_FALCON=y +CONFIG_MSM_MMCC_FALCON=y CONFIG_REMOTE_SPINLOCK_MSM=y CONFIG_IOMMU_IO_PGTABLE_FAST=y CONFIG_IOMMU_IO_PGTABLE_FAST_SELFTEST=y From 3704dafda85f1a71d0c894fb6727b61b05b79985 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Mon, 5 Dec 2016 18:48:31 +0530 Subject: [PATCH 19/51] ARM: dts: msm: Update clock mmss node for MSMfalcon/Triton Modify the clock_mmss dummy clock to use the real clock controller for MMSS clock controller client. Use dummy clocks for RUMI platform. Change-Id: I1ec9fe1d473be79ec0a54f2b8cacfc891f5be5bb Signed-off-by: Taniya Das --- arch/arm/boot/dts/qcom/msmfalcon-rumi.dts | 5 +++++ arch/arm/boot/dts/qcom/msmfalcon.dtsi | 7 +++++-- arch/arm/boot/dts/qcom/msmtriton-rumi.dts | 5 +++++ arch/arm/boot/dts/qcom/msmtriton.dtsi | 7 +++++-- 4 files changed, 20 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/qcom/msmfalcon-rumi.dts b/arch/arm/boot/dts/qcom/msmfalcon-rumi.dts index 2b8a78ee1fdc..c24d02e203d4 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-rumi.dts +++ b/arch/arm/boot/dts/qcom/msmfalcon-rumi.dts @@ -111,3 +111,8 @@ &pmfalcon_pdphy { status = "disabled"; }; + +&clock_mmss { + compatible = "qcom,dummycc"; + clock-output-names = "mmss_clocks"; +}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon.dtsi b/arch/arm/boot/dts/qcom/msmfalcon.dtsi index a9b903e2f902..2267771684ae 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon.dtsi +++ b/arch/arm/boot/dts/qcom/msmfalcon.dtsi @@ -869,8 +869,11 @@ }; clock_mmss: clock-controller@c8c0000 { - compatible = "qcom,dummycc"; - clock-output-names = "mmss_clocks"; + compatible = "qcom,mmcc-msmfalcon"; + reg = <0xc8c0000 0x40000>; + vdd_mx_mmss-supply = <&pm2falcon_s5_level>; + vdd_dig_mmss-supply = <&pm2falcon_s3_level>; + vdda-supply = <&pmfalcon_l10>; #clock-cells = <1>; #reset-cells = <1>; }; diff --git a/arch/arm/boot/dts/qcom/msmtriton-rumi.dts b/arch/arm/boot/dts/qcom/msmtriton-rumi.dts index 491b55aab9a6..9b32c7700c82 100644 --- a/arch/arm/boot/dts/qcom/msmtriton-rumi.dts +++ b/arch/arm/boot/dts/qcom/msmtriton-rumi.dts @@ -68,3 +68,8 @@ compatible = "qcom,dummycc"; clock-output-names = "gfx_clocks"; }; + +&clock_mmss { + compatible = "qcom,dummycc"; + clock-output-names = "mmss_clocks"; +}; diff --git a/arch/arm/boot/dts/qcom/msmtriton.dtsi b/arch/arm/boot/dts/qcom/msmtriton.dtsi index d96531a5b35a..b9a1a7b99d2e 100644 --- a/arch/arm/boot/dts/qcom/msmtriton.dtsi +++ b/arch/arm/boot/dts/qcom/msmtriton.dtsi @@ -557,8 +557,11 @@ }; clock_mmss: clock-controller@c8c0000 { - compatible = "qcom,dummycc"; - clock-output-names = "mmss_clocks"; + compatible = "qcom,mmcc-msmfalcon"; + reg = <0xc8c0000 0x40000>; + vdd_mx_mmss-supply = <&pm2falcon_s5_level>; + vdd_dig_mmss-supply = <&pm2falcon_s3_level>; + vdda-supply = <&pmfalcon_l10>; #clock-cells = <1>; #reset-cells = <1>; }; From be5a91fa22e22f02e1d65ab888166f3794b4e322 Mon Sep 17 00:00:00 2001 From: Zhenhua Huang Date: Wed, 30 Nov 2016 18:29:15 +0800 Subject: [PATCH 20/51] ARM: dts: msm: Modify QRD interposer dts file for msm8998 Update regulators for clocks and usb phy. CRs-Fixed: 1096674 Change-Id: Ib205ccebaec612fd9d1d6bb1a02a4f14be8f21c1 Signed-off-by: Zhenhua Huang --- .../msm8998-v2.1-interposer-msmfalcon-qrd.dts | 207 +++++------------- ...msm8998-v2.1-interposer-msmfalcon-qrd.dtsi | 1 + 2 files changed, 55 insertions(+), 153 deletions(-) diff --git a/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-qrd.dts b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-qrd.dts index ddae02812731..013c849c4936 100644 --- a/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-qrd.dts +++ b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-qrd.dts @@ -14,6 +14,9 @@ /dts-v1/; #include "msm8998-v2.1-interposer-msmfalcon-qrd.dtsi" +#include "msm8998-interposer-pmfalcon.dtsi" +#include "msm8998-interposer-msmfalcon-audio.dtsi" +#include "msm8998-interposer-camera-sensor-mtp.dtsi" / { model = @@ -41,174 +44,72 @@ }; &clock_gcc { - /delete-property/vdd_dig-supply; - /delete-property/vdd_dig_ao-supply; + vdd_dig-supply = <&pm2falcon_s3_level>; + vdd_dig_ao-supply = <&pm2falcon_s3_level_ao>; }; &clock_mmss { - /delete-property/vdd_dig-supply; - /delete-property/vdd_mmsscc_mx-supply; + vdd_dig-supply = <&pm2falcon_s3_level>; + vdd_mmsscc_mx-supply = <&pm2falcon_s5_level>; }; &clock_gpu { - /delete-property/vdd_dig-supply; + vdd_dig-supply = <&pm2falcon_s3_level>; }; &clock_gfx { - /delete-property/vdd_mx-supply; - /delete-property/vdd_gpu_mx-supply; + /* GFX Rail = CX */ + vdd_gpucc-supply = <&pm2falcon_s3_level>; + vdd_mx-supply = <&pm2falcon_s5_level>; + vdd_gpu_mx-supply = <&pm2falcon_s5_level>; + qcom,gfxfreq-speedbin0 = + < 0 0 0 >, + < 180000000 RPM_SMD_REGULATOR_LEVEL_MIN_SVS + RPM_SMD_REGULATOR_LEVEL_SVS >, + < 257000000 RPM_SMD_REGULATOR_LEVEL_LOW_SVS + RPM_SMD_REGULATOR_LEVEL_SVS >, + < 342000000 RPM_SMD_REGULATOR_LEVEL_SVS + RPM_SMD_REGULATOR_LEVEL_SVS >, + < 414000000 RPM_SMD_REGULATOR_LEVEL_SVS_PLUS + RPM_SMD_REGULATOR_LEVEL_SVS >, + < 515000000 RPM_SMD_REGULATOR_LEVEL_NOM + RPM_SMD_REGULATOR_LEVEL_NOM >, + < 596000000 RPM_SMD_REGULATOR_LEVEL_NOM_PLUS + RPM_SMD_REGULATOR_LEVEL_NOM >, + < 670000000 RPM_SMD_REGULATOR_LEVEL_TURBO + RPM_SMD_REGULATOR_LEVEL_TURBO >, + < 710000000 RPM_SMD_REGULATOR_LEVEL_TURBO + RPM_SMD_REGULATOR_LEVEL_TURBO >; + qcom,gfxfreq-mx-speedbin0 = + < 0 0 >, + < 180000000 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 257000000 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 342000000 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 414000000 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 515000000 RPM_SMD_REGULATOR_LEVEL_NOM >, + < 596000000 RPM_SMD_REGULATOR_LEVEL_NOM >, + < 670000000 RPM_SMD_REGULATOR_LEVEL_TURBO >, + < 710000000 RPM_SMD_REGULATOR_LEVEL_TURBO >; }; -&pcie0 { - /delete-property/vreg-1.8-supply; - /delete-property/vreg-0.9-supply; - /delete-property/vreg-cx-supply; +&gdsc_gpu_gx { + clock-names = "core_root_clk"; + clocks = <&clock_gfx clk_gfx3d_clk_src>; + qcom,force-enable-root-clk; + /* GFX Rail = CX */ + parent-supply = <&pm2falcon_s3_level>; + status = "ok"; }; &qusb_phy0 { - /delete-property/vdd-supply; - /delete-property/vdda18-supply; - /delete-property/vdda33-supply; + vdd-supply = <&pm2falcon_l1>; + vdda18-supply = <&pmfalcon_l10>; + qcom,vdd-voltage-level = <0 925000 925000>; + vdda33-supply = <&pm2falcon_l7>; }; &ssphy { - /delete-property/vdd-supply; - /delete-property/core-supply; + vdd-supply = <&pm2falcon_l1>; + qcom,vdd-voltage-level = <0 925000 925000>; + core-supply = <&pmfalcon_l1>; }; - -&usb3 { - /delete-property/extcon; -}; - -&mdss_dsi { - /delete-property/vdda-1p2-supply; - /delete-property/vdda-0p9-supply; -}; - -&mdss_dsi0 { - /delete-property/wqhd-vddio-supply; - /delete-property/lab-supply; - /delete-property/ibb-supply; -}; - -&mdss_dsi1 { - /delete-property/wqhd-vddio-supply; - /delete-property/lab-supply; - /delete-property/ibb-supply; -}; - -&mdss_hdmi_pll { - /delete-property/vdda-pll-supply; - /delete-property/vdda-phy-supply; -}; - -&mdss_dp_ctrl { - /delete-property/vdda-1p2-supply; - /delete-property/vdda-0p9-supply; - /delete-property/qcom,dp-usbpd-detection; -}; - -&apc0_cpr { - /* disable aging and closed-loop */ - /delete-property/vdd-supply; - /delete-property/qcom,cpr-enable; - /delete-property/qcom,cpr-hw-closed-loop; - /delete-property/qcom,cpr-aging-ref-voltage; -}; - -&apc0_pwrcl_vreg { - /delete-property/qcom,cpr-aging-max-voltage-adjustment; - /delete-property/qcom,cpr-aging-ref-corner; - /delete-property/qcom,cpr-aging-ro-scaling-factor; - /delete-property/qcom,allow-aging-voltage-adjustment; - /delete-property/qcom,allow-aging-open-loop-voltage-adjustment; -}; - -&apc1_cpr { - /* disable aging and closed-loop */ - /delete-property/vdd-supply; - /delete-property/qcom,cpr-enable; - /delete-property/qcom,cpr-hw-closed-loop; - /delete-property/qcom,cpr-aging-ref-voltage; -}; - -&apc1_perfcl_vreg { - /delete-property/qcom,cpr-aging-max-voltage-adjustment; - /delete-property/qcom,cpr-aging-ref-corner; - /delete-property/qcom,cpr-aging-ro-scaling-factor; - /delete-property/qcom,allow-aging-voltage-adjustment; - /delete-property/qcom,allow-aging-open-loop-voltage-adjustment; -}; - -&gfx_cpr { - reg = <0x05061000 0x4000>, - <0x00784000 0x1000>; - reg-names = "cpr_ctrl", "fuse_base"; - - /* disable aging and closed-loop */ - /delete-property/vdd-supply; - /delete-property/qcom,cpr-enable; - /delete-property/qcom,cpr-aging-ref-voltage; - /delete-property/qcom,cpr-aging-allowed-reg-mask; - /delete-property/qcom,cpr-aging-allowed-reg-value; -}; - -&gfx_vreg { - /delete-property/qcom,cpr-aging-max-voltage-adjustment; - /delete-property/qcom,cpr-aging-ref-corner; - /delete-property/qcom,cpr-aging-ro-scaling-factor; - /delete-property/qcom,allow-aging-voltage-adjustment; - /delete-property/qcom,allow-aging-open-loop-voltage-adjustment; -}; - -&clock_audio { - /delete-property/qcom,audio-ref-clk-gpio; -}; - -&soc { - /delete-node/qcom,csid@ca30000; - /delete-node/qcom,csid@ca30400; - /delete-node/qcom,csid@ca30800; - /delete-node/qcom,csid@ca30c00; - - /delete-node/qcom,lpass@17300000; - /delete-node/qcom,mss@4080000; - /delete-node/qcom,spss@1d00000; - /delete-node/qcom,bcl; - /delete-node/qcom,msm-thermal; - /delete-node/qcom,ssc@5c00000; - /delete-node/qcom,icnss@18800000; - /delete-node/qcom,wil6210; - /delete-node/qcom,rpm-smd; - /delete-node/qcom,spmi@800f000; - - - rpm_bus: qcom,rpm-smd { - compatible = "qcom,rpm-glink"; - qcom,glink-edge = "rpm"; - rpm-channel-name = "rpm_requests"; - }; - - spmi_bus: qcom,spmi@800f000 { - compatible = "qcom,spmi-pmic-arb"; - reg = <0x800f000 0x1000>, - <0x8400000 0x1000000>, - <0x9400000 0x1000000>, - <0xa400000 0x220000>, - <0x800a000 0x3000>; - reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; - interrupt-names = "periph_irq"; - interrupts = ; - qcom,ee = <0>; - qcom,channel = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - cell-index = <0>; - }; -}; - -#include "msm-pmfalcon.dtsi" -#include "msm-pm2falcon.dtsi" -#include "msmfalcon-regulator.dtsi" diff --git a/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-qrd.dtsi b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-qrd.dtsi index 775b6b1190d1..83368136a8b3 100644 --- a/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-qrd.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-qrd.dtsi @@ -12,6 +12,7 @@ #include #include "msm8998-v2.1-interposer-msmfalcon.dtsi" +#include "msm8998-camera-sensor-mtp.dtsi" / { bluetooth: bt_wcn3990 { From 15895e937f1580d2ef346f95a336ba571ac856ac Mon Sep 17 00:00:00 2001 From: Mohammed Khajapasha Date: Tue, 28 Jun 2016 11:55:34 +0530 Subject: [PATCH 21/51] msm-core: use get_user() API to read userspace data/settings Currently userspace data is getting accessed directly and leading to crash, So use get_user() API to copy userspace data/settings to kernel space. Change-Id: I3a75ec9503d8207829640bf88e1c3160bf72c9f0 Signed-off-by: Mohammed Khajapasha --- drivers/power/qcom/msm-core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/power/qcom/msm-core.c b/drivers/power/qcom/msm-core.c index 727a768e63eb..3ac4611da9bd 100644 --- a/drivers/power/qcom/msm-core.c +++ b/drivers/power/qcom/msm-core.c @@ -486,9 +486,9 @@ static long msm_core_ioctl(struct file *file, unsigned int cmd, return -EINVAL; get_user(cluster, &argp->cluster); - mpidr = (argp->cluster << (MAX_CORES_PER_CLUSTER * + mpidr = (cluster << (MAX_CORES_PER_CLUSTER * MAX_NUM_OF_CLUSTERS)); - cpumask = argp->cpumask; + get_user(cpumask, &argp->cpumask); switch (cmd) { case EA_LEAKAGE: From 85d3b912311c1572f0a65e52f87d5c400cd381a6 Mon Sep 17 00:00:00 2001 From: "Raju P.L.S.S.S.N" Date: Thu, 4 Aug 2016 19:17:31 +0530 Subject: [PATCH 22/51] ARM: dts: msm: Add PM support for msmfalcon Add initial PM configuration necessary for SPM, LPM, MPM, RPM stats to support msmfalcon. Change-Id: Ia1e83fe40710e80156b049982e9a8421d04902a1 Signed-off-by: Raju P.L.S.S.S.N --- arch/arm/boot/dts/qcom/msmfalcon-pm.dtsi | 821 +++++++++++++++++++++++ arch/arm/boot/dts/qcom/msmfalcon.dtsi | 1 + 2 files changed, 822 insertions(+) create mode 100644 arch/arm/boot/dts/qcom/msmfalcon-pm.dtsi diff --git a/arch/arm/boot/dts/qcom/msmfalcon-pm.dtsi b/arch/arm/boot/dts/qcom/msmfalcon-pm.dtsi new file mode 100644 index 000000000000..39c766613b30 --- /dev/null +++ b/arch/arm/boot/dts/qcom/msmfalcon-pm.dtsi @@ -0,0 +1,821 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include + +&soc { + qcom,spm@178120000 { + compatible = "qcom,spm-v2"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x17812000 0x1000>; + qcom,name = "gold-l2"; /* Gold L2 SAW */ + qcom,saw2-ver-reg = <0xfd0>; + qcom,cpu-vctl-list = <&CPU4 &CPU5 &CPU6 &CPU7>; + qcom,vctl-timeout-us = <500>; + qcom,vctl-port = <0x0>; + qcom,phase-port = <0x1>; + qcom,saw2-avs-ctl = <0x1010031>; + qcom,saw2-avs-limit = <0x4580458>; + qcom,pfm-port = <0x2>; + }; + + qcom,spm@179120000 { + compatible = "qcom,spm-v2"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x17912000 0x1000>; + qcom,name = "silver-l2"; /* Silver L2 SAW */ + qcom,saw2-ver-reg = <0xfd0>; + qcom,cpu-vctl-list = <&CPU0 &CPU1 &CPU2 &CPU3>; + qcom,vctl-timeout-us = <500>; + qcom,vctl-port = <0x0>; + qcom,phase-port = <0x1>; + qcom,saw2-avs-ctl = <0x1010031>; + qcom,saw2-avs-limit = <0x4580458>; + qcom,pfm-port = <0x2>; + }; + + qcom,lpm-levels { + compatible = "qcom,lpm-levels"; + qcom,use-psci; + #address-cells = <1>; + #size-cells = <0>; + qcom,pm-cluster@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + label = "system"; + qcom,spm-device-names = "cci"; + qcom,psci-mode-shift = <8>; + qcom,psci-mode-mask = <0xf>; + + qcom,pm-cluster-level@0{ + reg = <0>; + label = "system-wfi"; + qcom,psci-mode = <0x0>; + qcom,latency-us = <100>; + qcom,ss-power = <725>; + qcom,energy-overhead = <85000>; + qcom,time-overhead = <120>; + }; + + qcom,pm-cluster-level@1{ /* E3 */ + reg = <1>; + label = "system-pc"; + qcom,psci-mode = <0x3>; + qcom,latency-us = <350>; + qcom,ss-power = <530>; + qcom,energy-overhead = <160000>; + qcom,time-overhead = <550>; + qcom,min-child-idx = <3>; + qcom,is-reset; + qcom,notify-rpm; + }; + + qcom,pm-cluster@0{ + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + label = "pwr"; + qcom,spm-device-names = "l2"; + qcom,cpu = <&CPU0 &CPU1 &CPU2 &CPU3>; + qcom,psci-mode-shift = <4>; + qcom,psci-mode-mask = <0xf>; + + qcom,pm-cluster-level@0{ /* D1 */ + reg = <0>; + label = "pwr-l2-wfi"; + qcom,psci-mode = <0x1>; + qcom,latency-us = <40>; + qcom,ss-power = <740>; + qcom,energy-overhead = <65000>; + qcom,time-overhead = <85>; + }; + qcom,pm-cluster-level@1{ /* D2D */ + reg = <1>; + label = "pwr-l2-dynret"; + qcom,psci-mode = <0x2>; + qcom,latency-us = <60>; + qcom,ss-power = <700>; + qcom,energy-overhead = <85000>; + qcom,time-overhead = <85>; + qcom,min-child-idx = <1>; + }; + + qcom,pm-cluster-level@2{ /* D2E */ + reg = <2>; + label = "pwr-l2-ret"; + qcom,psci-mode = <0x3>; + qcom,latency-us = <100>; + qcom,ss-power = <640>; + qcom,energy-overhead = <135000>; + qcom,time-overhead = <85>; + qcom,min-child-idx = <2>; + }; + + qcom,pm-cluster-level@3{ /* D4 */ + reg = <3>; + label = "pwr-l2-pc"; + qcom,psci-mode = <0x4>; + qcom,latency-us = <700>; + qcom,ss-power = <450>; + qcom,energy-overhead = <210000>; + qcom,time-overhead = <11500>; + qcom,min-child-idx = <2>; + qcom,is-reset; + }; + + qcom,pm-cpu { + #address-cells = <1>; + #size-cells = <0>; + qcom,psci-mode-shift = <0>; + qcom,psci-mode-mask = <0xf>; + + qcom,pm-cpu-level@0 { /* C1 */ + reg = <0>; + qcom,spm-cpu-mode = "wfi"; + qcom,psci-cpu-mode = <0x1>; + qcom,latency-us = <20>; + qcom,ss-power = <750>; + qcom,energy-overhead = <32000>; + qcom,time-overhead = <60>; + }; + + qcom,pm-cpu-level@1 { /* C2D */ + reg = <1>; + qcom,psci-cpu-mode = <2>; + qcom,spm-cpu-mode = "ret"; + qcom,latency-us = <40>; + qcom,ss-power = <730>; + qcom,energy-overhead = <85500>; + qcom,time-overhead = <110>; + }; + + qcom,pm-cpu-level@2 { /* C3 */ + reg = <2>; + qcom,spm-cpu-mode = "pc"; + qcom,psci-cpu-mode = <0x3>; + qcom,latency-us = <80>; + qcom,ss-power = <700>; + qcom,energy-overhead = <126480>; + qcom,time-overhead = <160>; + qcom,is-reset; + }; + }; + }; + + qcom,pm-cluster@1{ + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + label = "perf"; + qcom,spm-device-names = "l2"; + qcom,cpu = <&CPU4 &CPU5 &CPU6 &CPU7>; + qcom,psci-mode-shift = <4>; + qcom,psci-mode-mask = <0xf>; + + qcom,pm-cluster-level@0{ /* D1 */ + reg = <0>; + label = "perf-l2-wfi"; + qcom,psci-mode = <0x1>; + qcom,latency-us = <40>; + qcom,ss-power = <740>; + qcom,energy-overhead = <70000>; + qcom,time-overhead = <80>; + }; + + qcom,pm-cluster-level@1{ /* D2D */ + reg = <1>; + label = "perf-l2-dynret"; + qcom,psci-mode = <2>; + qcom,latency-us = <60>; + qcom,ss-power = <700>; + qcom,energy-overhead = <85000>; + qcom,time-overhead = <85>; + qcom,min-child-idx = <1>; + }; + + qcom,pm-cluster-level@2{ /* D2E */ + reg = <2>; + label = "perf-l2-ret"; + qcom,psci-mode = <3>; + qcom,latency-us = <100>; + qcom,ss-power = <640>; + qcom,energy-overhead = <135000>; + qcom,time-overhead = <85>; + qcom,min-child-idx = <2>; + }; + + qcom,pm-cluster-level@3{ /* D4 */ + reg = <3>; + label = "perf-l2-pc"; + qcom,psci-mode = <0x4>; + qcom,latency-us = <800>; + qcom,ss-power = <450>; + qcom,energy-overhead = <240000>; + qcom,time-overhead = <11500>; + qcom,min-child-idx = <2>; + qcom,is-reset; + }; + + qcom,pm-cpu { + #address-cells = <1>; + #size-cells = <0>; + qcom,psci-mode-shift = <0>; + qcom,psci-mode-mask = <0xf>; + + qcom,pm-cpu-level@0 { /* C1 */ + reg = <0>; + qcom,spm-cpu-mode = "wfi"; + qcom,psci-cpu-mode = <0x1>; + qcom,latency-us = <25>; + qcom,ss-power = <750>; + qcom,energy-overhead = <37000>; + qcom,time-overhead = <50>; + }; + + qcom,pm-cpu-level@1 { /* C2D */ + reg = <1>; + qcom,psci-cpu-mode = <2>; + qcom,spm-cpu-mode = "ret"; + qcom,latency-us = <40>; + qcom,ss-power = <730>; + qcom,energy-overhead = <85500>; + qcom,time-overhead = <110>; + }; + + qcom,pm-cpu-level@2 { /* C3 */ + reg = <2>; + qcom,spm-cpu-mode = "pc"; + qcom,psci-cpu-mode = <0x3>; + qcom,latency-us = <80>; + qcom,ss-power = <700>; + qcom,energy-overhead = <136480>; + qcom,time-overhead = <160>; + qcom,is-reset; + }; + }; + }; + }; + }; + + qcom,rpm-stats@200000 { + compatible = "qcom,rpm-stats"; + reg = <0x200000 0x1000>, + <0x290014 0x4>, + <0x29001c 0x4>; + reg-names = "phys_addr_base", + "offset_addr", + "heap_phys_addrbase"; + qcom,sleep-stats-version = <2>; + }; + + qcom,rpm-rail-stats@200000 { + compatible = "qcom,rpm-rail-stats"; + reg = <0x200000 0x100>, + <0x29000c 0x4>; + reg-names = "phys_addr_base", + "offset_addr"; + }; + + qcom,rpm-log@200000 { + compatible = "qcom,rpm-log"; + reg = <0x200000 0x4000>, + <0x290018 0x4>; + qcom,rpm-addr-phys = <0x200000>; + qcom,offset-version = <4>; + qcom,offset-page-buffer-addr = <36>; + qcom,offset-log-len = <40>; + qcom,offset-log-len-mask = <44>; + qcom,offset-page-indices = <56>; + }; + + qcom,rpm-master-stats@778150 { + compatible = "qcom,rpm-master-stats"; + reg = <0x778150 0x5000>; + qcom,masters = "APSS", "MPSS", "ADSP", "CDSP", "TZ"; + qcom,master-stats-version = <2>; + qcom,master-offset = <4096>; + }; + + rpm_msg_ram: memory@0x200000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0x200000 0x1000>, + <0x290000 0x1000>; + }; + + rpm_code_ram: rpm-memory@0x778000 { + compatible = "qcom,rpm-code-ram"; + reg = <0x778000 0x5000>; + }; + + qcom,system-stats { + compatible = "qcom,system-stats"; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + qcom,rpm-code-ram = <&rpm_code_ram>; + qcom,masters = "APSS", "MPSS", "ADSP", "CDSP", "TZ"; + }; + + qcom,mpm@7781b8 { + compatible = "qcom,mpm-v2"; + reg = <0x7781b8 0x1000>, /* MSM_RPM_MPM_BASE 4K */ + <0x17911008 0x4>; /* MSM_APCS_GCC_BASE 4K */ + reg-names = "vmpm", "ipc"; + interrupts = ; + clocks = <&clock_rpmcc CXO_LPM_CLK>; + clock-names = "xo"; + qcom,num-mpm-irqs = <96>; + + qcom,ipc-bit-offset = <1>; + + qcom,gic-parent = <&intc>; + qcom,gic-map = + <0x02 216>, /* tsens1_tsens_upper_lower_int */ + <0x31 212>, /* usb30_power_event_irq */ + <0x34 275>, /* qmp_usb3_lfps_rxterm_irq_cx */ + <0x4f 379>, /* qusb2phy_intr */ + <0x57 358>, /* ee0_apps_hlos_spmi_periph_irq */ + <0xff 16>, /* APC[0-7]_qgicQTmrHypPhysIrptReq */ + <0xff 17>, /* APC[0-7]_qgicQTmrSecPhysIrptReq */ + <0xff 18>, /* APC[0-7]_qgicQTmrNonSecPhysIrptReq */ + <0xff 19>, /* APC[0-7]_qgicQTmrVirtIrptReq */ + <0xff 20>, /* APC[0-7]_dbgCommRxFull */ + <0xff 21>, /* APC[0-7]_dbgCommTxEmpty */ + <0xff 22>, /* APC[0-7]_qgicPerfMonIrptReq */ + <0xff 23>, /* corespm_vote_int[0-7] */ + <0xff 24>, /* APC[0-3]_qgicExtFaultIrptReq */ + <0xff 28>, /* qgicWakeupSync[0-7] */ + <0xff 29>, /* APCC_cti_SPI_intx[0-7] */ + <0xff 30>, /* APCC_cti_SPI_inty[0-7] */ + <0xff 32>, /* l2spm_vote_int[0] */ + <0xff 33>, /* l2spm_vote_int[1] */ + <0xff 34>, /* APCC_qgicL2ErrorIrptReq */ + <0xff 35>, /* WDT_barkInt */ + <0xff 36>, /* WDT_biteExpired */ + <0xff 39>, /* QTMR_qgicFrm0VirtIrq */ + <0xff 40>, /* QTMR_qgicFrm0PhyIrq */ + <0xff 41>, /* QTMR_qgicFrm1PhyIrq */ + <0xff 42>, /* QTMR_qgicFrm2PhyIrq */ + <0xff 43>, /* QTMR_qgicFrm3PhyIrq */ + <0xff 44>, /* QTMR_qgicFrm4PhyIrq */ + <0xff 45>, /* QTMR_qgicFrm5PhyIrq */ + <0xff 46>, /* QTMR_qgicFrm6PhyIrq */ + <0xff 47>, /* rbif_Irq[0] */ + <0xff 48>, /* rbif_Irq[1] */ + <0xff 49>, /* rbif_Irq[2] */ + <0xff 50>, /* rbif_Irq[3] */ + <0xff 51>, /* rbif_Irq[4] */ + <0xff 52>, /* cci_spm_vote_summary_int */ + <0xff 54>, /* nERRORIRQ */ + <0xff 55>, /* nEVNTCNTOVERFLOW_cci */ + <0xff 56>, /* QTMR_qgicFrm0VirtIrq */ + <0xff 57>, /* QTMR_qgicFrm0PhyIrq */ + <0xff 58>, /* QTMR_qgicFrm1PhyIrq */ + <0xff 59>, /* QTMR_qgicFrm2PhyIrq */ + <0xff 60>, /* QTMR_qgicFrm3PhyIrq */ + <0xff 61>, /* QTMR_qgicFrm4PhyIrq */ + <0xff 62>, /* QTMR_qgicFrm5PhyIrq */ + <0xff 63>, /* QTMR_qgicFrm6PhyIrq */ + <0xff 64>, /* wakeup_counter_irq_OR */ + <0xff 65>, /* APC[0-3]_vs_alarm */ + <0xff 66>, /* apc1_vs_alarm */ + <0xff 67>, /* o_pwr_osm_irq */ + <0xff 68>, /* o_perf_osm_irq */ + <0xff 69>, /* o_pwr_dcvsh_interrupt */ + <0xff 70>, /* o_perf_dcvsh_interrupt */ + <0xff 73>, /* L2_EXTERRIRQ_C0 */ + <0xff 74>, /* L2_EXTERRIRQ_C1 */ + <0xff 75>, /* L2_INTERRIRQ_C0 */ + <0xff 76>, /* L2_INTERRIRQ_C1 */ + <0xff 77>, /* L2SPM_svicInt[0] */ + <0xff 78>, /* L2SPM_svicInt[1] */ + <0xff 79>, /* L2SPM_svicIntSwDone[0] */ + <0xff 80>, /* L2SPM_svicIntSwDone[1] */ + <0xff 81>, /* l2_avs_err[0] */ + <0xff 82>, /* l2_avs_err[1] */ + <0xff 83>, /* l2_avs_ack[0] */ + <0xff 84>, /* l2_avs_ack[1] */ + <0xff 98>, /* o_qm_interrupt */ + <0xff 100>, /* camss_vbif_1_irpt */ + <0xff 101>, /* processor_1_user_int */ + <0xff 102>, /* processor_1_kernel_int */ + <0xff 106>, /* dir_conn_irq_lpa_dsp[2] */ + <0xff 107>, /* dir_conn_irq_lpa_dsp[1] */ + <0xff 109>, /* camss_vbif_0_irpt */ + <0xff 110>, /* csiphy_0_irq */ + <0xff 111>, /* csiphy_1_irq */ + <0xff 112>, /* csiphy_2_irq */ + <0xff 115>, /* mdss_irq */ + <0xff 116>, /* mdss_vbif_irpt */ + <0xff 117>, /* dir_conn_irq_lpa_dsp[0] */ + <0xff 119>, /* lpass_irq_out_apcs[11] */ + <0xff 122>, /* o_pimem_tpdm_bc_irq_ofsat */ + <0xff 123>, /* o_pimem_tpdm_tc_irq_ofsat */ + <0xff 124>, /* dir_conn_irq_sensors[1] */ + <0xff 125>, /* dir_conn_irq_sensors[0] */ + <0xff 127>, /* peripheral_irq[2] */ + <0xff 128>, /* peripheral_irq[3] */ + <0xff 129>, /* peripheral_irq[4] */ + <0xff 130>, /* peripheral_irq[5] */ + <0xff 133>, /* peripheral_irq[2] */ + <0xff 134>, /* peripheral_irq[3] */ + <0xff 135>, /* peripheral_irq[4] */ + <0xff 136>, /* peripheral_irq[5] */ + <0xff 139>, /* peripheral_irq[0] */ + <0xff 140>, /* peripheral_irq[1] */ + <0xff 142>, /* sdcc_irq[0] */ + <0xff 143>, /* sdcc_irq[1] */ + <0xff 144>, /* sdcc_pwr_cmd_irq */ + <0xff 145>, /* peripheral_irq[0] */ + <0xff 146>, /* peripheral_irq[1] */ + <0xff 148>, /* osmmu_CIrpt[4] */ + <0xff 149>, /* osmmu_CIrpt[5] */ + <0xff 150>, /* sdio_wakeup_irq */ + <0xff 151>, /* acvremoval_int */ + <0xff 152>, /* trs_int */ + <0xff 155>, /* dir_conn_irq_lpa_dsp[5] */ + <0xff 156>, /* dir_conn_irq_lpa_dsp[4] */ + <0xff 157>, /* sdcc_irq[0] */ + <0xff 158>, /* sdcc_irq[1] */ + <0xff 159>, /* lpass_irq_out_apcs[39] */ + <0xff 160>, /* lpass_irq_out_apcs[38] */ + <0xff 163>, /* usb30_ctrl_irq[0] */ + <0xff 164>, /* usb30_bam_irq[0] */ + <0xff 165>, /* usb30_hs_phy_irq */ + <0xff 166>, /* o_lm_int_2qgic */ + <0xff 169>, /* lpass_irq_out_apcs[33] */ + <0xff 171>, /* usb20s_hs_phy_irq */ + <0xff 172>, /* dcvs_int[6] */ + <0xff 173>, /* dcvs_int[7] */ + <0xff 175>, /* usb20s_ee1_irq */ + <0xff 176>, /* usb20s_power_event_irq */ + <0xff 184>, /* dir_conn_irq_lpa_dsp[3] */ + <0xff 185>, /* camss_vbif_2_irpt */ + <0xff 186>, /* mnoc_obs_mainfault */ + <0xff 188>, /* lpass_irq_out_apcs[00] */ + <0xff 189>, /* lpass_irq_out_apcs[01] */ + <0xff 190>, /* lpass_irq_out_apcs[02] */ + <0xff 191>, /* lpass_irq_out_apcs[03] */ + <0xff 192>, /* lpass_irq_out_apcs[04] */ + <0xff 193>, /* lpass_irq_out_apcs[05] */ + <0xff 194>, /* lpass_irq_out_apcs[06] */ + <0xff 195>, /* lpass_irq_out_apcs[07] */ + <0xff 196>, /* lpass_irq_out_apcs[08] */ + <0xff 197>, /* lpass_irq_out_apcs[09] */ + <0xff 199>, /* qdss_usb_trace_bam_irq[0] */ + <0xff 200>, /* rpm_ipc[4] */ + <0xff 201>, /* rpm_ipc[5] */ + <0xff 202>, /* rpm_ipc[6] */ + <0xff 203>, /* rpm_ipc[7] */ + <0xff 204>, /* rpm_ipc[20] */ + <0xff 205>, /* rpm_ipc[21] */ + <0xff 206>, /* rpm_ipc[22] */ + <0xff 207>, /* rpm_ipc[23] */ + <0xff 208>, /* lpi_dir_conn_irq_apps[0] */ + <0xff 209>, /* lpi_dir_conn_irq_apps[1] */ + <0xff 210>, /* lpi_dir_conn_irq_apps[2] */ + <0xff 213>, /* secure_wdog_bark_irq */ + <0xff 214>, /* tsens1_tsens_max_min_int */ + <0xff 215>, /* o_bimc_intr[0] */ + <0xff 217>, /* o_ocimem_nonsec_irq */ + <0xff 218>, /* cpr_irq[1] */ + <0xff 219>, /* lpass_irq_out_vmm[00] */ + <0xff 220>, /* spmi_protocol_irq */ + <0xff 221>, /* lpass_irq_out_vmm[01] */ + <0xff 222>, /* lpass_irq_out_vmm[02] */ + <0xff 223>, /* spdm_offline_irq */ + <0xff 224>, /* spdm_realtime_irq[1] */ + <0xff 225>, /* snoc_obs_mainFault */ + <0xff 226>, /* cnoc_obs_mainFault */ + <0xff 227>, /* o_tcsr_xpu3_sec_summary_intr */ + <0xff 228>, /* o_tcsr_xpu3_non_sec_summary_intr */ + <0xff 229>, /* o_timeout_slave_hmss_summary_intr */ + <0xff 230>, /* o_tcsr_vmidmt_client_sec_summary_intr */ + <0xff 231>, /* o_tcsr_vmidmt_client_nsec_summary_intr */ + <0xff 232>, /* o_tcsr_vmidmt_cfg_sec_summary_intr */ + <0xff 233>, /* o_tcsr_vmidmt_cfg_non_sec_summary_intr */ + <0xff 234>, /* lpass_irq_out_vmm[03] */ + <0xff 235>, /* cpr_irq[0] */ + <0xff 236>, /* crypto_core_irq[0] */ + <0xff 237>, /* crypto_core_irq[1] */ + <0xff 238>, /* crypto_bam_irq[0] */ + <0xff 239>, /* crypto_bam_irq[1] */ + <0xff 240>, /* summary_irq_hmss */ + <0xff 241>, /* dir_conn_irq_hmss[7] */ + <0xff 242>, /* dir_conn_irq_hmss[6] */ + <0xff 243>, /* dir_conn_irq_hmss[5] */ + <0xff 244>, /* dir_conn_irq_hmss[4] */ + <0xff 245>, /* dir_conn_irq_hmss[3] */ + <0xff 246>, /* dir_conn_irq_hmss[2] */ + <0xff 247>, /* dir_conn_irq_hmss[1] */ + <0xff 248>, /* dir_conn_irq_hmss[0] */ + <0xff 249>, /* summary_irq_hmss_tz */ + <0xff 250>, /* cpr_irq[3] */ + <0xff 251>, /* cpr_irq[2] */ + <0xff 252>, /* cpr_irq[1] */ + <0xff 253>, /* sdcc_pwr_cmd_irq */ + <0xff 254>, /* sdio_wakeup_irq */ + <0xff 255>, /* cpr_irq[0] */ + <0xff 256>, /* lpass_irq_out_apcs[34] */ + <0xff 257>, /* lpass_irq_out_apcs[35] */ + <0xff 258>, /* lpass_irq_out_apcs[21] */ + <0xff 261>, /* o_tcsr_mmu_nsgcfglrpt_summary_intr */ + <0xff 262>, /* o_tcsr_mmu_gcfglrpt_summary_intr */ + <0xff 263>, /* o_tcsr_mmu_nsglrpt_summary_intr */ + <0xff 264>, /* o_tcsr_mmu_glrpt_summary_intr */ + <0xff 265>, /* vbif_irpt */ + <0xff 266>, /* lpass_irq_out_apcs[20] */ + <0xff 267>, /* lpass_irq_out_apcs[19] */ + <0xff 269>, /* rpm_wdog_expired_irq */ + <0xff 270>, /* bam_irq[0] */ + <0xff 271>, /* bam_irq[0] */ + <0xff 276>, /* mmss_bimc_smmu_cirpt[4] */ + <0xff 277>, /* mmss_bimc_smmu_cirpt[5] */ + <0xff 278>, /* usb30_ctrl_irq[1] */ + <0xff 279>, /* mmss_bimc_smmu_cirpt[6] */ + <0xff 280>, /* mmss_bimc_smmu_cirpt[7] */ + <0xff 281>, /* mmss_bimc_smmu_cirpt[8] */ + <0xff 282>, /* mmss_bimc_smmu_cirpt[9] */ + <0xff 283>, /* mmss_bimc_smmu_cirpt[10] */ + <0xff 284>, /* mmss_bimc_smmu_cirpt[11] */ + <0xff 285>, /* mmss_bimc_smmu_cirpt[12] */ + <0xff 286>, /* mmss_bimc_smmu_cirpt[13] */ + <0xff 287>, /* mmss_bimc_smmu_cirpt[14] */ + <0xff 288>, /* mmss_bimc_smmu_cirpt[15] */ + <0xff 289>, /* ufs_ice_sec_level_irq */ + <0xff 291>, /* lpass_irq_out_apcs[18] */ + <0xff 292>, /* mmss_bimc_smmu_cirpt[16] */ + <0xff 293>, /* mmss_bimc_smmu_cirpt[17] */ + <0xff 294>, /* mmss_bimc_smmu_cirpt[18] */ + <0xff 295>, /* mmss_bimc_smmu_cirpt[0] */ + <0xff 296>, /* mmss_bimc_smmu_pmirpt */ + <0xff 297>, /* ufs_intrq */ + <0xff 298>, /* mmss_bimc_smmu_cirpt[1] */ + <0xff 299>, /* mmss_bimc_smmu_cirpt[2] */ + <0xff 300>, /* mmss_bimc_smmu_cirpt[3] */ + <0xff 301>, /* lpass_irq_out_apcs[17] */ + <0xff 302>, /* qdss_etrbytecnt_irq */ + <0xff 303>, /* lpass_irq_out_apcs[16] */ + <0xff 304>, /* mmss_bimc_smmu_cirpt[19] */ + <0xff 305>, /* mmss_bimc_smmu_cirpt[20] */ + <0xff 306>, /* mmss_bimc_smmu_cirpt[21] */ + <0xff 307>, /* mmss_bimc_smmu_cirpt[22] */ + <0xff 308>, /* mmss_bimc_smmu_cirpt[23] */ + <0xff 316>, /* lpass_irq_out_apcs[13] */ + <0xff 317>, /* rbif_irq */ + <0xff 318>, /* gpu_cc_gpu_cx_gds_hw_ctrl_irq_out */ + <0xff 319>, /* venus0_irq */ + <0xff 323>, /* lpass_irq_out_apcs[14] */ + <0xff 324>, /* lpass_irq_out_apcs[15] */ + <0xff 325>, /* camss_irq18 */ + <0xff 326>, /* camss_irq0 */ + <0xff 327>, /* camss_irq1 */ + <0xff 328>, /* camss_irq2 */ + <0xff 329>, /* camss_irq3 */ + <0xff 330>, /* camss_irq4 */ + <0xff 331>, /* camss_irq5 */ + <0xff 332>, /* GC_SYS_irq[0] */ + <0xff 333>, /* GC_SYS_irq[1] */ + <0xff 334>, /* GC_SYS_irq[2] */ + <0xff 335>, /* GC_SYS_irq[3] */ + <0xff 336>, /* camss_irq13 */ + <0xff 337>, /* camss_irq14 */ + <0xff 338>, /* camss_irq15 */ + <0xff 339>, /* camss_irq16 */ + <0xff 340>, /* camss_irq17 */ + <0xff 341>, /* camss_irq6 */ + <0xff 342>, /* lpass_irq_out_apcs[36] */ + <0xff 345>, /* camss_irq7 */ + <0xff 346>, /* camss_irq8 */ + <0xff 347>, /* camss_irq9 */ + <0xff 348>, /* camss_irq10 */ + <0xff 350>, /* camss_irq12 */ + <0xff 351>, /* lpass_irq_out_apcs[12] */ + <0xff 357>, /* o_pimem_nonfatal_irq */ + <0xff 359>, /* ee1_apps_trustzone_spmi_periph_irq */ + <0xff 360>, /* o_pimem_fatal_irq */ + <0xff 361>, /* osmmu_CIrpt[0] */ + <0xff 362>, /* osmmu_CIrpt[1] */ + <0xff 363>, /* osmmu_CIrpt[2] */ + <0xff 364>, /* osmmu_CIrpt[3] */ + <0xff 365>, /* ipa_irq[0] */ + <0xff 366>, /* osmmu_PMIrpt */ + <0xff 380>, /* qusb2phy_intr */ + <0xff 381>, /* osmmu_CIrpt[6] */ + <0xff 382>, /* osmmu_CIrpt[7] */ + <0xff 385>, /* osmmu_CIrpt[12] */ + <0xff 386>, /* osmmu_CIrpt[13] */ + <0xff 387>, /* osmmu_CIrpt[14] */ + <0xff 388>, /* osmmu_CIrpt[15] */ + <0xff 389>, /* osmmu_CIrpt[16] */ + <0xff 390>, /* osmmu_CIrpt[17] */ + <0xff 391>, /* osmmu_CIrpt[18] */ + <0xff 392>, /* osmmu_CIrpt[19] */ + <0xff 393>, /* o_dcc_crc_fail_int */ + <0xff 404>, /* aggre2noc_obs_mainFault */ + <0xff 405>, /* osmmu_CIrpt[0] */ + <0xff 406>, /* osmmu_CIrpt[1] */ + <0xff 407>, /* osmmu_CIrpt[2] */ + <0xff 408>, /* osmmu_CIrpt[3] */ + <0xff 409>, /* osmmu_CIrpt[4] */ + <0xff 410>, /* osmmu_CIrpt[5] */ + <0xff 411>, /* o_dcc_task_done_int */ + <0xff 412>, /* vsense_apps_alarm_irq */ + <0xff 413>, /* osmmu_PMIrpt */ + <0xff 414>, /* channel0_apps_hlos_trans_done_irq */ + <0xff 415>, /* channel1_apps_trustzone_trans_done_irq */ + <0xff 416>, /* rpm_ipc[28] */ + <0xff 417>, /* rpm_ipc[29] */ + <0xff 418>, /* rpm_ipc[30] */ + <0xff 419>, /* rpm_ipc[31] */ + <0xff 423>, /* lpass_irq_out_apcs[40] */ + <0xff 424>, /* ipa_irq[2] */ + <0xff 425>, /* lpass_irq_out_apcs[22] */ + <0xff 426>, /* lpass_irq_out_apcs[23] */ + <0xff 427>, /* lpass_irq_out_apcs[24] */ + <0xff 428>, /* lpass_irq_out_apcs[25] */ + <0xff 429>, /* lpass_irq_out_apcs[26] */ + <0xff 430>, /* lpass_irq_out_apcs[27] */ + <0xff 431>, /* lpass_irq_out_apcs[28] */ + <0xff 432>, /* lpass_irq_out_apcs[29] */ + <0xff 433>, /* lpass_irq_out_apcs[30] */ + <0xff 434>, /* lpass_irq_out_apcs[31] */ + <0xff 435>, /* lpass_irq_out_apcs[32] */ + <0xff 436>, /* lpass_irq_out_apcs[37] */ + <0xff 445>, /* wcss_apss_ce_intr[0] */ + <0xff 446>, /* wcss_apss_ce_intr[1] */ + <0xff 447>, /* wcss_apss_ce_intr[2] */ + <0xff 448>, /* wcss_apss_ce_intr[3] */ + <0xff 449>, /* wcss_apss_ce_intr[4] */ + <0xff 450>, /* wcss_apss_ce_intr[5] */ + <0xff 452>, /* wcss_apss_ce_intr[6] */ + <0xff 453>, /* wcss_apss_ce_intr[7] */ + <0xff 454>, /* wcss_apss_ce_intr[8] */ + <0xff 455>, /* wcss_apss_ce_intr[9] */ + <0xff 456>, /* wcss_apss_ce_intr[10] */ + <0xff 457>, /* wcss_apss_ce_intr[11] */ + <0xff 458>, /* wcss_apss_status_intr */ + <0xff 462>, /* tsens1_tsens_critical_int */ + <0xff 464>, /* ipa_bam_irq[0] */ + <0xff 465>, /* ipa_bam_irq[2] */ + <0xff 466>, /* ssc_uart_int */ + <0xff 468>, /* cri_cm_irq_tz */ + <0xff 469>, /* cri_cm_irq_hyp */ + <0xff 471>, /* mmss_bimc_smmu_gds_hw_ctrl_irq_out */ + <0xff 472>, /* gcc_gds_hw_ctrl_irq_out */ + <0xff 474>, /* osmmu_CIrpt[20] */ + <0xff 475>, /* osmmu_CIrpt[21] */ + <0xff 476>, /* osmmu_CIrpt[22] */ + <0xff 477>, /* tsens0_tsens_critical_int */ + <0xff 478>, /* tsens0_tsens_max_min_int */ + <0xff 479>, /* osmmu_CIrpt[23] */ + <0xff 480>, /* q6_wdog_expired_irq */ + <0xff 481>, /* mss_ipc_out_irq[4] */ + <0xff 482>, /* mss_ipc_out_irq[5] */ + <0xff 483>, /* mss_ipc_out_irq[6] */ + <0xff 484>, /* mss_ipc_out_irq[7] */ + <0xff 485>, /* mss_ipc_out_irq[28] */ + <0xff 486>, /* mss_ipc_out_irq[29] */ + <0xff 487>, /* mss_ipc_out_irq[30] */ + <0xff 488>, /* mss_ipc_out_irq[31] */ + <0xff 490>, /* tsens0_tsens_upper_lower_int */ + <0xff 491>, /* qspi_irq0 */ + <0xff 492>, /* sdcc_ice_sec_level_irq */ + <0xff 494>, /* osmmu_CIrpt[6] */ + <0xff 495>, /* osmmu_CIrpt[7] */ + <0xff 496>, /* osmmu_CIrpt[8] */ + <0xff 497>, /* osmmu_CIrpt[9] */ + <0xff 498>, /* osmmu_CIrpt[10] */ + <0xff 499>, /* osmmu_CIrpt[11] */ + <0xff 500>, /* osmmu_CIrpt[24] */ + <0xff 501>, /* osmmu_CIrpt[25] */ + <0xff 503>, /* o_bimc_intr[1] */ + <0xff 504>, /* osmmu_CIrpt[26] */ + <0xff 505>, /* osmmu_CIrpt[27] */ + <0xff 506>, /* osmmu_CIrpt[28] */ + <0xff 512>, /* turing_irq_out_vmm[0] */ + <0xff 513>, /* turing_irq_out_vmm[1] */ + <0xff 514>, /* turing_irq_out_vmm[2] */ + <0xff 515>, /* turing_irq_out_vmm[3] */ + <0xff 516>, /* lpass_irq_out_apcs[41] */ + <0xff 517>, /* lpass_irq_out_apcs[42] */ + <0xff 519>, /* lpass_irq_out_apcs[44] */ + <0xff 520>, /* lpass_irq_out_apcs[45] */ + <0xff 544>, /* turing_irq_out_apcs[00] */ + <0xff 545>, /* turing_irq_out_apcs[01] */ + <0xff 546>, /* turing_irq_out_apcs[02] */ + <0xff 547>, /* turing_irq_out_apcs[03] */ + <0xff 548>, /* turing_irq_out_apcs[04] */ + <0xff 549>, /* turing_irq_out_apcs[05] */ + <0xff 550>, /* turing_irq_out_apcs[06] */ + <0xff 551>, /* turing_irq_out_apcs[07] */ + <0xff 552>, /* turing_irq_out_apcs[08] */ + <0xff 553>, /* turing_irq_out_apcs[09] */ + <0xff 554>, /* turing_irq_out_apcs[10] */ + <0xff 556>, /* turing_irq_out_apcs[12] */ + <0xff 557>, /* turing_irq_out_apcs[13] */ + <0xff 558>, /* turing_irq_out_apcs[14] */ + <0xff 559>, /* turing_irq_out_apcs[15] */ + <0xff 560>, /* turing_irq_out_apcs[16] */ + <0xff 561>, /* turing_irq_out_apcs[17] */ + <0xff 562>, /* turing_irq_out_apcs[18] */ + <0xff 563>, /* turing_irq_out_apcs[19] */ + <0xff 564>, /* turing_irq_out_apcs[20] */ + <0xff 565>, /* turing_irq_out_apcs[21] */ + <0xff 566>, /* turing_irq_out_apcs[22] */ + <0xff 567>, /* turing_irq_out_apcs[23] */ + <0xff 568>, /* turing_irq_out_apcs[24] */ + <0xff 569>, /* turing_irq_out_apcs[25] */ + <0xff 570>, /* turing_irq_out_apcs[26] */ + <0xff 571>, /* turing_irq_out_apcs[27] */ + <0xff 572>, /* turing_irq_out_apcs[28] */ + <0xff 573>, /* turing_irq_out_apcs[29] */ + <0xff 574>, /* turing_irq_out_apcs[30] */ + <0xff 575>, /* turing_irq_out_apcs[31] */ + <0xff 576>, /* turing_irq_out_apcs[32] */ + <0xff 577>, /* turing_irq_out_apcs[33] */ + <0xff 578>, /* turing_irq_out_apcs[34] */ + <0xff 579>, /* turing_irq_out_apcs[35] */ + <0xff 580>, /* turing_irq_out_apcs[36] */ + <0xff 581>, /* turing_irq_out_apcs[37] */ + <0xff 582>, /* turing_irq_out_apcs[38] */ + <0xff 583>, /* turing_irq_out_apcs[39] */ + <0xff 584>; /* turing_irq_out_apcs[40] */ + + qcom,gpio-parent = <&tlmm>; + qcom,gpio-map = + <3 1>, + <4 5>, + <5 9>, + <6 10>, + <7 66>, + <8 22>, + <9 25>, + <10 28>, + <11 58>, + <13 41>, + <14 43>, + <15 40>, + <16 42>, + <17 46>, + <18 50>, + <19 44>, + <21 56>, + <22 45>, + <23 68>, + <24 69>, + <25 70>, + <26 71>, + <27 72>, + <28 73>, + <29 64>, + <30 2>, + <31 13>, + <32 111>, + <33 74>, + <34 75>, + <35 76>, + <36 82>, + <37 17>, + <38 77>, + <39 47>, + <40 54>, + <41 48>, + <42 101>, + <43 49>, + <44 51>, + <45 86>, + <46 90>, + <47 91>, + <48 52>, + <50 55>, + <51 6>, + <53 65>, + <55 67>, + <56 83>, + <57 84>, + <58 85>, + <59 87>, + <63 21>, + <64 78>, + <65 113>, + <66 60>, + <67 98>, + <68 30>, + <70 31>, + <71 29>, + <76 107>, + <83 109>, + <84 103>, + <85 105>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon.dtsi b/arch/arm/boot/dts/qcom/msmfalcon.dtsi index a9b903e2f902..f19a8fe13418 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon.dtsi +++ b/arch/arm/boot/dts/qcom/msmfalcon.dtsi @@ -1555,6 +1555,7 @@ #include "msmfalcon-regulator.dtsi" #include "msm-gdsc-falcon.dtsi" #include "msmfalcon-gpu.dtsi" +#include "msmfalcon-pm.dtsi" &gdsc_usb30 { status = "ok"; From 57e1de214a7d21d403b49c7f98303a8c2e28a88c Mon Sep 17 00:00:00 2001 From: Venkatesh Yadav Abbarapu Date: Thu, 1 Sep 2016 10:49:48 +0530 Subject: [PATCH 23/51] ARM: dts: msm: Enable core hang detect feature on msmfalcon Add core hang detect node for msmfalcon which enables the core hang detect feature. Enable the same for msmtriton also. Change-Id: I108451bae429c8e4c858f7f549c4202f3d59a6d2 Signed-off-by: Venkatesh Yadav Abbarapu --- arch/arm/boot/dts/qcom/msmfalcon.dtsi | 18 ++++++++++++++++++ arch/arm/boot/dts/qcom/msmtriton.dtsi | 18 ++++++++++++++++++ 2 files changed, 36 insertions(+) diff --git a/arch/arm/boot/dts/qcom/msmfalcon.dtsi b/arch/arm/boot/dts/qcom/msmfalcon.dtsi index a9b903e2f902..52824d85f4dc 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon.dtsi +++ b/arch/arm/boot/dts/qcom/msmfalcon.dtsi @@ -1544,6 +1544,24 @@ clocks = <&clock_gcc GCC_PRNG_AHB_CLK>; clock-names = "iface_clk"; }; + + qcom,chd_silver { + compatible = "qcom,core-hang-detect"; + label = "silver"; + qcom,threshold-arr = <0x179880b0 0x179980b0 + 0x179a80b0 0x179b80b0>; + qcom,config-arr = <0x179880b8 0x179980b8 + 0x179a80b8 0x179b80b8>; + }; + + qcom,chd_gold { + compatible = "qcom,core-hang-detect"; + label = "gold"; + qcom,threshold-arr = <0x178880b0 0x178980b0 + 0x178a80b0 0x178b80b0>; + qcom,config-arr = <0x178880b8 0x178980b8 + 0x178a80b8 0x178b80b8>; + }; }; #include "msmfalcon-ion.dtsi" diff --git a/arch/arm/boot/dts/qcom/msmtriton.dtsi b/arch/arm/boot/dts/qcom/msmtriton.dtsi index d96531a5b35a..f95c2beb290f 100644 --- a/arch/arm/boot/dts/qcom/msmtriton.dtsi +++ b/arch/arm/boot/dts/qcom/msmtriton.dtsi @@ -959,6 +959,24 @@ qcom,irq-is-percpu; interrupts = <1 6 4>; }; + + qcom,chd_silver { + compatible = "qcom,core-hang-detect"; + label = "silver"; + qcom,threshold-arr = <0x179880b0 0x179980b0 + 0x179a80b0 0x179b80b0>; + qcom,config-arr = <0x179880b8 0x179980b8 + 0x179a80b8 0x179b80b8>; + }; + + qcom,chd_gold { + compatible = "qcom,core-hang-detect"; + label = "gold"; + qcom,threshold-arr = <0x178880b0 0x178980b0 + 0x178a80b0 0x178b80b0>; + qcom,config-arr = <0x178880b8 0x178980b8 + 0x178a80b8 0x178b80b8>; + }; }; #include "msmtriton-ion.dtsi" From 34cbae8bc57a8490e74bfba91050fa10d6fc4dcc Mon Sep 17 00:00:00 2001 From: Udaya Mallavarapu Date: Wed, 7 Dec 2016 13:16:21 +0530 Subject: [PATCH 24/51] media: dvb-core: Add feed state check before stop dvbdemux feed Add feed state check whether any filter is configured on dvbdemux feed before feed stop is called. If any filter is started the feed status should be set to DMX_STATE_GO. CRs-Fixed: 1090466 Change-Id: If9e87065bb9fb82befb398f2a3a0d0da2f76efa5 Signed-off-by: Udaya Mallavarapu --- drivers/media/dvb-core/dvb_demux.c | 5 +++++ .../platform/msm/dvb/demux/mpq_dmx_plugin_common.c | 12 ++++++++++-- 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/media/dvb-core/dvb_demux.c b/drivers/media/dvb-core/dvb_demux.c index 7809770bd1ae..60f7cfbd9f9b 100644 --- a/drivers/media/dvb-core/dvb_demux.c +++ b/drivers/media/dvb-core/dvb_demux.c @@ -2840,6 +2840,11 @@ static int dmx_section_feed_stop_filtering(struct dmx_section_feed *feed) mutex_lock(&dvbdmx->mutex); + if (dvbdmxfeed->state < DMX_STATE_GO) { + mutex_unlock(&dvbdmx->mutex); + return -EINVAL; + } + if (!dvbdmx->stop_feed) { mutex_unlock(&dvbdmx->mutex); return -ENODEV; diff --git a/drivers/media/platform/msm/dvb/demux/mpq_dmx_plugin_common.c b/drivers/media/platform/msm/dvb/demux/mpq_dmx_plugin_common.c index fb8f0c4bae37..a0195ac400f8 100644 --- a/drivers/media/platform/msm/dvb/demux/mpq_dmx_plugin_common.c +++ b/drivers/media/platform/msm/dvb/demux/mpq_dmx_plugin_common.c @@ -1801,7 +1801,11 @@ int mpq_dmx_terminate_feed(struct dvb_demux_feed *feed) } mpq_sdmx_close_session(mpq_demux); - mpq_demux->num_secure_feeds--; + if (mpq_demux->num_secure_feeds > 0) + mpq_demux->num_secure_feeds--; + else + MPQ_DVB_DBG_PRINT("%s: Invalid secure feed count= %u\n", + __func__, mpq_demux->num_secure_feeds); } if (dvb_dmx_is_video_feed(feed)) { @@ -1818,7 +1822,11 @@ int mpq_dmx_terminate_feed(struct dvb_demux_feed *feed) } mpq_sdmx_terminate_metadata_buffer(mpq_feed); - mpq_demux->num_active_feeds--; + if (mpq_demux->num_active_feeds > 0) + mpq_demux->num_active_feeds--; + else + MPQ_DVB_DBG_PRINT("%s: Invalid num_active_feeds count = %u\n", + __func__, mpq_demux->num_active_feeds); mutex_unlock(&mpq_demux->mutex); From 41417b20311288cdd4b947c9db65129ede6f34ce Mon Sep 17 00:00:00 2001 From: Weiyin Jiang Date: Wed, 23 Nov 2016 16:57:38 +0800 Subject: [PATCH 25/51] ASoC: msm: enable DAP set license logic on 8998 Since we move to GEF implementation for Dolby post processing, disabling DAP/DAX2 driver logic on msm8998 target except for license validation. CRs-Fixed: 1094027 Change-Id: I33c5625026611856f6cdd8c6e0b5d7ef229ba8c7 Signed-off-by: Weiyin Jiang --- sound/soc/msm/Kconfig | 11 ++++++++++- sound/soc/msm/qdsp6v2/Makefile | 1 + sound/soc/msm/qdsp6v2/msm-ds2-dap-config.c | 4 ++-- sound/soc/msm/qdsp6v2/msm-ds2-dap-config.h | 8 ++++---- sound/soc/msm/qdsp6v2/msm-pcm-routing-v2.c | 10 ++++++++++ sound/soc/msm/qdsp6v2/q6adm.c | 10 ++++++++++ 6 files changed, 37 insertions(+), 7 deletions(-) diff --git a/sound/soc/msm/Kconfig b/sound/soc/msm/Kconfig index a5cd94f91cfc..a5a81df49d69 100644 --- a/sound/soc/msm/Kconfig +++ b/sound/soc/msm/Kconfig @@ -50,6 +50,15 @@ config DOLBY_DS2 device, end point dependent post processing parameters and the various posrt processing parameters +config DOLBY_LICENSE + bool "Enable Dolby LICENSE" + depends on SND_SOC_MSM_QDSP6V2_INTF + help + To add support for dolby DAP post processing, + and retain DAP set license functionality only. + This is required by Dolby GEF implementation which needs + nothing but dolby license validation functionality in driver. + config DTS_EAGLE bool "Enable DTS Eagle Support" depends on SND_SOC_MSM_QDSP6V2_INTF @@ -211,7 +220,7 @@ config SND_SOC_MSM8998 select QTI_PP select SND_SOC_CPE select MSM_ULTRASOUND - select DOLBY_DS2 + select DOLBY_LICENSE select SND_HWDEP select DTS_EAGLE help diff --git a/sound/soc/msm/qdsp6v2/Makefile b/sound/soc/msm/qdsp6v2/Makefile index 461c09db2937..469ab1a19c5b 100644 --- a/sound/soc/msm/qdsp6v2/Makefile +++ b/sound/soc/msm/qdsp6v2/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_SND_HWDEP) += msm-pcm-routing-devdep.o obj-$(CONFIG_DTS_EAGLE) += msm-dts-eagle.o obj-$(CONFIG_DOLBY_DAP) += msm-dolby-dap-config.o obj-$(CONFIG_DOLBY_DS2) += msm-ds2-dap-config.o +obj-$(CONFIG_DOLBY_LICENSE) += msm-ds2-dap-config.o obj-$(CONFIG_DTS_SRS_TM) += msm-dts-srs-tm-config.o obj-$(CONFIG_QTI_PP) += msm-qti-pp-config.o obj-y += audio_calibration.o audio_cal_utils.o q6adm.o q6afe.o q6asm.o \ diff --git a/sound/soc/msm/qdsp6v2/msm-ds2-dap-config.c b/sound/soc/msm/qdsp6v2/msm-ds2-dap-config.c index ad2f2e9865c3..2441cabc07a7 100644 --- a/sound/soc/msm/qdsp6v2/msm-ds2-dap-config.c +++ b/sound/soc/msm/qdsp6v2/msm-ds2-dap-config.c @@ -20,7 +20,7 @@ #include -#ifdef CONFIG_DOLBY_DS2 +#if defined(CONFIG_DOLBY_DS2) || defined(CONFIG_DOLBY_LICENSE) /* ramp up/down for 30ms */ #define DOLBY_SOFT_VOLUME_PERIOD 40 @@ -2284,4 +2284,4 @@ int msm_ds2_dap_ioctl_shared(struct snd_hwdep *hw, struct file *file, { return 0; } -#endif /*CONFIG_DOLBY_DS2*/ +#endif /* CONFIG_DOLBY_DS2 || CONFIG_DOLBY_LICENSE */ diff --git a/sound/soc/msm/qdsp6v2/msm-ds2-dap-config.h b/sound/soc/msm/qdsp6v2/msm-ds2-dap-config.h index 82794ee768a8..0eb6017fd383 100644 --- a/sound/soc/msm/qdsp6v2/msm-ds2-dap-config.h +++ b/sound/soc/msm/qdsp6v2/msm-ds2-dap-config.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. +/* Copyright (c) 2013-2014, 2016, The Linux Foundation. All rights reserved. * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and * only version 2 as published by the Free Software Foundation. @@ -45,7 +45,7 @@ struct dolby_param_license32 { _IOR('U', 0x15, struct dolby_param_data32) #endif -#ifdef CONFIG_DOLBY_DS2 +#if defined(CONFIG_DOLBY_DS2) || defined(CONFIG_DOLBY_LICENSE) /* DOLBY DOLBY GUIDS */ #define DS2_MODULE_ID 0x00010775 @@ -86,11 +86,11 @@ int msm_ds2_dap_set_custom_stereo_onoff(int port_id, int copp_idx, /* Dolby DOLBY end */ #else -static inline void msm_ds2_dap_update_port_parameters(struct snd_hwdep *hw, +static inline int msm_ds2_dap_update_port_parameters(struct snd_hwdep *hw, struct file *file, bool open) { - return; + return 0; } static inline int msm_ds2_dap_ioctl(struct snd_hwdep *hw, struct file *file, diff --git a/sound/soc/msm/qdsp6v2/msm-pcm-routing-v2.c b/sound/soc/msm/qdsp6v2/msm-pcm-routing-v2.c index 9164475386ff..513d9ed822f9 100644 --- a/sound/soc/msm/qdsp6v2/msm-pcm-routing-v2.c +++ b/sound/soc/msm/qdsp6v2/msm-pcm-routing-v2.c @@ -46,6 +46,16 @@ #include "q6voice.h" #include "sound/q6lsm.h" +#ifndef CONFIG_DOLBY_DAP +#undef DOLBY_ADM_COPP_TOPOLOGY_ID +#define DOLBY_ADM_COPP_TOPOLOGY_ID 0xFFFFFFFE +#endif + +#ifndef CONFIG_DOLBY_DS2 +#undef DS2_ADM_COPP_TOPOLOGY_ID +#define DS2_ADM_COPP_TOPOLOGY_ID 0xFFFFFFFF +#endif + static int get_cal_path(int path_type); static struct mutex routing_lock; diff --git a/sound/soc/msm/qdsp6v2/q6adm.c b/sound/soc/msm/qdsp6v2/q6adm.c index 8f99a73fd29f..30876b52ec9e 100644 --- a/sound/soc/msm/qdsp6v2/q6adm.c +++ b/sound/soc/msm/qdsp6v2/q6adm.c @@ -39,6 +39,16 @@ #define ULL_SUPPORTED_BITS_PER_SAMPLE 16 #define ULL_SUPPORTED_SAMPLE_RATE 48000 +#ifndef CONFIG_DOLBY_DAP +#undef DOLBY_ADM_COPP_TOPOLOGY_ID +#define DOLBY_ADM_COPP_TOPOLOGY_ID 0xFFFFFFFE +#endif + +#ifndef CONFIG_DOLBY_DS2 +#undef DS2_ADM_COPP_TOPOLOGY_ID +#define DS2_ADM_COPP_TOPOLOGY_ID 0xFFFFFFFF +#endif + /* ENUM for adm_status */ enum adm_cal_status { ADM_STATUS_CALIBRATION_REQUIRED = 0, From 6764573a87956416d892abab0556f18bcc173c66 Mon Sep 17 00:00:00 2001 From: Anirudh Ghayal Date: Wed, 7 Dec 2016 13:44:01 +0530 Subject: [PATCH 26/51] ARM: dts: msm: Add VOL_UP node for MSMFALCON and interposer PM2FALCON GPIO 7 is connected to VOL_UP key. Add the PMIC and GPIO key configuration for GPIO 7. Change-Id: Ie1dcc85f579e0b9817a104be86bbb9e91771b15c Signed-off-by: Anirudh Ghayal --- .../msm8998-v2.1-interposer-msmfalcon-mtp.dts | 29 +++++++++++++++++++ arch/arm/boot/dts/qcom/msmfalcon.dtsi | 29 +++++++++++++++++++ 2 files changed, 58 insertions(+) diff --git a/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-mtp.dts b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-mtp.dts index e537928b21e0..b0e687f967be 100644 --- a/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-mtp.dts +++ b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-mtp.dts @@ -132,3 +132,32 @@ qcom,platform-te-gpio = <&tlmm 10 0>; qcom,panel-mode-gpio = <&tlmm 91 0>; }; + +&pm2falcon_gpios { + /* GPIO 7 for VOL_UP */ + gpio@c600 { + status = "okay"; + qcom,mode = <0>; + qcom,pull = <0>; + qcom,vin-sel = <0>; + qcom,src-sel = <0>; + qcom,out-strength = <1>; + }; +}; + +&soc { + gpio_keys { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + status = "okay"; + + vol_up { + label = "volume_up"; + gpios = <&pm2falcon_gpios 7 0x1>; + linux,input-type = <1>; + linux,code = <115>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon.dtsi b/arch/arm/boot/dts/qcom/msmfalcon.dtsi index a9b903e2f902..0c686ad523d3 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon.dtsi +++ b/arch/arm/boot/dts/qcom/msmfalcon.dtsi @@ -1635,3 +1635,32 @@ #include "msmfalcon-common.dtsi" #include "msmfalcon-blsp.dtsi" #include "msmfalcon-vidc.dtsi" + +&pm2falcon_gpios { + /* GPIO 7 for VOL_UP */ + gpio@c600 { + status = "okay"; + qcom,mode = <0>; + qcom,pull = <0>; + qcom,vin-sel = <0>; + qcom,src-sel = <0>; + qcom,out-strength = <1>; + }; +}; + +&soc { + gpio_keys { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + status = "okay"; + + vol_up { + label = "volume_up"; + gpios = <&pm2falcon_gpios 7 0x1>; + linux,input-type = <1>; + linux,code = <115>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + }; +}; From ae8dff9cb70f4a32fd0da14dab63916b673d2c3b Mon Sep 17 00:00:00 2001 From: Asutosh Das Date: Mon, 5 Dec 2016 11:41:40 +0530 Subject: [PATCH 27/51] phy: qcom-ufs: Modify the vdd-phy min-max range There are 2 issues with setting the vdd-phy voltage: 1. The min & max range that's defined is 1v, whereas 0.925 (+/- 5%) is the required voltage. A range of 0.8v to 0.925v would suffice. 2. This defined range is over-ridden with the current rail-voltage. This assumes that some consumer has set the regulator to the correct voltage. This change corrects the defined min/max range to 0.8v-0.925v for vdd-phy. It also removes the code that's causing [2]. CRs-fixed: 1095116 Change-Id: I943bc4f38385036b21c1f9a2e479d6e94ac12813 Signed-off-by: Asutosh Das --- drivers/phy/phy-qcom-ufs.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/drivers/phy/phy-qcom-ufs.c b/drivers/phy/phy-qcom-ufs.c index e0cab3a683d6..6e06fef81849 100644 --- a/drivers/phy/phy-qcom-ufs.c +++ b/drivers/phy/phy-qcom-ufs.c @@ -15,8 +15,8 @@ #include "phy-qcom-ufs-i.h" #define MAX_PROP_NAME 32 -#define VDDA_PHY_MIN_UV 1000000 -#define VDDA_PHY_MAX_UV 1000000 +#define VDDA_PHY_MIN_UV 800000 +#define VDDA_PHY_MAX_UV 925000 #define VDDA_PLL_MIN_UV 1200000 #define VDDA_PLL_MAX_UV 1800000 #define VDDP_REF_CLK_MIN_UV 1200000 @@ -239,7 +239,6 @@ ufs_qcom_phy_init_vregulators(struct phy *generic_phy, struct ufs_qcom_phy *phy_common) { int err; - int vdda_phy_uV; err = ufs_qcom_phy_init_vreg(generic_phy, &phy_common->vdda_pll, "vdda-pll"); @@ -251,10 +250,6 @@ ufs_qcom_phy_init_vregulators(struct phy *generic_phy, if (err) goto out; - vdda_phy_uV = regulator_get_voltage(phy_common->vdda_phy.reg); - phy_common->vdda_phy.max_uV = vdda_phy_uV; - phy_common->vdda_phy.min_uV = vdda_phy_uV; - /* vddp-ref-clk-* properties are optional */ __ufs_qcom_phy_init_vreg(generic_phy, &phy_common->vddp_ref_clk, "vddp-ref-clk", true); From 7c480568b31c5f1e176fdac975b8cc827526c2aa Mon Sep 17 00:00:00 2001 From: Vijayavardhan Vennapusa Date: Wed, 30 Nov 2016 15:28:40 +0530 Subject: [PATCH 28/51] ARM: dts: msm: Add missing properties for USB node for msmfalcon Add missing required properties for USB node for msmfalcon for USB functionality to be working. Change-Id: I602cac95616da34ffe6462c8cf3af85ce973085b Signed-off-by: Vijayavardhan Vennapusa --- arch/arm/boot/dts/qcom/msmfalcon-common.dtsi | 25 +++++++++++++++----- arch/arm/boot/dts/qcom/msmfalcon-rumi.dts | 1 + arch/arm/boot/dts/qcom/msmfalcon-sim.dts | 1 + arch/arm/boot/dts/qcom/msmtriton-rumi.dts | 2 ++ 4 files changed, 23 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/qcom/msmfalcon-common.dtsi b/arch/arm/boot/dts/qcom/msmfalcon-common.dtsi index b2bad31d12d4..3363d16fae1e 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-common.dtsi +++ b/arch/arm/boot/dts/qcom/msmfalcon-common.dtsi @@ -35,6 +35,7 @@ <61 512 240000 800000>; qcom,dwc-usb3-msm-tx-fifo-size = <21288>; + extcon = <&pmfalcon_pdphy>; clocks = <&clock_gcc GCC_USB30_MASTER_CLK>, <&clock_gcc GCC_CFG_NOC_USB3_AXI_CLK>, @@ -49,6 +50,8 @@ "noc_aggr_clk", "utmi_clk", "sleep_clk", "cfg_ahb_clk", "xo"; + qcom,core-clk-rate = <133330000>; + resets = <&clock_gcc GCC_USB_30_BCR>; reset-names = "core_reset"; @@ -59,7 +62,6 @@ interrupts = <0 131 0>; usb-phy = <&qusb_phy0>, <&ssphy>; tx-fifo-resize; - snps,usb3-u1u2-disable; snps,nominal-elastic-buffer; snps,is-utmi-l1-suspend; snps,hird-threshold = /bits/ 8 <0x0>; @@ -72,7 +74,7 @@ interrupts = <0 132 0>; qcom,bam-type = <0>; - qcom,usb-bam-fifo-baseaddr = <0x066bb000>; + qcom,usb-bam-fifo-baseaddr = <0x146bb000>; qcom,usb-bam-num-pipes = <8>; qcom,ignore-core-reset-ack; qcom,disable-clk-gating; @@ -131,16 +133,15 @@ qusb_phy0: qusb@c012000 { compatible = "qcom,qusb2phy"; reg = <0x0c012000 0x180>, + <0x01fcb24c 0x4>, <0x00188018 0x4>; reg-names = "qusb_phy_base", + "tcsr_clamp_dig_n_1p8", "ref_clk_addr"; vdd-supply = <&pm2falcon_l1>; vdda18-supply = <&pmfalcon_l10>; vdda33-supply = <&pm2falcon_l7>; qcom,vdd-voltage-level = <0 925000 925000>; - qcom,tune2-efuse-bit-pos = <21>; - qcom,tune2-efuse-num-bits = <4>; - qcom,enable-dpdm-pulsing; qcom,qusb-phy-init-seq = <0xf8 0x80 0xb3 0x84 0x83 0x88 @@ -152,6 +153,8 @@ 0x9f 0x1c 0x00 0x18>; phy_type= "utmi"; + qcom,phy-clk-scheme = "cml"; + qcom,major-rev = <1>; clocks = <&clock_rpmcc RPM_LN_BB_CLK1>, <&clock_gcc GCC_RX0_USB2_CLKREF_CLK>, @@ -165,7 +168,7 @@ ssphy: ssphy@c010000 { compatible = "qcom,usb-ssphy-qmp-v2"; - reg = <0xc010000 0x7a8>, + reg = <0xc010000 0xe18>, <0x01fcb244 0x4>, <0x01fcb248 0x4>; reg-names = "qmp_phy_base", @@ -174,8 +177,18 @@ vdd-supply = <&pm2falcon_l1>; core-supply = <&pmfalcon_l10>; qcom,vdd-voltage-level = <0 925000 925000>; + vdd-core-voltage-level = <0 1800000 1800000>; qcom,vbus-valid-override; + qcom,qmp-phy-reg-offset = + <0xd74 /* USB3_PHY_PCS_STATUS */ + 0xcd8 /* USB3_PHY_AUTONOMOUS_MODE_CTRL */ + 0xcdc /* USB3_PHY_LFPS_RXTERM_IRQ_CLEAR */ + 0xc04 /* USB3_PHY_POWER_DOWN_CONTROL */ + 0xc00 /* USB3_PHY_SW_RESET */ + 0xc08 /* USB3_PHY_START */ + 0xa00>; /* USB3PHY_PCS_MISC_TYPEC_CTRL */ + clocks = <&clock_gcc GCC_USB3_PHY_AUX_CLK>, <&clock_gcc GCC_USB3_PHY_PIPE_CLK>, <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, diff --git a/arch/arm/boot/dts/qcom/msmfalcon-rumi.dts b/arch/arm/boot/dts/qcom/msmfalcon-rumi.dts index 2b8a78ee1fdc..a23e82aea8b7 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-rumi.dts +++ b/arch/arm/boot/dts/qcom/msmfalcon-rumi.dts @@ -28,6 +28,7 @@ &usb3 { /delete-property/ USB3_GDSC-supply; + /delete-property/ extcon; dwc3@a800000 { maximum-speed = "high-speed"; }; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-sim.dts b/arch/arm/boot/dts/qcom/msmfalcon-sim.dts index d279e742c23a..fe92f40d786f 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-sim.dts +++ b/arch/arm/boot/dts/qcom/msmfalcon-sim.dts @@ -29,6 +29,7 @@ &usb3 { reg = <0xa800000 0xfc000>; reg-names = "core_base"; + /delete-property/ extcon; dwc3@a800000 { maximum-speed = "high-speed"; }; diff --git a/arch/arm/boot/dts/qcom/msmtriton-rumi.dts b/arch/arm/boot/dts/qcom/msmtriton-rumi.dts index 491b55aab9a6..723a0e0a6f99 100644 --- a/arch/arm/boot/dts/qcom/msmtriton-rumi.dts +++ b/arch/arm/boot/dts/qcom/msmtriton-rumi.dts @@ -23,6 +23,8 @@ }; &usb3 { + /delete-property/ USB3_GDSC-supply; + /delete-property/ extcon; dwc3@a800000 { maximum-speed = "high-speed"; }; From c8b3f11197d58a3e88293ceba0256a3e42ceb25d Mon Sep 17 00:00:00 2001 From: AnilKumar Chimata Date: Wed, 7 Dec 2016 14:51:13 +0530 Subject: [PATCH 29/51] defconfig: Enable ext4 ICE encryption for msmfalcon_32 Enable EXT4_FS_ICE_ENCRYPTION feature for msmfalcon_32 to use ICE for FBE. Change-Id: I991f3550720526b097c009dc852e9caaabf4860b Signed-off-by: AnilKumar Chimata --- arch/arm/configs/msmfalcon-perf_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/msmfalcon-perf_defconfig b/arch/arm/configs/msmfalcon-perf_defconfig index 86a9ac168d0e..5e36c8871914 100644 --- a/arch/arm/configs/msmfalcon-perf_defconfig +++ b/arch/arm/configs/msmfalcon-perf_defconfig @@ -548,6 +548,7 @@ CONFIG_EXT3_FS=y CONFIG_EXT4_FS_SECURITY=y CONFIG_EXT4_ENCRYPTION=y CONFIG_EXT4_FS_ENCRYPTION=y +CONFIG_EXT4_FS_ICE_ENCRYPTION=y CONFIG_EXT4_DEBUG=y CONFIG_FUSE_FS=y CONFIG_MSDOS_FS=y From d7c3ca1390eee2c293a24e1bf4be2f13be9d0105 Mon Sep 17 00:00:00 2001 From: AnilKumar Chimata Date: Tue, 6 Dec 2016 18:37:16 +0530 Subject: [PATCH 30/51] defconfig: Add missing features for HW Encryption support Enable SCSI_UFS_QCOM_ICE for msmfalcon_32 which is required for hardware encryption. Change-Id: I6f9afca5bebd5ad0745b064bb7d1a33f78fe6941 Signed-off-by: AnilKumar Chimata --- arch/arm/configs/msmfalcon-perf_defconfig | 1 + arch/arm/configs/msmfalcon_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/configs/msmfalcon-perf_defconfig b/arch/arm/configs/msmfalcon-perf_defconfig index 5e36c8871914..82854b1a4a06 100644 --- a/arch/arm/configs/msmfalcon-perf_defconfig +++ b/arch/arm/configs/msmfalcon-perf_defconfig @@ -249,6 +249,7 @@ CONFIG_SCSI_SCAN_ASYNC=y CONFIG_SCSI_UFSHCD=y CONFIG_SCSI_UFSHCD_PLATFORM=y CONFIG_SCSI_UFS_QCOM=y +CONFIG_SCSI_UFS_QCOM_ICE=y CONFIG_MD=y CONFIG_BLK_DEV_DM=y CONFIG_DM_CRYPT=y diff --git a/arch/arm/configs/msmfalcon_defconfig b/arch/arm/configs/msmfalcon_defconfig index b53d1bfec33e..af77a46862b7 100644 --- a/arch/arm/configs/msmfalcon_defconfig +++ b/arch/arm/configs/msmfalcon_defconfig @@ -248,6 +248,7 @@ CONFIG_SCSI_SCAN_ASYNC=y CONFIG_SCSI_UFSHCD=y CONFIG_SCSI_UFSHCD_PLATFORM=y CONFIG_SCSI_UFS_QCOM=y +CONFIG_SCSI_UFS_QCOM_ICE=y CONFIG_MD=y CONFIG_BLK_DEV_DM=y CONFIG_DM_CRYPT=y From 2964fdc17679972b80b4ec01b6c5377dab801f13 Mon Sep 17 00:00:00 2001 From: Gaurav Kohli Date: Tue, 6 Dec 2016 11:41:39 +0530 Subject: [PATCH 31/51] soc: qcom: pil: Use NULL check of resource pointer for restart register In failure case pointer to resource for restart register may be used while it is uninitialized. So use proper NULL check for the same. Change-Id: I3fc77b72e825f4b11724808239eea16aa126de42 Signed-off-by: Gaurav Kohli --- drivers/soc/qcom/pil-q6v5-mss.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/soc/qcom/pil-q6v5-mss.c b/drivers/soc/qcom/pil-q6v5-mss.c index 4ece8cf7907f..dc803bdfd554 100644 --- a/drivers/soc/qcom/pil-q6v5-mss.c +++ b/drivers/soc/qcom/pil-q6v5-mss.c @@ -285,6 +285,11 @@ static int pil_mss_loadable_init(struct modem_data *drv, if (!res) { res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "restart_reg_sec"); + if (!res) { + dev_err(&pdev->dev, "Failed to get resource for restart reg\n"); + return -EINVAL; + } + q6->restart_reg_sec = true; } From 375f27114e74a8f787d08df47650d288a62318c3 Mon Sep 17 00:00:00 2001 From: Anirudh Ghayal Date: Wed, 7 Dec 2016 15:54:32 +0530 Subject: [PATCH 32/51] ARM: dts: msm: Add pinctrl configuration for PMFALCOM L6/9/19 BT and WLAN vote for the regulator-mode via pinctrl. Add support for this. Change-Id: I95158cce1b20778547615141ffbbb7d81d5e10a1 Signed-off-by: Anirudh Ghayal --- .../boot/dts/qcom/msmfalcon-regulator.dtsi | 36 +++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm/boot/dts/qcom/msmfalcon-regulator.dtsi b/arch/arm/boot/dts/qcom/msmfalcon-regulator.dtsi index 0ab76c273ac3..02e61bcdd95c 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-regulator.dtsi +++ b/arch/arm/boot/dts/qcom/msmfalcon-regulator.dtsi @@ -176,6 +176,18 @@ regulator-max-microvolt = <1370000>; status = "okay"; }; + + pmfalcon_l6_pin_ctrl: regulator-l6-pin-ctrl { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pmfalcon_l6_pin_ctrl"; + qcom,set = <3>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1370000>; + /* Force NPM follows HW_EN1 */ + qcom,init-pin-ctrl-mode = <2>; + /* Enable follows HW_EN1 */ + qcom,enable-with-pin-ctrl = <0 2>; + }; }; rpm-regulator-ldoa7 { @@ -203,6 +215,18 @@ regulator-max-microvolt = <1900000>; status = "okay"; }; + + pmfalcon_l9_pin_ctrl: regulator-l9-pin-ctrl { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pmfalcon_l9_pin_ctrl"; + qcom,set = <3>; + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <1900000>; + /* Force NPM follows HW_EN1 */ + qcom,init-pin-ctrl-mode = <2>; + /* Enable follows HW_EN1 */ + qcom,enable-with-pin-ctrl = <0 2>; + }; }; rpm-regulator-ldoa10 { @@ -275,6 +299,18 @@ regulator-max-microvolt = <3400000>; status = "okay"; }; + + pmfalcon_l19_pin_ctrl: regulator-l19-pin-ctrl { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pmfalcon_l19_pin_ctrl"; + qcom,set = <3>; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3400000>; + /* Force NPM follows HW_EN1 */ + qcom,init-pin-ctrl-mode = <2>; + /* Enable follows HW_EN1 */ + qcom,enable-with-pin-ctrl = <0 2>; + }; }; rpm-regulator-ldob1 { From a1478993cf39a034d42e0ae176b082bf0eec0642 Mon Sep 17 00:00:00 2001 From: Ashay Jaiswal Date: Wed, 7 Dec 2016 16:39:53 +0530 Subject: [PATCH 33/51] defconfig: msm: msm8998: enable LCDB driver LCDB driver exposes regulators to control the positive and negative voltage bias for the LCD display panel. It also allows configurability for the various bias-voltage parameters. CRs-Fixed: 1074468 Change-Id: I68958c5ecfb71a11f346c5c46884948e4b36eea0 Signed-off-by: Ashay Jaiswal --- arch/arm/configs/msmcortex_defconfig | 1 + arch/arm64/configs/msmcortex-perf_defconfig | 1 + arch/arm64/configs/msmcortex_defconfig | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/arm/configs/msmcortex_defconfig b/arch/arm/configs/msmcortex_defconfig index b55857fd7cc4..9eaa449d4df6 100644 --- a/arch/arm/configs/msmcortex_defconfig +++ b/arch/arm/configs/msmcortex_defconfig @@ -312,6 +312,7 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_RPM_SMD=y CONFIG_REGULATOR_QPNP=y CONFIG_REGULATOR_QPNP_LABIBB=y +CONFIG_REGULATOR_QPNP_LCDB=y CONFIG_REGULATOR_SPM=y CONFIG_REGULATOR_CPR3_HMSS=y CONFIG_REGULATOR_CPR3_MMSS=y diff --git a/arch/arm64/configs/msmcortex-perf_defconfig b/arch/arm64/configs/msmcortex-perf_defconfig index 3a1d78adabf6..60bb033be6df 100644 --- a/arch/arm64/configs/msmcortex-perf_defconfig +++ b/arch/arm64/configs/msmcortex-perf_defconfig @@ -343,6 +343,7 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_RPM_SMD=y CONFIG_REGULATOR_QPNP=y CONFIG_REGULATOR_QPNP_LABIBB=y +CONFIG_REGULATOR_QPNP_LCDB=y CONFIG_REGULATOR_SPM=y CONFIG_REGULATOR_CPR3_HMSS=y CONFIG_REGULATOR_CPR3_MMSS=y diff --git a/arch/arm64/configs/msmcortex_defconfig b/arch/arm64/configs/msmcortex_defconfig index aecae7c8074b..1ef2d90f13de 100644 --- a/arch/arm64/configs/msmcortex_defconfig +++ b/arch/arm64/configs/msmcortex_defconfig @@ -346,6 +346,7 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_RPM_SMD=y CONFIG_REGULATOR_QPNP=y CONFIG_REGULATOR_QPNP_LABIBB=y +CONFIG_REGULATOR_QPNP_LCDB=y CONFIG_REGULATOR_SPM=y CONFIG_REGULATOR_CPR3_HMSS=y CONFIG_REGULATOR_CPR3_MMSS=y From 56dacc35025cf5cb19b547335d300f458a4fc3db Mon Sep 17 00:00:00 2001 From: Vijayavardhan Vennapusa Date: Wed, 7 Dec 2016 17:28:09 +0530 Subject: [PATCH 34/51] defconfig: msmfalcon: enable the USB video class support Enable USB video class support for msmfalcon for host video usecases. Change-Id: I30f8294527275a267bd88115a8a8d44beb2adfb8 Signed-off-by: Vijayavardhan Vennapusa --- arch/arm/configs/msmfalcon-perf_defconfig | 2 ++ arch/arm/configs/msmfalcon_defconfig | 2 ++ arch/arm64/configs/msmfalcon-perf_defconfig | 2 ++ arch/arm64/configs/msmfalcon_defconfig | 2 ++ 4 files changed, 8 insertions(+) diff --git a/arch/arm/configs/msmfalcon-perf_defconfig b/arch/arm/configs/msmfalcon-perf_defconfig index 86a9ac168d0e..95e3cedc406d 100644 --- a/arch/arm/configs/msmfalcon-perf_defconfig +++ b/arch/arm/configs/msmfalcon-perf_defconfig @@ -361,6 +361,8 @@ CONFIG_MEDIA_CONTROLLER=y CONFIG_VIDEO_V4L2_SUBDEV_API=y CONFIG_VIDEO_ADV_DEBUG=y CONFIG_VIDEO_FIXED_MINOR_RANGES=y +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_USB_VIDEO_CLASS=y CONFIG_V4L_PLATFORM_DRIVERS=y CONFIG_MSM_CAMERA=y CONFIG_MSM_CAMERA_DEBUG=y diff --git a/arch/arm/configs/msmfalcon_defconfig b/arch/arm/configs/msmfalcon_defconfig index b53d1bfec33e..914c30dd0f3e 100644 --- a/arch/arm/configs/msmfalcon_defconfig +++ b/arch/arm/configs/msmfalcon_defconfig @@ -360,6 +360,8 @@ CONFIG_MEDIA_CONTROLLER=y CONFIG_VIDEO_V4L2_SUBDEV_API=y CONFIG_VIDEO_ADV_DEBUG=y CONFIG_VIDEO_FIXED_MINOR_RANGES=y +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_USB_VIDEO_CLASS=y CONFIG_V4L_PLATFORM_DRIVERS=y CONFIG_MSM_CAMERA=y CONFIG_MSM_CAMERA_DEBUG=y diff --git a/arch/arm64/configs/msmfalcon-perf_defconfig b/arch/arm64/configs/msmfalcon-perf_defconfig index 148cb523cbc9..60486957dc29 100644 --- a/arch/arm64/configs/msmfalcon-perf_defconfig +++ b/arch/arm64/configs/msmfalcon-perf_defconfig @@ -360,6 +360,8 @@ CONFIG_MEDIA_CONTROLLER=y CONFIG_VIDEO_V4L2_SUBDEV_API=y CONFIG_VIDEO_ADV_DEBUG=y CONFIG_VIDEO_FIXED_MINOR_RANGES=y +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_USB_VIDEO_CLASS=y CONFIG_V4L_PLATFORM_DRIVERS=y CONFIG_MSM_CAMERA=y CONFIG_MSM_CAMERA_DEBUG=y diff --git a/arch/arm64/configs/msmfalcon_defconfig b/arch/arm64/configs/msmfalcon_defconfig index 26ad84e5ecca..543e2740bb0a 100644 --- a/arch/arm64/configs/msmfalcon_defconfig +++ b/arch/arm64/configs/msmfalcon_defconfig @@ -362,6 +362,8 @@ CONFIG_MEDIA_CONTROLLER=y CONFIG_VIDEO_V4L2_SUBDEV_API=y CONFIG_VIDEO_ADV_DEBUG=y CONFIG_VIDEO_FIXED_MINOR_RANGES=y +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_USB_VIDEO_CLASS=y CONFIG_V4L_PLATFORM_DRIVERS=y CONFIG_MSM_CAMERA=y CONFIG_MSM_CAMERA_DEBUG=y From 37e0cf7dc991fad303ae676cc0feefe9c3c238fd Mon Sep 17 00:00:00 2001 From: Charan Teja Reddy Date: Thu, 1 Dec 2016 15:52:12 +0530 Subject: [PATCH 35/51] ARM: dts: msm: update the smmu device node configuration for msmfalcon Update the SMMU device node configuration for correct operation of SMMU on msmfalcon. Change-Id: I29fa8f488df800d38f6403646e58a19e555ba1cd Signed-off-by: Charan Teja Reddy --- arch/arm/boot/dts/qcom/msm-arm-smmu-falcon.dtsi | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/qcom/msm-arm-smmu-falcon.dtsi b/arch/arm/boot/dts/qcom/msm-arm-smmu-falcon.dtsi index e4824418409b..ff4db75d9aff 100644 --- a/arch/arm/boot/dts/qcom/msm-arm-smmu-falcon.dtsi +++ b/arch/arm/boot/dts/qcom/msm-arm-smmu-falcon.dtsi @@ -13,7 +13,6 @@ #include #include #include -#include #include &soc { @@ -61,7 +60,6 @@ }; lpass_q6_smmu: arm,smmu-lpass_q6@5100000 { - status = "disabled"; compatible = "qcom,smmu-v2"; reg = <0x5100000 0x40000>; #iommu-cells = <1>; @@ -94,11 +92,11 @@ }; mmss_bimc_smmu: arm,smmu-mmss@cd00000 { - status = "disabled"; compatible = "qcom,smmu-v2"; reg = <0xcd00000 0x40000>; #iommu-cells = <1>; qcom,register-save; + qcom,no-smr-check; qcom,skip-init; #global-interrupts = <2>; interrupts = , @@ -129,7 +127,7 @@ ; vdd-supply = <&gdsc_bimc_smmu>; clocks = <&clock_mmss MMSS_MNOC_AHB_CLK>, - <&clock_gcc MMSSNOC_AXI_CLK>, + <&clock_rpmcc MMSSNOC_AXI_CLK>, <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>, <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>; clock-names = "mmss_mnoc_ahb_clk", @@ -137,11 +135,9 @@ "mmss_bimc_smmu_ahb_clk", "mmss_bimc_smmu_axi_clk"; #clock-cells = <1>; - qcom,bus-master-id = ; }; kgsl_smmu: arm,smmu-kgsl@5040000 { - status = "disabled"; compatible = "qcom,smmu-v2"; reg = <0x5040000 0x10000>; #iommu-cells = <1>; @@ -170,7 +166,6 @@ }; turing_q6_smmu: arm,smmu-turing_q6@5180000 { - status = "disabled"; compatible = "qcom,smmu-v2"; reg = <0x5180000 0x40000>; #iommu-cells = <1>; From 6e71895900ab48221aa3c630b54288e066c3f124 Mon Sep 17 00:00:00 2001 From: Vijayavardhan Vennapusa Date: Tue, 6 Dec 2016 18:07:32 +0530 Subject: [PATCH 36/51] ARM: dts: msm: Attach device memory to lpass iommu on msmfalcon In order to share the usb audio qmi device iova with lpass usb audio driver, attach usb audio qmi device to lpass q6 iommu using sid 6. Change-Id: I6b3c9b49ac973f2472391b3f702908212e3f6e7d Signed-off-by: Vijayavardhan Vennapusa --- arch/arm/boot/dts/qcom/msmfalcon-common.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/qcom/msmfalcon-common.dtsi b/arch/arm/boot/dts/qcom/msmfalcon-common.dtsi index b2bad31d12d4..9769020b01e5 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-common.dtsi +++ b/arch/arm/boot/dts/qcom/msmfalcon-common.dtsi @@ -190,6 +190,13 @@ reset-names = "phy_reset", "phy_phy_reset"; }; + usb_audio_qmi_dev { + compatible = "qcom,usb-audio-qmi-dev"; + iommus = <&lpass_q6_smmu 6>; + qcom,usb-audio-stream-id = <6>; + qcom,usb-audio-intr-num = <2>; + }; + dbm_1p5: dbm@a8f8000 { compatible = "qcom,usb-dbm-1p5"; reg = <0xa8f8000 0x300>; From 256de04b8de29c89f91ad1eba1e7522d3ac9177d Mon Sep 17 00:00:00 2001 From: Lokesh Batra Date: Wed, 23 Mar 2016 11:59:12 -0700 Subject: [PATCH 37/51] msm: kgsl: Add trace ID support for graphics coresight Add the support for trace ID for coresight. This ID is will be defined in the respective device tree file. Change-Id: I78ba05ed05b54fdc0f4d4f55c468f90f39c821f1 Signed-off-by: Lokesh Batra Signed-off-by: Harshdeep Dhatt --- Documentation/devicetree/bindings/gpu/adreno.txt | 2 +- drivers/gpu/msm/adreno.h | 2 ++ drivers/gpu/msm/adreno_coresight.c | 12 ++++++++++++ 3 files changed, 15 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/gpu/adreno.txt b/Documentation/devicetree/bindings/gpu/adreno.txt index 8a79626125d9..f5ae85d27692 100644 --- a/Documentation/devicetree/bindings/gpu/adreno.txt +++ b/Documentation/devicetree/bindings/gpu/adreno.txt @@ -187,7 +187,7 @@ Documentation/devicetree/bindings/coresight/coresight.txt - coresight-child-list List of phandles pointing to the children of this component. - coresight-child-ports List of input port numbers of the children. - +- coresight-atid The unique ATID value of the coresight device Example of A330 GPU in MSM8916: diff --git a/drivers/gpu/msm/adreno.h b/drivers/gpu/msm/adreno.h index 1c30b43fdfcf..2c8345aadc07 100644 --- a/drivers/gpu/msm/adreno.h +++ b/drivers/gpu/msm/adreno.h @@ -676,11 +676,13 @@ ssize_t adreno_coresight_store_register(struct device *dev, * @registers - Array of GPU specific registers to configure trace bus output * @count - Number of registers in the array * @groups - Pointer to an attribute list of control files + * @atid - The unique ATID value of the coresight device */ struct adreno_coresight { struct adreno_coresight_register *registers; unsigned int count; const struct attribute_group **groups; + unsigned int atid; }; diff --git a/drivers/gpu/msm/adreno_coresight.c b/drivers/gpu/msm/adreno_coresight.c index 02a39278ccb3..901e2144c6d8 100644 --- a/drivers/gpu/msm/adreno_coresight.c +++ b/drivers/gpu/msm/adreno_coresight.c @@ -200,6 +200,9 @@ static int _adreno_coresight_set(struct adreno_device *adreno_dev) kgsl_regwrite(device, coresight->registers[i].offset, coresight->registers[i].value); + kgsl_property_read_u32(device, "coresight-atid", + (unsigned int *)&(coresight->atid)); + return 0; } /** @@ -281,7 +284,16 @@ void adreno_coresight_start(struct adreno_device *adreno_dev) _adreno_coresight_set(adreno_dev); } +static int adreno_coresight_trace_id(struct coresight_device *csdev) +{ + struct kgsl_device *device = dev_get_drvdata(csdev->dev.parent); + struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(ADRENO_DEVICE(device)); + + return gpudev->coresight->atid; +} + static const struct coresight_ops_source adreno_coresight_source_ops = { + .trace_id = adreno_coresight_trace_id, .enable = adreno_coresight_enable, .disable = adreno_coresight_disable, }; From 20d34be35455dc2cb69e2211b8e6d9ac0a6b5518 Mon Sep 17 00:00:00 2001 From: Rupesh Tatiya Date: Mon, 21 Nov 2016 12:56:36 +0530 Subject: [PATCH 38/51] ARM: dts: msm: update wcn3990 node for msm8998 interposer Disable qca, wcn3990 bluetooth node to avoid failure in bootup. Change-Id: I7c6700a44c45360acf8aebc0ab9264c2e08abc8f Signed-off-by: Rupesh Tatiya --- arch/arm/boot/dts/qcom/msm8998-interposer-msmfalcon-cdp.dtsi | 1 + arch/arm/boot/dts/qcom/msm8998-interposer-msmfalcon-mtp.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/qcom/msm8998-interposer-msmfalcon-cdp.dtsi b/arch/arm/boot/dts/qcom/msm8998-interposer-msmfalcon-cdp.dtsi index a2193de57dea..437b054a6ad0 100644 --- a/arch/arm/boot/dts/qcom/msm8998-interposer-msmfalcon-cdp.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-interposer-msmfalcon-cdp.dtsi @@ -14,6 +14,7 @@ #include "msm8998-camera-sensor-cdp.dtsi" / { bluetooth: bt_wcn3990 { + status = "disabled"; compatible = "qca,wcn3990"; qca,bt-vdd-io-supply = <&pm8998_s3>; qca,bt-vdd-xtal-supply = <&pm8998_s5>; diff --git a/arch/arm/boot/dts/qcom/msm8998-interposer-msmfalcon-mtp.dtsi b/arch/arm/boot/dts/qcom/msm8998-interposer-msmfalcon-mtp.dtsi index 9257c031d2f9..e9c64c12c419 100644 --- a/arch/arm/boot/dts/qcom/msm8998-interposer-msmfalcon-mtp.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-interposer-msmfalcon-mtp.dtsi @@ -15,6 +15,7 @@ #include "msm8998-camera-sensor-mtp.dtsi" / { bluetooth: bt_wcn3990 { + status = "disabled"; compatible = "qca,wcn3990"; qca,bt-vdd-io-supply = <&pm8998_s3>; qca,bt-vdd-xtal-supply = <&pm8998_s5>; From 64a7b2e649b19e747fa805079c203f1d8753a81d Mon Sep 17 00:00:00 2001 From: Ram Chandrasekar Date: Wed, 23 Nov 2016 14:21:47 -0700 Subject: [PATCH 39/51] msm: lmh_dcvsh: Support new API to notify scheduler HLOS can place a mitigation frequency via the LMH DCVSh hardware using the software cap register and this request doesn't trigger a debug interrupt. Thus, this frequency mitigation change will not result in scheduler being notified by LMH DCVSh driver. Introduce a new API in LMH DCVSh driver, that can be used by other drivers to trigger the scheduler notification. This API and the interrupt handler follows the same code path to poll and notify the scheduler. Change-Id: Iefcdb57ff598ecb1bafc535958684f75b1f6e645 Signed-off-by: Ram Chandrasekar --- drivers/thermal/msm_lmh_dcvs.c | 32 +++++++++++++++++++++++++++----- include/linux/msm_thermal.h | 13 +++++++++++++ 2 files changed, 40 insertions(+), 5 deletions(-) diff --git a/drivers/thermal/msm_lmh_dcvs.c b/drivers/thermal/msm_lmh_dcvs.c index 3758e39a1c02..ac1da854ab32 100644 --- a/drivers/thermal/msm_lmh_dcvs.c +++ b/drivers/thermal/msm_lmh_dcvs.c @@ -25,6 +25,8 @@ #include #include #include +#include +#include #include #include @@ -83,6 +85,7 @@ struct msm_lmh_dcvs_hw { uint32_t max_freq; uint32_t hw_freq_limit; struct list_head list; + DECLARE_BITMAP(is_irq_enabled, 1); }; LIST_HEAD(lmh_dcvs_hw_list); @@ -145,6 +148,7 @@ static void msm_lmh_dcvs_poll(unsigned long data) if (max_limit >= hw->max_freq) { del_timer(&hw->poll_timer); writel_relaxed(0xFF, hw->int_clr_reg); + set_bit(1, hw->is_irq_enabled); enable_irq(hw->irq_num); } else { mod_timer(&hw->poll_timer, jiffies + msecs_to_jiffies( @@ -152,15 +156,21 @@ static void msm_lmh_dcvs_poll(unsigned long data) } } +static void lmh_dcvs_notify(struct msm_lmh_dcvs_hw *hw) +{ + if (test_and_clear_bit(1, hw->is_irq_enabled)) { + disable_irq_nosync(hw->irq_num); + msm_lmh_mitigation_notify(hw); + mod_timer(&hw->poll_timer, jiffies + msecs_to_jiffies( + MSM_LIMITS_POLLING_DELAY_MS)); + } +} + static irqreturn_t lmh_dcvs_handle_isr(int irq, void *data) { struct msm_lmh_dcvs_hw *hw = data; - disable_irq_nosync(irq); - msm_lmh_mitigation_notify(hw); - mod_timer(&hw->poll_timer, jiffies + msecs_to_jiffies( - MSM_LIMITS_POLLING_DELAY_MS)); - + lmh_dcvs_notify(hw); return IRQ_HANDLED; } @@ -314,6 +324,17 @@ static struct cpu_cooling_ops cd_ops = { .ceil_limit = lmh_set_max_limit, }; +int msm_lmh_dcvsh_sw_notify(int cpu) +{ + struct msm_lmh_dcvs_hw *hw = get_dcvsh_hw_from_cpu(cpu); + + if (!hw) + return -EINVAL; + + lmh_dcvs_notify(hw); + return 0; +} + static int msm_lmh_dcvs_probe(struct platform_device *pdev) { int ret; @@ -460,6 +481,7 @@ static int msm_lmh_dcvs_probe(struct platform_device *pdev) pr_err("Error getting IRQ number. err:%d\n", ret); return ret; } + set_bit(1, hw->is_irq_enabled); ret = devm_request_threaded_irq(&pdev->dev, hw->irq_num, NULL, lmh_dcvs_handle_isr, IRQF_TRIGGER_HIGH | IRQF_ONESHOT | IRQF_NO_SUSPEND, sensor_name, hw); diff --git a/include/linux/msm_thermal.h b/include/linux/msm_thermal.h index f3ec960536aa..33286c2d81fc 100644 --- a/include/linux/msm_thermal.h +++ b/include/linux/msm_thermal.h @@ -255,6 +255,15 @@ extern int devmgr_client_request_mitigation(struct device_clnt_data *clnt, extern void devmgr_unregister_mitigation_client( struct device *dev, struct device_clnt_data *clnt); +#ifdef CONFIG_QCOM_THERMAL_LIMITS_DCVS +extern int msm_lmh_dcvsh_sw_notify(int cpu); +#else +static inline int msm_lmh_dcvsh_sw_notify(int cpu) +{ + return -ENODEV; +} +#endif + #else static inline int msm_thermal_init(struct msm_thermal_data *pdata) { @@ -330,6 +339,10 @@ static inline void devmgr_unregister_mitigation_client( struct device_clnt_data *clnt) { } +static inline int msm_lmh_dcvsh_sw_notify(int cpu) +{ + return -ENODEV; +} #endif #endif /*__MSM_THERMAL_H*/ From a5dea1fbd6544ca5911671db71fab6916d61878d Mon Sep 17 00:00:00 2001 From: Harry Yang Date: Mon, 5 Dec 2016 09:58:12 -0800 Subject: [PATCH 40/51] power_supply: Add BOOST_CURRENT property This property will be used to indicate to the boost current after the boost is turned on. CRs-Fixed: 1095917 Change-Id: Ie667fa49c4a8e8c008e8866f655e3bbe3e69e156 Signed-off-by: Harry Yang --- drivers/power/power_supply_sysfs.c | 1 + include/linux/power_supply.h | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/power/power_supply_sysfs.c b/drivers/power/power_supply_sysfs.c index 2718ea93bd45..d83928901a77 100644 --- a/drivers/power/power_supply_sysfs.c +++ b/drivers/power/power_supply_sysfs.c @@ -250,6 +250,7 @@ static struct device_attribute power_supply_attrs[] = { POWER_SUPPLY_ATTR(update_now), POWER_SUPPLY_ATTR(esr_count), POWER_SUPPLY_ATTR(buck_freq), + POWER_SUPPLY_ATTR(boost_current), POWER_SUPPLY_ATTR(safety_timer_enabled), POWER_SUPPLY_ATTR(charge_done), POWER_SUPPLY_ATTR(flash_active), diff --git a/include/linux/power_supply.h b/include/linux/power_supply.h index 18e1a979db76..125568f7862c 100644 --- a/include/linux/power_supply.h +++ b/include/linux/power_supply.h @@ -199,6 +199,7 @@ enum power_supply_property { POWER_SUPPLY_PROP_UPDATE_NOW, POWER_SUPPLY_PROP_ESR_COUNT, POWER_SUPPLY_PROP_BUCK_FREQ, + POWER_SUPPLY_PROP_BOOST_CURRENT, POWER_SUPPLY_PROP_SAFETY_TIMER_ENABLE, POWER_SUPPLY_PROP_CHARGE_DONE, POWER_SUPPLY_PROP_FLASH_ACTIVE, From e219034e0473f7cade281d7e59d9cc6418040884 Mon Sep 17 00:00:00 2001 From: Ram Chandrasekar Date: Wed, 23 Nov 2016 14:39:13 -0700 Subject: [PATCH 41/51] msm: thermal: Notify LMH DCVSh driver after freq mitigation request LMH DCVSh hardware doesn't generate a debug interrupt, when HLOS CPU frequency cap is the only throttling value coming to the hardware aggregator logic. The LMH DCVSh requires atleast one of the hardware algorithm to throttle to generate a debug interrupt. So there will be a case where, LMH DCVS driver won't notify scheduler about the throttling frequency if HLOS is the only reason for throttling. LMH DCVSh driver now exposes a new API, to trigger the frequency polling loop. KTM is updated to use this API to trigger the LMH DCVSh polling, whenever there is a new software frequency cap. This will ensure that the LMH DCVSh will notify the scheduler even if software is the only throttling reason. Change-Id: I92b1bd9a5efc9810eea721b088dff1bd6eef3838 Signed-off-by: Ram Chandrasekar --- drivers/thermal/msm_thermal.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/thermal/msm_thermal.c b/drivers/thermal/msm_thermal.c index 002cafb08f37..7158fb1239df 100644 --- a/drivers/thermal/msm_thermal.c +++ b/drivers/thermal/msm_thermal.c @@ -1056,6 +1056,11 @@ static int msm_lmh_dcvs_update(int cpu) MSM_LIMITS_DOMAIN_MIN, min_freq); if (ret) return ret; + /* + * Notify LMH dcvs driver about the new software limit. This will + * trigger LMH DCVS driver polling for the mitigated frequency. + */ + msm_lmh_dcvsh_sw_notify(cpu); return ret; } From 38b489ccd4c78d3d1bf69a1a0a57812d0fc0d73e Mon Sep 17 00:00:00 2001 From: Skylar Chang Date: Tue, 29 Nov 2016 13:36:24 -0800 Subject: [PATCH 42/51] msm: ipa3: check the rx_door_bell value on disable In WDI2.0, seeing some issue about rdy_ring_rp_va is not equal to rdy_comp_ring_wp_va because wlan-fw still update the doorbell after ipa host-driver issue the CH_DISABLE cmd to ipa-uc. The fix is to compare rdy_comp_ring_wp_va and rx_door_bell values instead. Change-Id: Ibe57c7d5ba9e45260c12528910f173e347259d7c Signed-off-by: Skylar Chang --- drivers/platform/msm/ipa/ipa_v3/ipa_uc_wdi.c | 55 +++++++++++-------- .../msm/ipa/ipa_v3/ipahal/ipahal_reg.c | 32 +++++++++++ .../msm/ipa/ipa_v3/ipahal/ipahal_reg.h | 5 ++ 3 files changed, 69 insertions(+), 23 deletions(-) diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_uc_wdi.c b/drivers/platform/msm/ipa/ipa_v3/ipa_uc_wdi.c index ab4911462ddf..e38f6f2860cf 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa_uc_wdi.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa_uc_wdi.c @@ -1356,6 +1356,7 @@ int ipa3_disable_wdi_pipe(u32 clnt_hdl) struct ipa_ep_cfg_ctrl ep_cfg_ctrl; u32 prod_hdl; int i; + u32 rx_door_bell_value; if (clnt_hdl >= ipa3_ctx->ipa_num_pipes || ipa3_ctx->ep[clnt_hdl].valid == 0) { @@ -1367,28 +1368,6 @@ int ipa3_disable_wdi_pipe(u32 clnt_hdl) if (result) return result; - /* checking rdy_ring_rp_pa matches the rdy_comp_ring_wp_pa on WDI2.0 */ - if (ipa3_ctx->ipa_wdi2) { - for (i = 0; i < IPA_UC_FINISH_MAX; i++) { - IPADBG("(%d) rp_value(%u), comp_wp_value(%u)\n", - i, - *ipa3_ctx->uc_ctx.rdy_ring_rp_va, - *ipa3_ctx->uc_ctx.rdy_comp_ring_wp_va); - if (*ipa3_ctx->uc_ctx.rdy_ring_rp_va != - *ipa3_ctx->uc_ctx.rdy_comp_ring_wp_va) { - usleep_range(IPA_UC_WAIT_MIN_SLEEP, - IPA_UC_WAII_MAX_SLEEP); - } else { - break; - } - } - /* In case ipa_uc still haven't processed all - * pending descriptors, we have to assert - */ - if (i == IPA_UC_FINISH_MAX) - WARN_ON(1); - } - IPADBG("ep=%d\n", clnt_hdl); ep = &ipa3_ctx->ep[clnt_hdl]; @@ -1429,10 +1408,40 @@ int ipa3_disable_wdi_pipe(u32 clnt_hdl) } usleep_range(IPA_UC_POLL_SLEEP_USEC * IPA_UC_POLL_SLEEP_USEC, IPA_UC_POLL_SLEEP_USEC * IPA_UC_POLL_SLEEP_USEC); + + /* + * checking rdy_ring_rp_pa matches the + * rdy_comp_ring_wp_pa on WDI2.0 + */ + if (ipa3_ctx->ipa_wdi2) { + for (i = 0; i < IPA_UC_FINISH_MAX; i++) { + rx_door_bell_value = ipahal_read_reg_mn( + IPA_UC_MAILBOX_m_n, + IPA_HW_WDI_RX_MBOX_START_INDEX/32, + IPA_HW_WDI_RX_MBOX_START_INDEX % 32); + IPADBG("(%d)rx_DB(%u)rp(%u),comp_wp(%u)\n", + i, + rx_door_bell_value, + *ipa3_ctx->uc_ctx.rdy_ring_rp_va, + *ipa3_ctx->uc_ctx.rdy_comp_ring_wp_va); + if (rx_door_bell_value != + *ipa3_ctx->uc_ctx.rdy_comp_ring_wp_va) { + usleep_range(IPA_UC_WAIT_MIN_SLEEP, + IPA_UC_WAII_MAX_SLEEP); + } else { + break; + } + } + /* + * In case ipa_uc still haven't processed all + * pending descriptors, we have to assert + */ + if (i == IPA_UC_FINISH_MAX) + ipa_assert(); + } } disable.params.ipa_pipe_number = clnt_hdl; - result = ipa3_uc_send_cmd(disable.raw32b, IPA_CPU_2_HW_CMD_WDI_CH_DISABLE, IPA_HW_2_CPU_WDI_CMD_STATUS_SUCCESS, diff --git a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.c b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.c index cef9f7ef3fe4..347a8c418ebb 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.c @@ -1286,6 +1286,38 @@ u32 ipahal_read_reg_n(enum ipahal_reg_name reg, u32 n) return ioread32(ipahal_ctx->base + offset); } +/* + * ipahal_read_reg_mn() - Get mn parameterized reg value + */ +u32 ipahal_read_reg_mn(enum ipahal_reg_name reg, u32 m, u32 n) +{ + u32 offset; + + if (reg >= IPA_REG_MAX) { + IPAHAL_ERR("Invalid register reg=%u\n", reg); + return -EFAULT; + } + + IPAHAL_DBG_LOW("read %s m=%u n=%u\n", + ipahal_reg_name_str(reg), m, n); + offset = ipahal_reg_objs[ipahal_ctx->hw_type][reg].offset; + if (offset == -1) { + IPAHAL_ERR("Read access to obsolete reg=%s\n", + ipahal_reg_name_str(reg)); + WARN_ON_ONCE(1); + return -EFAULT; + } + /* + * Currently there is one register with m and n parameters + * IPA_UC_MAILBOX_m_n. The m value of it is 0x80. + * If more such registers will be added in the future, + * we can move the m parameter to the table above. + */ + offset += 0x80 * m; + offset += ipahal_reg_objs[ipahal_ctx->hw_type][reg].n_ofst * n; + return ioread32(ipahal_ctx->base + offset); +} + /* * ipahal_write_reg_mn() - Write to m/n parameterized reg a raw value */ diff --git a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.h b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.h index 8fb9040360ea..5f1e3fe410b1 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.h +++ b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.h @@ -340,6 +340,11 @@ const char *ipahal_reg_name_str(enum ipahal_reg_name reg_name); */ u32 ipahal_read_reg_n(enum ipahal_reg_name reg, u32 n); +/* + * ipahal_read_reg_mn() - Get mn parameterized reg value + */ +u32 ipahal_read_reg_mn(enum ipahal_reg_name reg, u32 m, u32 n); + /* * ipahal_write_reg_mn() - Write to m/n parameterized reg a raw value */ From ac4034d803e0adee0dfa826fadf607f6bf4d148d Mon Sep 17 00:00:00 2001 From: Lokesh Batra Date: Tue, 8 Mar 2016 05:40:03 -0800 Subject: [PATCH 43/51] ARM: dts: msm: Add GPU coresight properties for msm8998 Add properties in the GPU device tree for coresight. Define GPU name and its funnel connections. CR-fixed: 988516 Change-Id: Ibf2e369c2a4732ebc7471ee103bc8d5d934247ec Signed-off-by: Lokesh Batra --- arch/arm/boot/dts/qcom/msm8998-coresight.dtsi | 8 ++++++++ arch/arm/boot/dts/qcom/msm8998-gpu.dtsi | 8 ++++++++ 2 files changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/qcom/msm8998-coresight.dtsi b/arch/arm/boot/dts/qcom/msm8998-coresight.dtsi index aeb6bf6141d8..75a90b0499e1 100644 --- a/arch/arm/boot/dts/qcom/msm8998-coresight.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-coresight.dtsi @@ -277,6 +277,14 @@ <&funnel_apss_merg_out_funnel_in1>; }; }; + port@6 { + reg = <7>; + funnel_in1_in_gfx: endpoint { + slave-mode; + remote-endpoint = + <&gfx_out_funnel_in1>; + }; + }; }; }; diff --git a/arch/arm/boot/dts/qcom/msm8998-gpu.dtsi b/arch/arm/boot/dts/qcom/msm8998-gpu.dtsi index 8739e8f22549..c85493d54e35 100644 --- a/arch/arm/boot/dts/qcom/msm8998-gpu.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-gpu.dtsi @@ -122,6 +122,14 @@ vddcx-supply = <&gdsc_gpu_cx>; vdd-supply = <&gdsc_gpu_gx>; + /* Trace bus */ + coresight-name = "coresight-gfx"; + port { + gfx_out_funnel_in1: endpoint { + remote-endpoint = <&funnel_in1_in_gfx>; + }; + }; + /* GPU Mempools */ qcom,gpu-mempools { #address-cells= <1>; From ac782356a0d0fa7242e289f1fc750fda7f014fee Mon Sep 17 00:00:00 2001 From: Harshdeep Dhatt Date: Wed, 23 Nov 2016 16:06:06 -0700 Subject: [PATCH 44/51] ARM: dts: msm: Specify coresight trace ID for msm8998 Specify the graphics coresight trace ID in the device tree file. Change-Id: I30a10a63b320cd3cb6d7cc4ef2fba423f697a66f Signed-off-by: Harshdeep Dhatt --- arch/arm/boot/dts/qcom/msm8998-gpu.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/qcom/msm8998-gpu.dtsi b/arch/arm/boot/dts/qcom/msm8998-gpu.dtsi index c85493d54e35..9a497a473a56 100644 --- a/arch/arm/boot/dts/qcom/msm8998-gpu.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-gpu.dtsi @@ -124,6 +124,7 @@ /* Trace bus */ coresight-name = "coresight-gfx"; + coresight-atid = <3>; port { gfx_out_funnel_in1: endpoint { remote-endpoint = <&funnel_in1_in_gfx>; From 9c6653b0b14ecd6ad49ad02ea397a72dacfcc954 Mon Sep 17 00:00:00 2001 From: Ashay Jaiswal Date: Wed, 7 Dec 2016 11:21:32 +0530 Subject: [PATCH 45/51] qpnp-fg-gen3: Add support for PMFALCON in Fuel Gauge Add support of PMFALCON PMIC in FG driver. PMFALCON FG core uses same SRAM map as PMI8998v2.0. While at it, add workaround flag variable to keep track of all hardware specific workarounds. CRs-Fixed: 1096793 Change-Id: I8ba73276fd30f6eaf935ed77b75601f1322c0ba6 Signed-off-by: Ashay Jaiswal --- drivers/power/qcom-charger/fg-core.h | 5 +++++ drivers/power/qcom-charger/qpnp-fg-gen3.c | 19 ++++++++++++------- 2 files changed, 17 insertions(+), 7 deletions(-) diff --git a/drivers/power/qcom-charger/fg-core.h b/drivers/power/qcom-charger/fg-core.h index f0de532f196c..9ddd18800f9d 100644 --- a/drivers/power/qcom-charger/fg-core.h +++ b/drivers/power/qcom-charger/fg-core.h @@ -188,6 +188,10 @@ struct fg_alg_flag { bool invalid; }; +enum wa_flags { + PMI8998_V1_REV_WA = BIT(0), +}; + /* DT parameters for FG device */ struct fg_dt_props { bool force_load_profile; @@ -306,6 +310,7 @@ struct fg_chip { u32 batt_soc_base; u32 batt_info_base; u32 mem_if_base; + u32 wa_flags; int batt_id_kohms; int charge_status; int prev_charge_status; diff --git a/drivers/power/qcom-charger/qpnp-fg-gen3.c b/drivers/power/qcom-charger/qpnp-fg-gen3.c index 4d2cfc84d455..84204163f076 100644 --- a/drivers/power/qcom-charger/qpnp-fg-gen3.c +++ b/drivers/power/qcom-charger/qpnp-fg-gen3.c @@ -550,7 +550,7 @@ static int fg_get_battery_esr(struct fg_chip *chip, int *val) return rc; } - if (chip->pmic_rev_id->rev4 < PMI8998_V2P0_REV4) + if (chip->wa_flags & PMI8998_V1_REV_WA) temp = ((buf[0] & ESR_MSB_MASK) << 8) | (buf[1] & ESR_LSB_MASK); else @@ -597,7 +597,7 @@ static int fg_get_battery_current(struct fg_chip *chip, int *val) return rc; } - if (chip->pmic_rev_id->rev4 < PMI8998_V2P0_REV4) + if (chip->wa_flags & PMI8998_V1_REV_WA) temp = buf[0] << 8 | buf[1]; else temp = buf[1] << 8 | buf[0]; @@ -624,7 +624,7 @@ static int fg_get_battery_voltage(struct fg_chip *chip, int *val) return rc; } - if (chip->pmic_rev_id->rev4 < PMI8998_V2P0_REV4) + if (chip->wa_flags & PMI8998_V1_REV_WA) temp = buf[0] << 8 | buf[1]; else temp = buf[1] << 8 | buf[0]; @@ -2401,8 +2401,8 @@ static int fg_hw_init(struct fg_chip *chip) } /* This SRAM register is only present in v2.0 and above */ - if (chip->pmic_rev_id->rev4 >= PMI8998_V2P0_REV4 && - chip->bp.float_volt_uv > 0) { + if (!(chip->wa_flags & PMI8998_V1_REV_WA) && + chip->bp.float_volt_uv > 0) { fg_encode(chip->sp, FG_SRAM_FLOAT_VOLT, chip->bp.float_volt_uv / 1000, buf); rc = fg_sram_write(chip, chip->sp[FG_SRAM_FLOAT_VOLT].addr_word, @@ -2482,8 +2482,8 @@ static int fg_hw_init(struct fg_chip *chip) } /* This configuration is available only for pmicobalt v2.0 and above */ - if (chip->pmic_rev_id->rev4 >= PMI8998_V2P0_REV4 && - chip->dt.recharge_volt_thr_mv > 0) { + if (!(chip->wa_flags & PMI8998_V1_REV_WA) && + chip->dt.recharge_volt_thr_mv > 0) { fg_encode(chip->sp, FG_SRAM_RECHARGE_VBATT_THR, chip->dt.recharge_volt_thr_mv, buf); rc = fg_sram_write(chip, @@ -3013,6 +3013,7 @@ static int fg_parse_dt(struct fg_chip *chip) if (chip->pmic_rev_id->rev4 < PMI8998_V2P0_REV4) { chip->sp = pmi8998_v1_sram_params; chip->alg_flags = pmi8998_v1_alg_flags; + chip->wa_flags |= PMI8998_V1_REV_WA; } else if (chip->pmic_rev_id->rev4 == PMI8998_V2P0_REV4) { chip->sp = pmi8998_v2_sram_params; chip->alg_flags = pmi8998_v2_alg_flags; @@ -3020,6 +3021,10 @@ static int fg_parse_dt(struct fg_chip *chip) return -EINVAL; } break; + case PMFALCON_SUBTYPE: + chip->sp = pmi8998_v2_sram_params; + chip->alg_flags = pmi8998_v2_alg_flags; + break; default: return -EINVAL; } From 043b01d09a7b4c5b353c6cb4c55c8c2a9384b938 Mon Sep 17 00:00:00 2001 From: Meng Wang Date: Mon, 28 Nov 2016 17:25:20 +0800 Subject: [PATCH 46/51] include: clock: remove ifdef from header file As audio-ext-clk.h is finally included in device tree and and using ifdef results in compilation failure. Delete ifdef from audio-ext-clk.h. CRs-Fixed: 1090500 Change-Id: Ib6f715c3f606770e7e0b1f0f84ab50e442398cd0 Signed-off-by: Meng Wang --- include/dt-bindings/clock/audio-ext-clk.h | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/include/dt-bindings/clock/audio-ext-clk.h b/include/dt-bindings/clock/audio-ext-clk.h index c9a8286d7c7f..a384ddf68ea0 100644 --- a/include/dt-bindings/clock/audio-ext-clk.h +++ b/include/dt-bindings/clock/audio-ext-clk.h @@ -14,19 +14,17 @@ #define __AUDIO_EXT_CLK_H /* Audio External Clocks */ -#ifdef CONFIG_COMMON_CLK_QCOM #define AUDIO_PMI_CLK 0 #define AUDIO_PMIC_LNBB_CLK 1 #define AUDIO_AP_CLK 2 #define AUDIO_AP_CLK2 3 #define AUDIO_LPASS_MCLK 4 #define AUDIO_LPASS_MCLK2 5 -#else + #define clk_audio_ap_clk 0x9b5727cb #define clk_audio_pmi_clk 0xcbfe416d #define clk_audio_ap_clk2 0x454d1e91 #define clk_audio_lpass_mclk 0xf0f2a284 #define clk_audio_pmi_lnbb_clk 0x57312343 -#endif #endif From e5b3bf88ce6f03193474605e753676d3986e5bd3 Mon Sep 17 00:00:00 2001 From: Vijayavardhan Vennapusa Date: Thu, 8 Dec 2016 12:04:18 +0530 Subject: [PATCH 47/51] defconfig: msmfalcon: Enable audiosource gadget driver Enable required audiosource driver that is required for audio over accessory dock to work. Change-Id: Ifeb779a3323c505d482eb53ad96a1b8aec0f3af5 Signed-off-by: Vijayavardhan Vennapusa --- arch/arm/configs/msmfalcon-perf_defconfig | 1 + arch/arm/configs/msmfalcon_defconfig | 1 + arch/arm64/configs/msmfalcon-perf_defconfig | 1 + arch/arm64/configs/msmfalcon_defconfig | 1 + 4 files changed, 4 insertions(+) diff --git a/arch/arm/configs/msmfalcon-perf_defconfig b/arch/arm/configs/msmfalcon-perf_defconfig index 86a9ac168d0e..3425f32fc00f 100644 --- a/arch/arm/configs/msmfalcon-perf_defconfig +++ b/arch/arm/configs/msmfalcon-perf_defconfig @@ -417,6 +417,7 @@ CONFIG_USB_CONFIGFS_F_FS=y CONFIG_USB_CONFIGFS_F_MTP=y CONFIG_USB_CONFIGFS_F_PTP=y CONFIG_USB_CONFIGFS_F_ACC=y +CONFIG_USB_CONFIGFS_F_AUDIO_SRC=y CONFIG_USB_CONFIGFS_UEVENT=y CONFIG_USB_CONFIGFS_F_MIDI=y CONFIG_USB_CONFIGFS_F_HID=y diff --git a/arch/arm/configs/msmfalcon_defconfig b/arch/arm/configs/msmfalcon_defconfig index b53d1bfec33e..c730d8825cef 100644 --- a/arch/arm/configs/msmfalcon_defconfig +++ b/arch/arm/configs/msmfalcon_defconfig @@ -418,6 +418,7 @@ CONFIG_USB_CONFIGFS_F_FS=y CONFIG_USB_CONFIGFS_F_MTP=y CONFIG_USB_CONFIGFS_F_PTP=y CONFIG_USB_CONFIGFS_F_ACC=y +CONFIG_USB_CONFIGFS_F_AUDIO_SRC=y CONFIG_USB_CONFIGFS_UEVENT=y CONFIG_USB_CONFIGFS_F_MIDI=y CONFIG_USB_CONFIGFS_F_HID=y diff --git a/arch/arm64/configs/msmfalcon-perf_defconfig b/arch/arm64/configs/msmfalcon-perf_defconfig index 148cb523cbc9..8d692ea09932 100644 --- a/arch/arm64/configs/msmfalcon-perf_defconfig +++ b/arch/arm64/configs/msmfalcon-perf_defconfig @@ -446,6 +446,7 @@ CONFIG_USB_CONFIGFS_F_FS=y CONFIG_USB_CONFIGFS_F_MTP=y CONFIG_USB_CONFIGFS_F_PTP=y CONFIG_USB_CONFIGFS_F_ACC=y +CONFIG_USB_CONFIGFS_F_AUDIO_SRC=y CONFIG_USB_CONFIGFS_UEVENT=y CONFIG_USB_CONFIGFS_F_MIDI=y CONFIG_USB_CONFIGFS_F_HID=y diff --git a/arch/arm64/configs/msmfalcon_defconfig b/arch/arm64/configs/msmfalcon_defconfig index 26ad84e5ecca..13c1231c8fa2 100644 --- a/arch/arm64/configs/msmfalcon_defconfig +++ b/arch/arm64/configs/msmfalcon_defconfig @@ -447,6 +447,7 @@ CONFIG_USB_CONFIGFS_F_FS=y CONFIG_USB_CONFIGFS_F_MTP=y CONFIG_USB_CONFIGFS_F_PTP=y CONFIG_USB_CONFIGFS_F_ACC=y +CONFIG_USB_CONFIGFS_F_AUDIO_SRC=y CONFIG_USB_CONFIGFS_UEVENT=y CONFIG_USB_CONFIGFS_F_MIDI=y CONFIG_USB_CONFIGFS_F_HID=y From cb5b41659be0551677f77ccfce7aa4a21049d5db Mon Sep 17 00:00:00 2001 From: Shankar Ravi Date: Wed, 7 Dec 2016 10:18:01 +0530 Subject: [PATCH 48/51] ARM: dts: msm: Update camera GPIO, VREG config for msmfalcon interposer 1. Update PMIC gpio configuration for front and rear camera. 2. Correct VANA GPIO. 3. Correct the CSID VREG Voting. Change-Id: I1e72bf8855ea1150eb2cedaee82d04610b09bdae Signed-off-by: Shankar Ravi --- .../msm8998-interposer-camera-sensor-cdp.dtsi | 124 +++++++++++++----- .../msm8998-interposer-camera-sensor-mtp.dtsi | 124 +++++++++++++----- 2 files changed, 180 insertions(+), 68 deletions(-) diff --git a/arch/arm/boot/dts/qcom/msm8998-interposer-camera-sensor-cdp.dtsi b/arch/arm/boot/dts/qcom/msm8998-interposer-camera-sensor-cdp.dtsi index 0b8d84766fc4..1a7f759f4b63 100644 --- a/arch/arm/boot/dts/qcom/msm8998-interposer-camera-sensor-cdp.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-interposer-camera-sensor-cdp.dtsi @@ -12,6 +12,36 @@ */ &soc { + tlmm: pinctrl@03400000 { + cam_sensor_rear_active: cam_sensor_rear_active { + /* RESET, STANDBY */ + mux { + pins = "gpio30", "gpio8"; + function = "gpio"; + }; + + config { + pins = "gpio30", "gpio8"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_suspend: cam_sensor_rear_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio30", "gpio8"; + function = "gpio"; + }; + + config { + pins = "gpio30", "gpio8"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + }; + led_flash0: qcom,camera-flash@0 { cell-index = <0>; compatible = "qcom,camera-flash"; @@ -46,50 +76,74 @@ }; qcom,csid@ca30000 { - qcom,csi-vdd-voltage = <1225000>; + qcom,csi-vdd-voltage = <1200000>; qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>; gdscr-supply = <&gdsc_camss_top>; vdd_sec-supply = <&pm2falcon_l1>; bimc_smmu-supply = <&gdsc_bimc_smmu>; qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; + qcom,cam-vreg-min-voltage = <925000 0 0>; + qcom,cam-vreg-max-voltage = <925000 0 0>; + qcom,cam-vreg-op-mode = <0 0 0>; qcom,clock-rates = <0 0 0 0 0 0 0 384000000 384000000 0 0 0 0 0>; }; qcom,csid@ca30400 { - qcom,csi-vdd-voltage = <1225000>; + qcom,csi-vdd-voltage = <1200000>; qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>; gdscr-supply = <&gdsc_camss_top>; vdd_sec-supply = <&pm2falcon_l1>; bimc_smmu-supply = <&gdsc_bimc_smmu>; qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; + qcom,cam-vreg-min-voltage = <925000 0 0>; + qcom,cam-vreg-max-voltage = <925000 0 0>; + qcom,cam-vreg-op-mode = <0 0 0>; qcom,clock-rates = <0 0 0 0 0 0 0 384000000 384000000 0 0 0 0 0>; }; qcom,csid@ca30800 { - qcom,csi-vdd-voltage = <1225000>; + qcom,csi-vdd-voltage = <1200000>; qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>; gdscr-supply = <&gdsc_camss_top>; vdd_sec-supply = <&pm2falcon_l1>; bimc_smmu-supply = <&gdsc_bimc_smmu>; qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; + qcom,cam-vreg-min-voltage = <925000 0 0>; + qcom,cam-vreg-max-voltage = <925000 0 0>; + qcom,cam-vreg-op-mode = <0 0 0>; qcom,clock-rates = <0 0 0 0 0 0 0 384000000 384000000 0 0 0 0 0>; }; qcom,csid@ca30c00 { - qcom,csi-vdd-voltage = <1225000>; + qcom,csi-vdd-voltage = <1200000>; qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>; gdscr-supply = <&gdsc_camss_top>; vdd_sec-supply = <&pm2falcon_l1>; bimc_smmu-supply = <&gdsc_bimc_smmu>; qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; + qcom,cam-vreg-min-voltage = <925000 0 0>; + qcom,cam-vreg-max-voltage = <925000 0 0>; + qcom,cam-vreg-op-mode = <0 0 0>; qcom,clock-rates = <0 0 0 0 0 0 0 384000000 384000000 0 0 0 0 0>; }; }; +&cci { + /delete-node/qcom,camera@0; + /delete-node/qcom,camera@1; + /delete-node/qcom,camera@2; + /delete-node/qcom,eeprom@0; + /delete-node/qcom,eeprom@1; + /delete-node/qcom,eeprom@2; + /delete-node/qcom,actuator@0; + /delete-node/qcom,actuator@1; + /delete-node/qcom,ois@0; +}; + &cci { actuator0: qcom,actuator@0 { cell-index = <0>; @@ -145,9 +199,9 @@ cam_vana-supply = <&pm2falcon_bob>; cam_vdig-supply = <&pmfalcon_s5>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; - qcom,cam-vreg-min-voltage = <0 3300000 1350000>; - qcom,cam-vreg-max-voltage = <0 3600000 1350000>; - qcom,cam-vreg-op-mode = <0 80000 105000>; + qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; + qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; + qcom,cam-vreg-op-mode = <105000 80000 105000>; qcom,gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; pinctrl-0 = <&cam_sensor_mclk0_active @@ -158,8 +212,8 @@ &cam_actuator_vaf_suspend>; gpios = <&tlmm 13 0>, <&tlmm 30 0>, - <&pmfalcon_gpios 4 0>, - <&tlmm 29 0>, + <&pm2falcon_gpios 4 0>, + <&tlmm 8 0>, <&tlmm 27 0>; qcom,gpio-reset = <1>; qcom,gpio-vdig = <2>; @@ -190,28 +244,33 @@ cam_vana-supply = <&pm2falcon_bob>; cam_vdig-supply = <&pmfalcon_s5>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; - qcom,cam-vreg-min-voltage = <0 3300000 1350000>; - qcom,cam-vreg-max-voltage = <0 3600000 1350000>; - qcom,cam-vreg-op-mode = <0 80000 105000>; + qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; + qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; + qcom,cam-vreg-op-mode = <105000 80000 105000>; qcom,gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; pinctrl-0 = <&cam_sensor_mclk1_active - &cam_sensor_front_active>; + &cam_sensor_front_active + &cam_actuator_vaf_active>; pinctrl-1 = <&cam_sensor_mclk1_suspend - &cam_sensor_front_suspend>; + &cam_sensor_front_suspend + &cam_actuator_vaf_suspend>; gpios = <&tlmm 14 0>, <&tlmm 28 0>, <&pmfalcon_gpios 3 0>, - <&tlmm 29 0>; + <&tlmm 29 0>, + <&tlmm 27 0>; qcom,gpio-reset = <1>; qcom,gpio-vdig = <2>; qcom,gpio-vana = <3>; - qcom,gpio-req-tbl-num = <0 1 2 3>; - qcom,gpio-req-tbl-flags = <1 0 0 0>; + qcom,gpio-vaf = <4>; + qcom,gpio-req-tbl-num = <0 1 2 3 4>; + qcom,gpio-req-tbl-flags = <1 0 0 0 0>; qcom,gpio-req-tbl-label = "CAMIF_MCLK2", "CAM_RESET2", "CAM_VDIG", - "CAM_VANA"; + "CAM_VANA", + "CAM_VAF"; qcom,sensor-position = <1>; qcom,sensor-mode = <0>; qcom,cci-master = <1>; @@ -229,7 +288,6 @@ qcom,csiphy-sd-index = <0>; qcom,csid-sd-index = <0>; qcom,mount-angle = <270>; - qcom,led-flash-src = <&led_flash0>; qcom,actuator-src = <&actuator0>; qcom,ois-src = <&ois0>; qcom,eeprom-src = <&eeprom0>; @@ -237,9 +295,9 @@ cam_vana-supply = <&pm2falcon_bob>; cam_vdig-supply = <&pmfalcon_s5>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; - qcom,cam-vreg-min-voltage = <0 3300000 1350000>; - qcom,cam-vreg-max-voltage = <0 3600000 1350000>; - qcom,cam-vreg-op-mode = <0 80000 105000>; + qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; + qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; + qcom,cam-vreg-op-mode = <105000 80000 105000>; qcom,gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; pinctrl-0 = <&cam_sensor_mclk0_active @@ -248,8 +306,8 @@ &cam_sensor_rear_suspend>; gpios = <&tlmm 13 0>, <&tlmm 30 0>, - <&pmfalcon_gpios 4 0>, - <&tlmm 29 0>; + <&pm2falcon_gpios 4 0>, + <&tlmm 8 0>; qcom,gpio-reset = <1>; qcom,gpio-vdig = <2>; qcom,gpio-vana = <3>; @@ -276,16 +334,15 @@ qcom,csiphy-sd-index = <2>; qcom,csid-sd-index = <2>; qcom,mount-angle = <90>; - qcom,led-flash-src = <&led_flash1>; - qcom,eeprom-src = <&eeprom2>; qcom,actuator-src = <&actuator1>; + qcom,eeprom-src = <&eeprom2>; cam_vio-supply = <&pmfalcon_l11>; cam_vana-supply = <&pm2falcon_bob>; cam_vdig-supply = <&pmfalcon_s5>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; - qcom,cam-vreg-min-voltage = <0 3300000 1350000>; - qcom,cam-vreg-max-voltage = <0 3600000 1350000>; - qcom,cam-vreg-op-mode = <0 80000 105000>; + qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; + qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; + qcom,cam-vreg-op-mode = <105000 80000 105000>; qcom,gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; pinctrl-0 = <&cam_sensor_mclk1_active @@ -294,8 +351,8 @@ &cam_sensor_front_suspend>; gpios = <&tlmm 14 0>, <&tlmm 28 0>, - <&pmfalcon_gpios 3 0>, - <&tlmm 29 0>; + <&pm2falcon_gpios 3 0>, + <&tlmm 8 0>; qcom,gpio-reset = <1>; qcom,gpio-vdig = <2>; qcom,gpio-vana = <3>; @@ -316,8 +373,7 @@ }; }; - -&pmfalcon_gpios { +&pm2falcon_gpios { gpio@c300 { /* GPIO4 -CAMERA SENSOR 0 VDIG*/ qcom,mode = <1>; /* Output */ qcom,pull = <5>; /* No Pull */ @@ -328,7 +384,7 @@ status = "ok"; }; - gpio@c200 { /* GPIO3 -CAMERA SENSOR 1 VDIG*/ + gpio@c200 { /* GPIO3 -CAMERA SENSOR 2 VDIG*/ qcom,mode = <1>; /* Output */ qcom,pull = <5>; /* No Pull */ qcom,vin-sel = <0>; /* VIN1 GPIO_LV */ diff --git a/arch/arm/boot/dts/qcom/msm8998-interposer-camera-sensor-mtp.dtsi b/arch/arm/boot/dts/qcom/msm8998-interposer-camera-sensor-mtp.dtsi index 0b8d84766fc4..1a7f759f4b63 100644 --- a/arch/arm/boot/dts/qcom/msm8998-interposer-camera-sensor-mtp.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-interposer-camera-sensor-mtp.dtsi @@ -12,6 +12,36 @@ */ &soc { + tlmm: pinctrl@03400000 { + cam_sensor_rear_active: cam_sensor_rear_active { + /* RESET, STANDBY */ + mux { + pins = "gpio30", "gpio8"; + function = "gpio"; + }; + + config { + pins = "gpio30", "gpio8"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_suspend: cam_sensor_rear_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio30", "gpio8"; + function = "gpio"; + }; + + config { + pins = "gpio30", "gpio8"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + }; + led_flash0: qcom,camera-flash@0 { cell-index = <0>; compatible = "qcom,camera-flash"; @@ -46,50 +76,74 @@ }; qcom,csid@ca30000 { - qcom,csi-vdd-voltage = <1225000>; + qcom,csi-vdd-voltage = <1200000>; qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>; gdscr-supply = <&gdsc_camss_top>; vdd_sec-supply = <&pm2falcon_l1>; bimc_smmu-supply = <&gdsc_bimc_smmu>; qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; + qcom,cam-vreg-min-voltage = <925000 0 0>; + qcom,cam-vreg-max-voltage = <925000 0 0>; + qcom,cam-vreg-op-mode = <0 0 0>; qcom,clock-rates = <0 0 0 0 0 0 0 384000000 384000000 0 0 0 0 0>; }; qcom,csid@ca30400 { - qcom,csi-vdd-voltage = <1225000>; + qcom,csi-vdd-voltage = <1200000>; qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>; gdscr-supply = <&gdsc_camss_top>; vdd_sec-supply = <&pm2falcon_l1>; bimc_smmu-supply = <&gdsc_bimc_smmu>; qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; + qcom,cam-vreg-min-voltage = <925000 0 0>; + qcom,cam-vreg-max-voltage = <925000 0 0>; + qcom,cam-vreg-op-mode = <0 0 0>; qcom,clock-rates = <0 0 0 0 0 0 0 384000000 384000000 0 0 0 0 0>; }; qcom,csid@ca30800 { - qcom,csi-vdd-voltage = <1225000>; + qcom,csi-vdd-voltage = <1200000>; qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>; gdscr-supply = <&gdsc_camss_top>; vdd_sec-supply = <&pm2falcon_l1>; bimc_smmu-supply = <&gdsc_bimc_smmu>; qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; + qcom,cam-vreg-min-voltage = <925000 0 0>; + qcom,cam-vreg-max-voltage = <925000 0 0>; + qcom,cam-vreg-op-mode = <0 0 0>; qcom,clock-rates = <0 0 0 0 0 0 0 384000000 384000000 0 0 0 0 0>; }; qcom,csid@ca30c00 { - qcom,csi-vdd-voltage = <1225000>; + qcom,csi-vdd-voltage = <1200000>; qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>; gdscr-supply = <&gdsc_camss_top>; vdd_sec-supply = <&pm2falcon_l1>; bimc_smmu-supply = <&gdsc_bimc_smmu>; qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; + qcom,cam-vreg-min-voltage = <925000 0 0>; + qcom,cam-vreg-max-voltage = <925000 0 0>; + qcom,cam-vreg-op-mode = <0 0 0>; qcom,clock-rates = <0 0 0 0 0 0 0 384000000 384000000 0 0 0 0 0>; }; }; +&cci { + /delete-node/qcom,camera@0; + /delete-node/qcom,camera@1; + /delete-node/qcom,camera@2; + /delete-node/qcom,eeprom@0; + /delete-node/qcom,eeprom@1; + /delete-node/qcom,eeprom@2; + /delete-node/qcom,actuator@0; + /delete-node/qcom,actuator@1; + /delete-node/qcom,ois@0; +}; + &cci { actuator0: qcom,actuator@0 { cell-index = <0>; @@ -145,9 +199,9 @@ cam_vana-supply = <&pm2falcon_bob>; cam_vdig-supply = <&pmfalcon_s5>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; - qcom,cam-vreg-min-voltage = <0 3300000 1350000>; - qcom,cam-vreg-max-voltage = <0 3600000 1350000>; - qcom,cam-vreg-op-mode = <0 80000 105000>; + qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; + qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; + qcom,cam-vreg-op-mode = <105000 80000 105000>; qcom,gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; pinctrl-0 = <&cam_sensor_mclk0_active @@ -158,8 +212,8 @@ &cam_actuator_vaf_suspend>; gpios = <&tlmm 13 0>, <&tlmm 30 0>, - <&pmfalcon_gpios 4 0>, - <&tlmm 29 0>, + <&pm2falcon_gpios 4 0>, + <&tlmm 8 0>, <&tlmm 27 0>; qcom,gpio-reset = <1>; qcom,gpio-vdig = <2>; @@ -190,28 +244,33 @@ cam_vana-supply = <&pm2falcon_bob>; cam_vdig-supply = <&pmfalcon_s5>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; - qcom,cam-vreg-min-voltage = <0 3300000 1350000>; - qcom,cam-vreg-max-voltage = <0 3600000 1350000>; - qcom,cam-vreg-op-mode = <0 80000 105000>; + qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; + qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; + qcom,cam-vreg-op-mode = <105000 80000 105000>; qcom,gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; pinctrl-0 = <&cam_sensor_mclk1_active - &cam_sensor_front_active>; + &cam_sensor_front_active + &cam_actuator_vaf_active>; pinctrl-1 = <&cam_sensor_mclk1_suspend - &cam_sensor_front_suspend>; + &cam_sensor_front_suspend + &cam_actuator_vaf_suspend>; gpios = <&tlmm 14 0>, <&tlmm 28 0>, <&pmfalcon_gpios 3 0>, - <&tlmm 29 0>; + <&tlmm 29 0>, + <&tlmm 27 0>; qcom,gpio-reset = <1>; qcom,gpio-vdig = <2>; qcom,gpio-vana = <3>; - qcom,gpio-req-tbl-num = <0 1 2 3>; - qcom,gpio-req-tbl-flags = <1 0 0 0>; + qcom,gpio-vaf = <4>; + qcom,gpio-req-tbl-num = <0 1 2 3 4>; + qcom,gpio-req-tbl-flags = <1 0 0 0 0>; qcom,gpio-req-tbl-label = "CAMIF_MCLK2", "CAM_RESET2", "CAM_VDIG", - "CAM_VANA"; + "CAM_VANA", + "CAM_VAF"; qcom,sensor-position = <1>; qcom,sensor-mode = <0>; qcom,cci-master = <1>; @@ -229,7 +288,6 @@ qcom,csiphy-sd-index = <0>; qcom,csid-sd-index = <0>; qcom,mount-angle = <270>; - qcom,led-flash-src = <&led_flash0>; qcom,actuator-src = <&actuator0>; qcom,ois-src = <&ois0>; qcom,eeprom-src = <&eeprom0>; @@ -237,9 +295,9 @@ cam_vana-supply = <&pm2falcon_bob>; cam_vdig-supply = <&pmfalcon_s5>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; - qcom,cam-vreg-min-voltage = <0 3300000 1350000>; - qcom,cam-vreg-max-voltage = <0 3600000 1350000>; - qcom,cam-vreg-op-mode = <0 80000 105000>; + qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; + qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; + qcom,cam-vreg-op-mode = <105000 80000 105000>; qcom,gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; pinctrl-0 = <&cam_sensor_mclk0_active @@ -248,8 +306,8 @@ &cam_sensor_rear_suspend>; gpios = <&tlmm 13 0>, <&tlmm 30 0>, - <&pmfalcon_gpios 4 0>, - <&tlmm 29 0>; + <&pm2falcon_gpios 4 0>, + <&tlmm 8 0>; qcom,gpio-reset = <1>; qcom,gpio-vdig = <2>; qcom,gpio-vana = <3>; @@ -276,16 +334,15 @@ qcom,csiphy-sd-index = <2>; qcom,csid-sd-index = <2>; qcom,mount-angle = <90>; - qcom,led-flash-src = <&led_flash1>; - qcom,eeprom-src = <&eeprom2>; qcom,actuator-src = <&actuator1>; + qcom,eeprom-src = <&eeprom2>; cam_vio-supply = <&pmfalcon_l11>; cam_vana-supply = <&pm2falcon_bob>; cam_vdig-supply = <&pmfalcon_s5>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; - qcom,cam-vreg-min-voltage = <0 3300000 1350000>; - qcom,cam-vreg-max-voltage = <0 3600000 1350000>; - qcom,cam-vreg-op-mode = <0 80000 105000>; + qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; + qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; + qcom,cam-vreg-op-mode = <105000 80000 105000>; qcom,gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; pinctrl-0 = <&cam_sensor_mclk1_active @@ -294,8 +351,8 @@ &cam_sensor_front_suspend>; gpios = <&tlmm 14 0>, <&tlmm 28 0>, - <&pmfalcon_gpios 3 0>, - <&tlmm 29 0>; + <&pm2falcon_gpios 3 0>, + <&tlmm 8 0>; qcom,gpio-reset = <1>; qcom,gpio-vdig = <2>; qcom,gpio-vana = <3>; @@ -316,8 +373,7 @@ }; }; - -&pmfalcon_gpios { +&pm2falcon_gpios { gpio@c300 { /* GPIO4 -CAMERA SENSOR 0 VDIG*/ qcom,mode = <1>; /* Output */ qcom,pull = <5>; /* No Pull */ @@ -328,7 +384,7 @@ status = "ok"; }; - gpio@c200 { /* GPIO3 -CAMERA SENSOR 1 VDIG*/ + gpio@c200 { /* GPIO3 -CAMERA SENSOR 2 VDIG*/ qcom,mode = <1>; /* Output */ qcom,pull = <5>; /* No Pull */ qcom,vin-sel = <0>; /* VIN1 GPIO_LV */ From 355786d15d3ba8d897354c75a57b7194e2aae6e9 Mon Sep 17 00:00:00 2001 From: Siddhartha Agrawal Date: Wed, 7 Dec 2016 15:40:38 -0800 Subject: [PATCH 49/51] msm: mdss: dp: correctly ref count the pll resources This fixes the issue where the dp pll resource was not correctly keeping a refcount on the pll resource. This will fix the bootup warning when both DSI and DP are enabled. Crs-Fixed: 1088737 Change-Id: I19f8eef7f664a58cac1a082b8195e48c52613c5d Signed-off-by: Siddhartha Agrawal --- drivers/clk/msm/mdss/mdss-dp-pll-8998-util.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/msm/mdss/mdss-dp-pll-8998-util.c b/drivers/clk/msm/mdss/mdss-dp-pll-8998-util.c index c13ff563c8bf..0bd7e6413a6b 100644 --- a/drivers/clk/msm/mdss/mdss-dp-pll-8998-util.c +++ b/drivers/clk/msm/mdss/mdss-dp-pll-8998-util.c @@ -836,8 +836,8 @@ enum handoff dp_vco_handoff(struct clk *c) io->handoff_resources = true; ret = HANDOFF_ENABLED_CLK; } else { - io->handoff_resources = false; mdss_pll_resource_enable(io, false); + ret = HANDOFF_DISABLED_CLK; DEV_DBG("%s: PLL not locked\n", __func__); } From a8c976f55a027707d49753be3cdc83802f7a0a0e Mon Sep 17 00:00:00 2001 From: Hemant Kumar Date: Thu, 1 Dec 2016 19:56:10 -0800 Subject: [PATCH 50/51] usb: phy: qusb2: Add support to vote for regulator L2a L2a is required to lock the phy PLL upon bus resume when exiting from XO shutdown. This LDO powers REFGEN block which is required to be powered on so that phy PLL gets locked as part of wakeup from XO shutdown. Change-Id: Ia0e3d574de7c78534832e4f8749672eb6fcde1f0 Signed-off-by: Hemant Kumar --- .../devicetree/bindings/usb/msm-phy.txt | 1 + arch/arm/boot/dts/qcom/msm8998.dtsi | 1 + drivers/usb/phy/phy-msm-qusb-v2.c | 47 ++++++++++++++++++- 3 files changed, 48 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/usb/msm-phy.txt b/Documentation/devicetree/bindings/usb/msm-phy.txt index b45ee910258e..032f07535415 100644 --- a/Documentation/devicetree/bindings/usb/msm-phy.txt +++ b/Documentation/devicetree/bindings/usb/msm-phy.txt @@ -178,6 +178,7 @@ Required properties: "vdd" : vdd supply for digital circuit operation "vdda18" : 1.8v high-voltage analog supply "vdda33" : 3.3v high-voltage analog supply + "vdda12" : 1.2v high-voltage analog supply - qcom,vdd-voltage-level: This property must be a list of three integer values (no, min, max) where each value represents either a voltage in microvolts or a value corresponding to voltage corner diff --git a/arch/arm/boot/dts/qcom/msm8998.dtsi b/arch/arm/boot/dts/qcom/msm8998.dtsi index 0b54647fedfb..c265eafcdd30 100644 --- a/arch/arm/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998.dtsi @@ -1762,6 +1762,7 @@ reg-names = "qusb_phy_base", "tcsr_clamp_dig_n_1p8"; vdd-supply = <&pm8998_l1>; + vdda12-supply = <&pm8998_l2>; vdda18-supply = <&pm8998_l12>; vdda33-supply = <&pm8998_l24>; qcom,vdd-voltage-level = <0 880000 880000>; diff --git a/drivers/usb/phy/phy-msm-qusb-v2.c b/drivers/usb/phy/phy-msm-qusb-v2.c index 5a768ee4d061..86908d2ce9d5 100644 --- a/drivers/usb/phy/phy-msm-qusb-v2.c +++ b/drivers/usb/phy/phy-msm-qusb-v2.c @@ -51,6 +51,10 @@ #define QUSB2PHY_PORT_TUNE1 0x23c +#define QUSB2PHY_1P2_VOL_MIN 1200000 /* uV */ +#define QUSB2PHY_1P2_VOL_MAX 1200000 /* uV */ +#define QUSB2PHY_1P2_HPM_LOAD 23000 + #define QUSB2PHY_1P8_VOL_MIN 1800000 /* uV */ #define QUSB2PHY_1P8_VOL_MAX 1800000 /* uV */ #define QUSB2PHY_1P8_HPM_LOAD 30000 /* uA */ @@ -83,6 +87,7 @@ struct qusb_phy { struct regulator *vdd; struct regulator *vdda33; struct regulator *vdda18; + struct regulator *vdda12; int vdd_levels[3]; /* none, low, high */ int init_seq_len; int *qusb_phy_init_seq; @@ -184,10 +189,30 @@ static int qusb_phy_enable_power(struct qusb_phy *qphy, bool on, } } + ret = regulator_set_load(qphy->vdda12, QUSB2PHY_1P2_HPM_LOAD); + if (ret < 0) { + dev_err(qphy->phy.dev, "Unable to set HPM of vdda12:%d\n", ret); + goto disable_vdd; + } + + ret = regulator_set_voltage(qphy->vdda12, QUSB2PHY_1P2_VOL_MIN, + QUSB2PHY_1P2_VOL_MAX); + if (ret) { + dev_err(qphy->phy.dev, + "Unable to set voltage for vdda12:%d\n", ret); + goto put_vdda12_lpm; + } + + ret = regulator_enable(qphy->vdda12); + if (ret) { + dev_err(qphy->phy.dev, "Unable to enable vdda12:%d\n", ret); + goto unset_vdda12; + } + ret = regulator_set_load(qphy->vdda18, QUSB2PHY_1P8_HPM_LOAD); if (ret < 0) { dev_err(qphy->phy.dev, "Unable to set HPM of vdda18:%d\n", ret); - goto disable_vdd; + goto disable_vdda12; } ret = regulator_set_voltage(qphy->vdda18, QUSB2PHY_1P8_VOL_MIN, @@ -262,6 +287,20 @@ put_vdda18_lpm: if (ret < 0) dev_err(qphy->phy.dev, "Unable to set LPM of vdda18\n"); +disable_vdda12: + ret = regulator_disable(qphy->vdda12); + if (ret) + dev_err(qphy->phy.dev, "Unable to disable vdda12:%d\n", ret); +unset_vdda12: + ret = regulator_set_voltage(qphy->vdda12, 0, QUSB2PHY_1P2_VOL_MAX); + if (ret) + dev_err(qphy->phy.dev, + "Unable to set (0) voltage for vdda12:%d\n", ret); +put_vdda12_lpm: + ret = regulator_set_load(qphy->vdda12, 0); + if (ret < 0) + dev_err(qphy->phy.dev, "Unable to set LPM of vdda12\n"); + disable_vdd: if (toggle_vdd) { ret = regulator_disable(qphy->vdd); @@ -985,6 +1024,12 @@ static int qusb_phy_probe(struct platform_device *pdev) return PTR_ERR(qphy->vdda18); } + qphy->vdda12 = devm_regulator_get(dev, "vdda12"); + if (IS_ERR(qphy->vdda12)) { + dev_err(dev, "unable to get vdda12 supply\n"); + return PTR_ERR(qphy->vdda12); + } + platform_set_drvdata(pdev, qphy); qphy->phy.label = "msm-qusb-phy-v2"; From 149c51d5f2b7b2028446e3757ff6b17e90092c48 Mon Sep 17 00:00:00 2001 From: Patrick Daly Date: Thu, 27 Oct 2016 18:08:01 -0700 Subject: [PATCH 51/51] iommu: arm-smmu: Fix clock reference count error When an atomic iommu domain attaches, an additional vote for both clk_prepare, bus_bw, and regulator_enable must be held. The prior logic only did this if the atomic domain was the first to attach to the iommu. Fix this. As a side effect, add reference counting for bus_bandwidth voting such that a call to arm_smmu_enable_clock() followed by arm_smmu_disable_clocks() will not always result in a bus bandwidth vote of zero. Change-Id: I7f88ea845a281c8c1def4f642e61262b53b60e1a Signed-off-by: Patrick Daly --- drivers/iommu/arm-smmu.c | 73 +++++++++++++++++++++++++++++++--------- 1 file changed, 58 insertions(+), 15 deletions(-) diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index eac6d07e6097..791f2fe70236 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -407,6 +407,9 @@ struct arm_smmu_device { unsigned int clock_refs_count; spinlock_t clock_refs_lock; + struct mutex power_lock; + unsigned int power_count; + struct msm_bus_client_handle *bus_client; char *bus_client_name; @@ -919,17 +922,43 @@ static int arm_smmu_unrequest_bus(struct arm_smmu_device *smmu) static int arm_smmu_disable_regulators(struct arm_smmu_device *smmu) { + int ret = 0; + + mutex_lock(&smmu->power_lock); + if (smmu->power_count == 0) { + WARN(1, "%s: Mismatched power count\n", dev_name(smmu->dev)); + mutex_unlock(&smmu->power_lock); + return -EINVAL; + } else if (smmu->power_count > 1) { + smmu->power_count -= 1; + mutex_unlock(&smmu->power_lock); + return 0; + } + arm_smmu_unprepare_clocks(smmu); arm_smmu_unrequest_bus(smmu); - if (!smmu->gdsc) - return 0; - return regulator_disable(smmu->gdsc); + if (smmu->gdsc) { + ret = regulator_disable(smmu->gdsc); + WARN(ret, "%s: Regulator disable failed\n", + dev_name(smmu->dev)); + } + + smmu->power_count = 0; + mutex_unlock(&smmu->power_lock); + return ret; } static int arm_smmu_enable_regulators(struct arm_smmu_device *smmu) { int ret; + mutex_lock(&smmu->power_lock); + if (smmu->power_count) { + smmu->power_count++; + mutex_unlock(&smmu->power_lock); + return 0; + } + if (smmu->gdsc) { ret = regulator_enable(smmu->gdsc); if (WARN_ON_ONCE(ret)) @@ -944,6 +973,8 @@ static int arm_smmu_enable_regulators(struct arm_smmu_device *smmu) if (WARN_ON_ONCE(ret)) goto out_bus; + smmu->power_count = 1; + mutex_unlock(&smmu->power_lock); return ret; out_bus: @@ -952,6 +983,7 @@ out_reg: if (smmu->gdsc) regulator_disable(smmu->gdsc); out: + mutex_unlock(&smmu->power_lock); return ret; } @@ -2217,8 +2249,7 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) * refcounting) is that we never disable regulators while a * client is attached in these cases. */ - if (!(smmu->options & ARM_SMMU_OPT_REGISTER_SAVE) || - atomic_ctx) { + if (!(smmu->options & ARM_SMMU_OPT_REGISTER_SAVE)) { ret = arm_smmu_enable_regulators(smmu); if (ret) goto err_unlock; @@ -2235,12 +2266,18 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) } smmu->attach_count++; + if (atomic_ctx) { + ret = arm_smmu_enable_regulators(smmu); + if (ret) + goto err_disable_clocks; + } + if (arm_smmu_is_static_cb(smmu)) { ret = arm_smmu_populate_cb(smmu, smmu_domain, dev); if (ret) { dev_err(dev, "Failed to get valid context bank\n"); - goto err_disable_clocks; + goto err_atomic_ctx; } smmu_domain->slave_side_secure = true; } @@ -2248,13 +2285,13 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) cfg = find_smmu_master_cfg(dev); if (!cfg) { ret = -ENODEV; - goto err_disable_clocks; + goto err_atomic_ctx; } /* Ensure that the domain is finalised */ ret = arm_smmu_init_domain_context(domain, smmu, cfg); if (IS_ERR_VALUE(ret)) - goto err_disable_clocks; + goto err_atomic_ctx; /* * Sanity check the domain. We don't support domains across @@ -2280,12 +2317,15 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) err_destroy_domain_context: arm_smmu_destroy_domain_context(domain); +err_atomic_ctx: + if (atomic_ctx) + arm_smmu_disable_regulators(smmu); err_disable_clocks: arm_smmu_disable_clocks(smmu); --smmu->attach_count; err_disable_regulators: if (!smmu->attach_count && - (!(smmu->options & ARM_SMMU_OPT_REGISTER_SAVE) || atomic_ctx)) + (!(smmu->options & ARM_SMMU_OPT_REGISTER_SAVE))) arm_smmu_disable_regulators(smmu); err_unlock: mutex_unlock(&smmu->attach_lock); @@ -2293,8 +2333,7 @@ err_unlock: return ret; } -static void arm_smmu_power_off(struct arm_smmu_device *smmu, - bool force_regulator_disable) +static void arm_smmu_power_off(struct arm_smmu_device *smmu) { /* Turn the thing off */ if (arm_smmu_enable_clocks(smmu)) @@ -2302,8 +2341,7 @@ static void arm_smmu_power_off(struct arm_smmu_device *smmu, writel_relaxed(sCR0_CLIENTPD, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0); arm_smmu_disable_clocks(smmu); - if (!(smmu->options & ARM_SMMU_OPT_REGISTER_SAVE) - || force_regulator_disable) + if (!(smmu->options & ARM_SMMU_OPT_REGISTER_SAVE)) arm_smmu_disable_regulators(smmu); } @@ -2345,6 +2383,8 @@ static void arm_smmu_detach_dev(struct iommu_domain *domain, struct device *dev) if (smmu_domain->attributes & (1 << DOMAIN_ATTR_DYNAMIC)) { arm_smmu_detach_dynamic(domain, smmu); mutex_unlock(&smmu_domain->init_mutex); + if (atomic_ctx) + arm_smmu_disable_regulators(smmu); return; } @@ -2358,7 +2398,9 @@ static void arm_smmu_detach_dev(struct iommu_domain *domain, struct device *dev) arm_smmu_domain_remove_master(smmu_domain, cfg); arm_smmu_destroy_domain_context(domain); if (!--smmu->attach_count) - arm_smmu_power_off(smmu, atomic_ctx); + arm_smmu_power_off(smmu); + if (atomic_ctx) + arm_smmu_disable_regulators(smmu); unlock: mutex_unlock(&smmu->attach_lock); mutex_unlock(&smmu_domain->init_mutex); @@ -3789,6 +3831,7 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev) } smmu->dev = dev; mutex_init(&smmu->attach_lock); + mutex_init(&smmu->power_lock); spin_lock_init(&smmu->atos_lock); spin_lock_init(&smmu->clock_refs_lock); INIT_LIST_HEAD(&smmu->static_cbndx_list); @@ -3970,7 +4013,7 @@ static int arm_smmu_device_remove(struct platform_device *pdev) * still powered on. Power off now. */ if (smmu->attach_count) - arm_smmu_power_off(smmu, false); + arm_smmu_power_off(smmu); mutex_unlock(&smmu->attach_lock); msm_bus_scale_unregister(smmu->bus_client);