From 99cc2192132ab28c495d015ed2e95dc29e2a27ad Mon Sep 17 00:00:00 2001 From: Frank van Maarseveen <frankvm@frankvm.com> Date: Fri, 9 Sep 2005 13:01:46 -0700 Subject: [PATCH] [PATCH] ppc32: Correct an instruction in the boot code In the flush and invalidate bootcode on PPC4xx we were accidentally using the wrong instruction. Use cmplw, which reads from a register like we want. Signed-off-by: Tom Rini <trini@kernel.crashing.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org> --- arch/ppc/boot/common/util.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/ppc/boot/common/util.S b/arch/ppc/boot/common/util.S index 47e641455bc5..c96c9f80521e 100644 --- a/arch/ppc/boot/common/util.S +++ b/arch/ppc/boot/common/util.S @@ -252,7 +252,7 @@ _GLOBAL(flush_instruction_cache) 1: dcbf r0,r3 # Flush the data cache icbi r0,r3 # Invalidate the instruction cache addi r3,r3,0x10 # Increment by one cache line - cmplwi cr0,r3,r4 # Are we at the end yet? + cmplw cr0,r3,r4 # Are we at the end yet? blt 1b # No, keep flushing and invalidating #else /* Enable, invalidate and then disable the L1 icache/dcache. */