leds: qpnp-wled: Update AMOLED_VOUT programming
For newer PMICs like pmicobalt, AMOLED_VOUT can be programmed via independent registers. Also the option to configure AVDD voltage through SWIRE and SPMI mode is present. Add support to program the AVDD voltage and mode through these registers. AVDD TRIM adjustment is needed only for pmi8952 and pmi8994. It is not needed for pmicobalt. Support it. CRs-Fixed: 1051250 Change-Id: Ia5cc4a6bbf6b6d0d86e13cec7da167f8a49b859d Signed-off-by: Devesh Jhunjhunwala <deveshj@codeaurora.org> Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
This commit is contained in:
Subbaraman Narayanamurthy
parent
7a1b6d0276
commit
9b32ac8b25
2 changed files with 123 additions and 45 deletions
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@ -61,10 +61,13 @@ Optional properties if 'qcom,disp-type-amoled' is mentioned in DT:
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- qcom,loop-ea-gm : control the gm for gm stage in control loop. default is 3.
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- qcom,loop-comp-res-kohm : control to select the compensation resistor in kohm. default is 320.
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- qcom,vref-psm-mv : reference psm voltage in mv. default for amoled is 450.
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- qcom,avdd-target-voltage-mv: The target voltage desired for the AVDD module in mV.
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The supported values are:
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7900, 7600, 7300, 6400, 6100, 5800.
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If not specified, default value used is 7600.
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- qcom,avdd-mode-spmi: Boolean property to enable AMOLED_VOUT programming via SPMI. If not specified,
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AMOLED_VOUT is programmed via S-wire. This can be specified only for newer
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PMICs like pmicobalt/pm2falcon.
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- qcom,avdd-target-voltage-mv: The voltage required for AMOLED_VOUT. Accepted values are in the range
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of 5650 to 7900 in steps of 150. Default value is 7600. Unit is in mV.
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For old revisions, accepted values are: 7900, 7600, 7300, 6400, 6100,
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5800.
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Example:
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qcom,leds@d800 {
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@ -45,11 +45,13 @@
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#define QPNP_WLED_SWITCH_FREQ_REG(b) (b + 0x4C)
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#define QPNP_WLED_OVP_REG(b) (b + 0x4D)
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#define QPNP_WLED_ILIM_REG(b) (b + 0x4E)
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#define QPNP_WLED_AMOLED_VOUT_REG(b) (b + 0x4F)
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#define QPNP_WLED_SOFTSTART_RAMP_DLY(b) (b + 0x53)
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#define QPNP_WLED_VLOOP_COMP_RES_REG(b) (b + 0x55)
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#define QPNP_WLED_VLOOP_COMP_GM_REG(b) (b + 0x56)
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#define QPNP_WLED_PSM_CTRL_REG(b) (b + 0x5B)
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#define QPNP_WLED_SC_PRO_REG(b) (b + 0x5E)
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#define QPNP_WLED_SWIRE_AVDD_REG(b) (b + 0x5F)
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#define QPNP_WLED_CTRL_SPARE_REG(b) (b + 0xDF)
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#define QPNP_WLED_TEST1_REG(b) (b + 0xE2)
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#define QPNP_WLED_TEST4_REG(b) (b + 0xE5)
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@ -196,12 +198,19 @@
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#define NUM_SUPPORTED_AVDD_VOLTAGES 6
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#define QPNP_WLED_DFLT_AVDD_MV 7600
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#define QPNP_WLED_AVDD_MIN_MV 5650
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#define QPNP_WLED_AVDD_MAX_MV 7900
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#define QPNP_WLED_AVDD_STEP_MV 150
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#define QPNP_WLED_AVDD_MIN_TRIM_VAL 0x0
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#define QPNP_WLED_AVDD_MAX_TRIM_VAL 0xF
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#define QPNP_WLED_AVDD_SEL_SPMI_BIT BIT(7)
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#define QPNP_WLED_AVDD_SET_BIT BIT(4)
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#define NUM_SUPPORTED_OVP_THRESHOLDS 4
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#define QPNP_WLED_AVDD_MV_TO_REG(val) \
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((val - QPNP_WLED_AVDD_MIN_MV) / QPNP_WLED_AVDD_STEP_MV)
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/* output feedback mode */
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enum qpnp_wled_fdbk_op {
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QPNP_WLED_FDBK_AUTO,
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@ -288,6 +297,7 @@ static int qpnp_wled_ovp_thresholds_pmicobalt[NUM_SUPPORTED_OVP_THRESHOLDS] = {
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* @ cons_sync_write_delay_us - delay between two consecutive writes to SYNC
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* @ strings - supported list of strings
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* @ num_strings - number of strings
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* @ avdd_mode_spmi - enable avdd programming via spmi
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* @ en_9b_dim_res - enable or disable 9bit dimming
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* @ en_phase_stag - enable or disable phase staggering
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* @ en_cabc - enable or disable cabc
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@ -330,6 +340,7 @@ struct qpnp_wled {
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u16 cons_sync_write_delay_us;
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u8 strings[QPNP_WLED_MAX_STRINGS];
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u8 num_strings;
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bool avdd_mode_spmi;
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bool en_9b_dim_res;
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bool en_phase_stag;
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bool en_cabc;
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@ -1089,6 +1100,102 @@ static int qpnp_wled_ovp_config(struct qpnp_wled *wled)
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return 0;
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}
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static int qpnp_wled_avdd_trim_config(struct qpnp_wled *wled)
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{
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int rc, i;
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u8 reg;
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for (i = 0; i < NUM_SUPPORTED_AVDD_VOLTAGES; i++) {
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if (wled->avdd_target_voltage_mv ==
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qpnp_wled_avdd_target_voltages[i])
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break;
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}
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if (i == NUM_SUPPORTED_AVDD_VOLTAGES) {
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dev_err(&wled->pdev->dev,
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"Invalid avdd target voltage specified in device tree\n");
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return -EINVAL;
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}
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/* Update WLED_OVP register based on desired target voltage */
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reg = qpnp_wled_ovp_reg_settings[i];
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rc = qpnp_wled_masked_write_reg(wled, QPNP_WLED_OVP_MASK, ®,
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QPNP_WLED_OVP_REG(wled->ctrl_base));
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if (rc)
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return rc;
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/* Update WLED_TRIM register based on desired target voltage */
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rc = qpnp_wled_read_reg(wled, ®,
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QPNP_WLED_REF_7P7_TRIM_REG(wled->ctrl_base));
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if (rc)
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return rc;
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reg += qpnp_wled_avdd_trim_adjustments[i];
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if ((s8)reg < QPNP_WLED_AVDD_MIN_TRIM_VAL ||
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(s8)reg > QPNP_WLED_AVDD_MAX_TRIM_VAL) {
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dev_dbg(&wled->pdev->dev,
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"adjusted trim %d is not within range, capping it\n",
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(s8)reg);
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if ((s8)reg < QPNP_WLED_AVDD_MIN_TRIM_VAL)
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reg = QPNP_WLED_AVDD_MIN_TRIM_VAL;
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else
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reg = QPNP_WLED_AVDD_MAX_TRIM_VAL;
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}
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reg &= QPNP_WLED_7P7_TRIM_MASK;
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rc = qpnp_wled_sec_write_reg(wled, reg,
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QPNP_WLED_REF_7P7_TRIM_REG(wled->ctrl_base));
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if (rc < 0)
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dev_err(&wled->pdev->dev, "Write to 7P7_TRIM register failed, rc=%d\n",
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rc);
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return rc;
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}
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static int qpnp_wled_avdd_mode_config(struct qpnp_wled *wled)
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{
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int rc;
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u8 reg = 0;
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/*
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* At present, configuring the mode to SPMI/SWIRE for controlling
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* AVDD voltage is available only in pmicobalt/pm2falcon.
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*/
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if (wled->pmic_rev_id->pmic_subtype != PMICOBALT_SUBTYPE &&
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wled->pmic_rev_id->pmic_subtype != PM2FALCON_SUBTYPE)
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return 0;
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/* AMOLED_VOUT should be configured for AMOLED */
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if (!wled->disp_type_amoled)
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return 0;
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/* Configure avdd register */
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if (wled->avdd_target_voltage_mv > QPNP_WLED_AVDD_MAX_MV) {
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dev_dbg(&wled->pdev->dev, "Capping avdd target voltage to %d\n",
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QPNP_WLED_AVDD_MAX_MV);
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wled->avdd_target_voltage_mv = QPNP_WLED_AVDD_MAX_MV;
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} else if (wled->avdd_target_voltage_mv < QPNP_WLED_AVDD_MIN_MV) {
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dev_info(&wled->pdev->dev, "Capping avdd target voltage to %d\n",
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QPNP_WLED_AVDD_MIN_MV);
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wled->avdd_target_voltage_mv = QPNP_WLED_AVDD_MIN_MV;
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}
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reg = QPNP_WLED_AVDD_MV_TO_REG(wled->avdd_target_voltage_mv);
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if (wled->avdd_mode_spmi) {
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reg |= QPNP_WLED_AVDD_SEL_SPMI_BIT;
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rc = qpnp_wled_write_reg(wled, reg,
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QPNP_WLED_AMOLED_VOUT_REG(wled->ctrl_base));
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} else {
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rc = qpnp_wled_write_reg(wled, reg,
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QPNP_WLED_SWIRE_AVDD_REG(wled->ctrl_base));
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}
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if (rc < 0)
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dev_err(&wled->pdev->dev, "Write to VOUT/AVDD register failed, rc=%d\n",
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rc);
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return rc;
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}
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/* Configure WLED registers */
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static int qpnp_wled_config(struct qpnp_wled *wled)
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{
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@ -1199,50 +1306,15 @@ static int qpnp_wled_config(struct qpnp_wled *wled)
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}
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if (is_avdd_trim_adjustment_required(wled)) {
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for (i = 0; i < NUM_SUPPORTED_AVDD_VOLTAGES; i++) {
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if (wled->avdd_target_voltage_mv ==
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qpnp_wled_avdd_target_voltages[i])
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break;
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}
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if (i == NUM_SUPPORTED_AVDD_VOLTAGES) {
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dev_err(&wled->pdev->dev,
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"Invalid avdd target voltage specified in device tree\n");
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return -EINVAL;
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}
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/* Update WLED_OVP register based on desired target voltage */
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reg = qpnp_wled_ovp_reg_settings[i];
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rc = qpnp_wled_masked_write_reg(wled, QPNP_WLED_OVP_MASK, ®,
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QPNP_WLED_OVP_REG(wled->ctrl_base));
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if (rc)
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return rc;
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/* Update WLED_TRIM register based on desired target voltage */
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rc = qpnp_wled_read_reg(wled, ®,
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QPNP_WLED_REF_7P7_TRIM_REG(wled->ctrl_base));
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if (rc)
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return rc;
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reg += qpnp_wled_avdd_trim_adjustments[i];
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if ((s8)reg < QPNP_WLED_AVDD_MIN_TRIM_VAL ||
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(s8)reg > QPNP_WLED_AVDD_MAX_TRIM_VAL) {
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dev_info(&wled->pdev->dev,
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"adjusted trim %d is not within range, capping it\n",
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(s8)reg);
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if ((s8)reg < QPNP_WLED_AVDD_MIN_TRIM_VAL)
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reg = QPNP_WLED_AVDD_MIN_TRIM_VAL;
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else
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reg = QPNP_WLED_AVDD_MAX_TRIM_VAL;
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}
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reg &= QPNP_WLED_7P7_TRIM_MASK;
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rc = qpnp_wled_sec_write_reg(wled, reg,
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QPNP_WLED_REF_7P7_TRIM_REG(wled->ctrl_base));
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if (rc)
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rc = qpnp_wled_avdd_trim_config(wled);
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if (rc < 0)
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return rc;
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}
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rc = qpnp_wled_avdd_mode_config(wled);
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if (rc < 0)
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return rc;
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/* Configure the MODULATION register */
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if (wled->mod_freq_khz <= QPNP_WLED_MOD_FREQ_1200_KHZ) {
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wled->mod_freq_khz = QPNP_WLED_MOD_FREQ_1200_KHZ;
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@ -1561,6 +1633,9 @@ static int qpnp_wled_parse_dt(struct qpnp_wled *wled)
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return rc;
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}
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wled->avdd_mode_spmi = of_property_read_bool(pdev->dev.of_node,
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"qcom,avdd-mode-spmi");
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wled->avdd_target_voltage_mv = QPNP_WLED_DFLT_AVDD_MV;
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rc = of_property_read_u32(pdev->dev.of_node,
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"qcom,avdd-target-voltage-mv", &temp_val);
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