From 936388f5f57d0f3c420db08140fa087d49da440c Mon Sep 17 00:00:00 2001 From: Vikram Mulukutla Date: Mon, 11 Jan 2016 11:54:04 -0800 Subject: [PATCH 1/2] clk: msm: clock-alpha-pll: Allow interrupts to be enabled during set_rate Some PLL implementations depend on the CPU being able to handle certain interrupts in order for the set_rate operation to complete. Allow interrupts to be handled in the set_rate op. CRs-Fixed: 960701 Change-Id: I6fda5ed9eb7d6f2e2cd91c58ebabfd7bc1c8a2fc Signed-off-by: Vikram Mulukutla --- drivers/clk/msm/clock-alpha-pll.c | 11 +++++++++-- include/soc/qcom/clock-alpha-pll.h | 1 + 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/clk/msm/clock-alpha-pll.c b/drivers/clk/msm/clock-alpha-pll.c index b9a1167a790d..834315aa4993 100644 --- a/drivers/clk/msm/clock-alpha-pll.c +++ b/drivers/clk/msm/clock-alpha-pll.c @@ -612,13 +612,17 @@ static int alpha_pll_set_rate(struct clk *c, unsigned long rate) return -EINVAL; } + if (pll->no_irq_dis) + spin_lock(&c->lock); + else + spin_lock_irqsave(&c->lock, flags); + /* * For PLLs that do not support dynamic programming (dynamic_update * is not set), ensure PLL is off before changing rate. For * optimization reasons, assume no downstream clock is actively * using it. */ - spin_lock_irqsave(&c->lock, flags); if (c->count && !pll->dynamic_update) c->ops->disable(c); @@ -644,7 +648,10 @@ static int alpha_pll_set_rate(struct clk *c, unsigned long rate) if (c->count && !pll->dynamic_update) c->ops->enable(c); - spin_unlock_irqrestore(&c->lock, flags); + if (pll->no_irq_dis) + spin_unlock(&c->lock); + else + spin_unlock_irqrestore(&c->lock, flags); return 0; } diff --git a/include/soc/qcom/clock-alpha-pll.h b/include/soc/qcom/clock-alpha-pll.h index 0b5329ba817c..acffe33dc4f3 100644 --- a/include/soc/qcom/clock-alpha-pll.h +++ b/include/soc/qcom/clock-alpha-pll.h @@ -79,6 +79,7 @@ struct alpha_pll_clk { * that the workaround is required. */ bool offline_bit_workaround; + bool no_irq_dis; bool is_fabia; unsigned long min_supported_freq; struct clk c; From 767c721b7c77b76ca4e49129dabeabd332bbdda7 Mon Sep 17 00:00:00 2001 From: Vikram Mulukutla Date: Mon, 11 Jan 2016 11:56:27 -0800 Subject: [PATCH 2/2] clk: msm: clock-cpu-8996: Allow interrupts during alt_pll set_rate The CPU that is disabling the alternate PLL may also need to handle CPR interrupts. Allow the CPU to handle interrupts during the set_rate operation. CRs-Fixed: 960701 Change-Id: I63d7ce3e3dd2b559c4db383b64faa9335c404576 Signed-off-by: Vikram Mulukutla --- drivers/clk/msm/clock-cpu-8996.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/msm/clock-cpu-8996.c b/drivers/clk/msm/clock-cpu-8996.c index 7e03a599fccc..bcda6f31d6f5 100644 --- a/drivers/clk/msm/clock-cpu-8996.c +++ b/drivers/clk/msm/clock-cpu-8996.c @@ -238,6 +238,7 @@ static struct alpha_pll_clk perfcl_alt_pll = { .post_div_config = 0x100, /* Div-2 */ .config_ctl_val = 0x4001051B, .offline_bit_workaround = true, + .no_irq_dis = true, .c = { .always_on = true, .parent = &alpha_xo_ao.c, @@ -300,6 +301,7 @@ static struct alpha_pll_clk pwrcl_alt_pll = { .post_div_config = 0x100, /* Div-2 */ .config_ctl_val = 0x4001051B, .offline_bit_workaround = true, + .no_irq_dis = true, .c = { .always_on = true, .dbg_name = "pwrcl_alt_pll",