OMAP4: hwmod data: Add McSPI
Update omap4 hwmod file with McSPI info. Signed-off-by: Benoit Cousson <b-cousson@ti.com> Signed-off-by: Charulatha V <charu@ti.com> Signed-off-by: Govindraj.R <govindraj.raja@ti.com> Acked-by: Grant Likely <grant.likely@secretlab.ca> Reviewed-by: Kevin Hilman <khilman@ti.com>
This commit is contained in:
Benoit Cousson
parent
d11c217f1a
commit
9bcbd7f0d5
1 changed files with 245 additions and 4 deletions
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@ -534,10 +534,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
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* mcbsp3
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* mcbsp3
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* mcbsp4
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* mcbsp4
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* mcpdm
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* mcpdm
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* mcspi1
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* mcspi2
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* mcspi3
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* mcspi4
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* mmc1
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* mmc1
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* mmc2
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* mmc2
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* mmc3
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* mmc3
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@ -1433,6 +1429,245 @@ static struct omap_hwmod omap44xx_iva_hwmod = {
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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};
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/*
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* 'mcspi' class
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* multichannel serial port interface (mcspi) / master/slave synchronous serial
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* bus
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*/
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static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
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.rev_offs = 0x0000,
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.sysc_offs = 0x0010,
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.sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
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SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
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SIDLE_SMART_WKUP),
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.sysc_fields = &omap_hwmod_sysc_type2,
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};
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static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
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.name = "mcspi",
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.sysc = &omap44xx_mcspi_sysc,
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};
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/* mcspi1 */
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static struct omap_hwmod omap44xx_mcspi1_hwmod;
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static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
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{ .irq = 65 + OMAP44XX_IRQ_GIC_START },
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};
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static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
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{ .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
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{ .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
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{ .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
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{ .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
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{ .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
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{ .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
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{ .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
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{ .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
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};
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static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
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{
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.pa_start = 0x48098000,
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.pa_end = 0x480981ff,
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.flags = ADDR_TYPE_RT
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},
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};
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/* l4_per -> mcspi1 */
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static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
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.master = &omap44xx_l4_per_hwmod,
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.slave = &omap44xx_mcspi1_hwmod,
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.clk = "l4_div_ck",
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.addr = omap44xx_mcspi1_addrs,
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.addr_cnt = ARRAY_SIZE(omap44xx_mcspi1_addrs),
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* mcspi1 slave ports */
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static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = {
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&omap44xx_l4_per__mcspi1,
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};
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static struct omap_hwmod omap44xx_mcspi1_hwmod = {
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.name = "mcspi1",
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.class = &omap44xx_mcspi_hwmod_class,
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.mpu_irqs = omap44xx_mcspi1_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi1_irqs),
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.sdma_reqs = omap44xx_mcspi1_sdma_reqs,
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.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi1_sdma_reqs),
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.main_clk = "mcspi1_fck",
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.prcm = {
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.omap4 = {
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.clkctrl_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
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},
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},
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.slaves = omap44xx_mcspi1_slaves,
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.slaves_cnt = ARRAY_SIZE(omap44xx_mcspi1_slaves),
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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/* mcspi2 */
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static struct omap_hwmod omap44xx_mcspi2_hwmod;
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static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
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{ .irq = 66 + OMAP44XX_IRQ_GIC_START },
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};
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static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
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{ .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
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{ .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
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{ .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
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{ .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
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};
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static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
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{
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.pa_start = 0x4809a000,
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.pa_end = 0x4809a1ff,
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.flags = ADDR_TYPE_RT
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},
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};
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/* l4_per -> mcspi2 */
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static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
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.master = &omap44xx_l4_per_hwmod,
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.slave = &omap44xx_mcspi2_hwmod,
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.clk = "l4_div_ck",
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.addr = omap44xx_mcspi2_addrs,
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.addr_cnt = ARRAY_SIZE(omap44xx_mcspi2_addrs),
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* mcspi2 slave ports */
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static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = {
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&omap44xx_l4_per__mcspi2,
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};
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static struct omap_hwmod omap44xx_mcspi2_hwmod = {
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.name = "mcspi2",
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.class = &omap44xx_mcspi_hwmod_class,
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.mpu_irqs = omap44xx_mcspi2_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi2_irqs),
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.sdma_reqs = omap44xx_mcspi2_sdma_reqs,
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.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi2_sdma_reqs),
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.main_clk = "mcspi2_fck",
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.prcm = {
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.omap4 = {
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.clkctrl_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
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},
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},
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.slaves = omap44xx_mcspi2_slaves,
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.slaves_cnt = ARRAY_SIZE(omap44xx_mcspi2_slaves),
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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/* mcspi3 */
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static struct omap_hwmod omap44xx_mcspi3_hwmod;
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static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
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{ .irq = 91 + OMAP44XX_IRQ_GIC_START },
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};
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static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
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{ .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
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{ .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
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{ .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
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{ .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
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};
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static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
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{
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.pa_start = 0x480b8000,
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.pa_end = 0x480b81ff,
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.flags = ADDR_TYPE_RT
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},
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};
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/* l4_per -> mcspi3 */
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static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
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.master = &omap44xx_l4_per_hwmod,
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.slave = &omap44xx_mcspi3_hwmod,
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.clk = "l4_div_ck",
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.addr = omap44xx_mcspi3_addrs,
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.addr_cnt = ARRAY_SIZE(omap44xx_mcspi3_addrs),
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* mcspi3 slave ports */
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static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = {
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&omap44xx_l4_per__mcspi3,
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};
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static struct omap_hwmod omap44xx_mcspi3_hwmod = {
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.name = "mcspi3",
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.class = &omap44xx_mcspi_hwmod_class,
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.mpu_irqs = omap44xx_mcspi3_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi3_irqs),
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.sdma_reqs = omap44xx_mcspi3_sdma_reqs,
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.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi3_sdma_reqs),
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.main_clk = "mcspi3_fck",
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.prcm = {
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.omap4 = {
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.clkctrl_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
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},
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},
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.slaves = omap44xx_mcspi3_slaves,
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.slaves_cnt = ARRAY_SIZE(omap44xx_mcspi3_slaves),
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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/* mcspi4 */
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static struct omap_hwmod omap44xx_mcspi4_hwmod;
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static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
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{ .irq = 48 + OMAP44XX_IRQ_GIC_START },
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};
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static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
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{ .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
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{ .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
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};
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static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
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{
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.pa_start = 0x480ba000,
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.pa_end = 0x480ba1ff,
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.flags = ADDR_TYPE_RT
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},
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};
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/* l4_per -> mcspi4 */
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static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
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.master = &omap44xx_l4_per_hwmod,
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.slave = &omap44xx_mcspi4_hwmod,
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.clk = "l4_div_ck",
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.addr = omap44xx_mcspi4_addrs,
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.addr_cnt = ARRAY_SIZE(omap44xx_mcspi4_addrs),
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* mcspi4 slave ports */
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static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = {
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&omap44xx_l4_per__mcspi4,
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};
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static struct omap_hwmod omap44xx_mcspi4_hwmod = {
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.name = "mcspi4",
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.class = &omap44xx_mcspi_hwmod_class,
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.mpu_irqs = omap44xx_mcspi4_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi4_irqs),
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.sdma_reqs = omap44xx_mcspi4_sdma_reqs,
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.sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi4_sdma_reqs),
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.main_clk = "mcspi4_fck",
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.prcm = {
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.omap4 = {
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.clkctrl_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
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},
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},
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.slaves = omap44xx_mcspi4_slaves,
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.slaves_cnt = ARRAY_SIZE(omap44xx_mcspi4_slaves),
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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/*
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/*
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* 'mpu' class
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* 'mpu' class
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* mpu sub-system
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* mpu sub-system
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@ -2110,6 +2345,12 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
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&omap44xx_iva_seq0_hwmod,
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&omap44xx_iva_seq0_hwmod,
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&omap44xx_iva_seq1_hwmod,
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&omap44xx_iva_seq1_hwmod,
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/* mcspi class */
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&omap44xx_mcspi1_hwmod,
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&omap44xx_mcspi2_hwmod,
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&omap44xx_mcspi3_hwmod,
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&omap44xx_mcspi4_hwmod,
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/* mpu class */
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/* mpu class */
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&omap44xx_mpu_hwmod,
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&omap44xx_mpu_hwmod,
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