ASoC: wcd9335: Adjust DMIC clock based on sample rate
Currently DMIC clock is set at 4.8MHz for all sampling rates. For optimal power, sampling rates <=48KHz should be set to 2.4MHz. CRs-fixed: 971183 Change-Id: If3076f017d476cfb57fa22b75cc74ed615c8882e Signed-off-by: Stephen Oglesby <soglesby@codeaurora.org> Signed-off-by: Phani Kumar Uppalapati <phaniu@codeaurora.org>
This commit is contained in:
Stephen Oglesby
Kyle Yan
parent
f47eab663e
commit
9fca33dfb6
1 changed files with 69 additions and 14 deletions
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@ -5429,6 +5429,67 @@ out:
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return ret;
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return ret;
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}
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}
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static void tasha_set_anc_dmic_mode(struct snd_soc_codec *codec,
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u8 dmic_ctl_val)
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{
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u8 anc_ctl_value;
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if (dmic_ctl_val == WCD9335_DMIC_CLK_DIV_2)
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anc_ctl_value = WCD9335_ANC_DMIC_X2_FULL_RATE;
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else
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anc_ctl_value = WCD9335_ANC_DMIC_X2_HALF_RATE;
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snd_soc_update_bits(codec, WCD9335_CDC_ANC0_MODE_2_CTL,
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0x40, anc_ctl_value << 6);
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snd_soc_update_bits(codec, WCD9335_CDC_ANC0_MODE_2_CTL,
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0x20, anc_ctl_value << 5);
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snd_soc_update_bits(codec, WCD9335_CDC_ANC1_MODE_2_CTL,
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0x40, anc_ctl_value << 6);
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snd_soc_update_bits(codec, WCD9335_CDC_ANC1_MODE_2_CTL,
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0x20, anc_ctl_value << 5);
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}
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static u32 tasha_get_dmic_sample_rate(struct snd_soc_codec *codec,
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unsigned int dmic, struct wcd9xxx_pdata *pdata)
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{
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u8 tx_stream_fs;
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u8 adc_mux_index = 0, adc_mux_sel = 0;
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bool dec_found = false;
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u16 adc_mux_ctl_reg, tx_fs_reg;
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u32 dmic_fs;
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while (dec_found == 0 && adc_mux_index < WCD9335_MAX_VALID_ADC_MUX) {
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if (adc_mux_index < 4) {
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adc_mux_ctl_reg = WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0 +
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(adc_mux_index * 2);
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adc_mux_sel = ((snd_soc_read(codec, adc_mux_ctl_reg) &
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0x78) >> 3) - 1;
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} else if (adc_mux_index < 9) {
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adc_mux_ctl_reg = WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
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((adc_mux_index - 4) * 1);
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adc_mux_sel = ((snd_soc_read(codec, adc_mux_ctl_reg) &
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0x38) >> 3) - 1;
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} else if (adc_mux_index == 9) {
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continue;
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}
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if (adc_mux_sel == dmic)
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dec_found = true;
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else
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++adc_mux_index;
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}
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if (dec_found == true && adc_mux_index <= 8) {
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tx_fs_reg = WCD9335_CDC_TX0_TX_PATH_CTL + (16 * adc_mux_index);
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tx_stream_fs = snd_soc_read(codec, tx_fs_reg) & 0x0F;
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dmic_fs = tx_stream_fs <= 4 ? WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ :
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WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ;
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} else {
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dmic_fs = pdata->dmic_sample_rate;
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}
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return dmic_fs;
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}
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static u8 tasha_get_dmic_clk_val(struct snd_soc_codec *codec,
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static u8 tasha_get_dmic_clk_val(struct snd_soc_codec *codec,
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u32 mclk_rate, u32 dmic_clk_rate)
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u32 mclk_rate, u32 dmic_clk_rate)
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{
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{
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@ -5512,6 +5573,7 @@ static int tasha_codec_enable_dmic(struct snd_soc_dapm_widget *w,
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s32 *dmic_clk_cnt;
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s32 *dmic_clk_cnt;
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u8 dmic_rate_val, dmic_rate_shift = 1;
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u8 dmic_rate_val, dmic_rate_shift = 1;
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unsigned int dmic;
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unsigned int dmic;
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u32 dmic_sample_rate;
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int ret;
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int ret;
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char *wname;
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char *wname;
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@ -5554,10 +5616,15 @@ static int tasha_codec_enable_dmic(struct snd_soc_dapm_widget *w,
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switch (event) {
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switch (event) {
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case SND_SOC_DAPM_PRE_PMU:
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case SND_SOC_DAPM_PRE_PMU:
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dmic_sample_rate = tasha_get_dmic_sample_rate(codec, dmic,
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pdata);
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dmic_rate_val =
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dmic_rate_val =
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tasha_get_dmic_clk_val(codec,
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tasha_get_dmic_clk_val(codec,
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pdata->mclk_rate,
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pdata->mclk_rate,
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pdata->dmic_sample_rate);
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dmic_sample_rate);
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/* Set ANC dmic control bits to match dmic rate */
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tasha_set_anc_dmic_mode(codec, dmic_rate_val);
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(*dmic_clk_cnt)++;
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(*dmic_clk_cnt)++;
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if (*dmic_clk_cnt == 1) {
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if (*dmic_clk_cnt == 1) {
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@ -11910,7 +11977,6 @@ static int tasha_handle_pdata(struct tasha_priv *tasha,
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{
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{
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struct snd_soc_codec *codec = tasha->codec;
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struct snd_soc_codec *codec = tasha->codec;
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u8 dmic_ctl_val, mad_dmic_ctl_val;
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u8 dmic_ctl_val, mad_dmic_ctl_val;
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u8 anc_ctl_value;
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u32 def_dmic_rate, dmic_clk_drv;
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u32 def_dmic_rate, dmic_clk_drv;
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int vout_ctl_1, vout_ctl_2, vout_ctl_3, vout_ctl_4;
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int vout_ctl_1, vout_ctl_2, vout_ctl_3, vout_ctl_4;
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int rc = 0;
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int rc = 0;
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@ -12020,19 +12086,8 @@ static int tasha_handle_pdata(struct tasha_priv *tasha,
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pdata->mclk_rate,
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pdata->mclk_rate,
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pdata->dmic_sample_rate);
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pdata->dmic_sample_rate);
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if (dmic_ctl_val == WCD9335_DMIC_CLK_DIV_2)
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tasha_set_anc_dmic_mode(codec, dmic_ctl_val);
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anc_ctl_value = WCD9335_ANC_DMIC_X2_FULL_RATE;
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else
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anc_ctl_value = WCD9335_ANC_DMIC_X2_HALF_RATE;
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snd_soc_update_bits(codec, WCD9335_CDC_ANC0_MODE_2_CTL,
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0x40, anc_ctl_value << 6);
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snd_soc_update_bits(codec, WCD9335_CDC_ANC0_MODE_2_CTL,
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0x20, anc_ctl_value << 5);
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snd_soc_update_bits(codec, WCD9335_CDC_ANC1_MODE_2_CTL,
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0x40, anc_ctl_value << 6);
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snd_soc_update_bits(codec, WCD9335_CDC_ANC1_MODE_2_CTL,
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0x20, anc_ctl_value << 5);
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done:
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done:
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return rc;
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return rc;
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}
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}
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