Qualcomm ARM Based SoC Updates for v4.2-1
* Added Subsystem Power Manager (SPM) driver * Split out 32-bit specific SCM code * Added HDCP SCM call -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) Comment: GPGTools - https://gpgtools.org iQIcBAABCgAGBQJVZzj8AAoJEF9hYXeAcXzBg5kP/iP2uYhtSoU12RYD/vpm6hlF AwqcwDk08YMevwHpj992q802yMan4EfA9tliPm4AZw/iIRmWnp1PQHY9A2ghBAi6 6ofA6lv0gEP1QVZzy6NOxtTzROPYrAQhIirbfpPXtVvuVi4s251u1oNHmchb5emv BZfsao4DluAdRBhcFOcxXnwWLjEYSJMzzXrkQKL+xT5DKiRz7gV+BWqvgYoMgorY 1s59LW5uzOU18xLNgJXeRNNVS/gPy2pc6UkHQQr1LVLUWTXlcz9aZIjldwpEQSnm N50g2ZX4y4NvT3x88n956S4qSgWuAnQ717KVJ3rdkxXK30wSxmxWX9QqMqnLl7dc VG2znmWZTGv+3Mmd5vCm7P+vROY7K1B3EILUZRmTyJXjKjU3ukS5M0iUjS/qUg6e e8Py1d+AMJvbbv74l1K0ivgN1WZCAsCmVrGo62LuybRZQHXmYJCOMG+unSAlNIoq APvjbD2P8CMpxQChOt0GHBfUldZnn/Zr3pims5aVpKr9dMVnEGr7x/nLsf1QxceW aWiacSxhewEiz25vFBR2KuP/aTkWThXckhQEDclHSoT9ZsHtcBdyTk4sMfCTb2q0 JZnJ8k/fMu98E88f1PYsBPOvu9aFAyBuAhaKgrIFR1Az5ADk4E/bLtORPh5TMPqJ hcds9Zlf3stQHkl1ug7j =h0R2 -----END PGP SIGNATURE----- Merge tag 'qcom-soc-for-4.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom into next/drivers Merge "Qualcomm ARM Based SoC Updates for v4.2-1" from Kumar Gala: * Added Subsystem Power Manager (SPM) driver * Split out 32-bit specific SCM code * Added HDCP SCM call * tag 'qcom-soc-for-4.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom: firmware: qcom: scm: Add HDCP Support firmware: qcom: scm: Split out 32-bit specific SCM code ARM: qcom: Add Subsystem Power Manager (SPM) driver
This commit is contained in:
Arnd Bergmann
commit
9ff3d178ab
8 changed files with 995 additions and 438 deletions
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@ -12,7 +12,8 @@ obj-$(CONFIG_ISCSI_IBFT_FIND) += iscsi_ibft_find.o
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obj-$(CONFIG_ISCSI_IBFT) += iscsi_ibft.o
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obj-$(CONFIG_ISCSI_IBFT) += iscsi_ibft.o
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obj-$(CONFIG_FIRMWARE_MEMMAP) += memmap.o
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obj-$(CONFIG_FIRMWARE_MEMMAP) += memmap.o
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obj-$(CONFIG_QCOM_SCM) += qcom_scm.o
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obj-$(CONFIG_QCOM_SCM) += qcom_scm.o
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CFLAGS_qcom_scm.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)
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obj-$(CONFIG_QCOM_SCM) += qcom_scm-32.o
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CFLAGS_qcom_scm-32.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)
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obj-$(CONFIG_GOOGLE_FIRMWARE) += google/
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obj-$(CONFIG_GOOGLE_FIRMWARE) += google/
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obj-$(CONFIG_EFI) += efi/
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obj-$(CONFIG_EFI) += efi/
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503
drivers/firmware/qcom_scm-32.c
Normal file
503
drivers/firmware/qcom_scm-32.c
Normal file
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@ -0,0 +1,503 @@
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/* Copyright (c) 2010,2015, The Linux Foundation. All rights reserved.
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* Copyright (C) 2015 Linaro Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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* 02110-1301, USA.
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*/
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/qcom_scm.h>
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#include <asm/outercache.h>
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#include <asm/cacheflush.h>
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#include "qcom_scm.h"
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#define QCOM_SCM_FLAG_COLDBOOT_CPU0 0x00
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#define QCOM_SCM_FLAG_COLDBOOT_CPU1 0x01
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#define QCOM_SCM_FLAG_COLDBOOT_CPU2 0x08
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#define QCOM_SCM_FLAG_COLDBOOT_CPU3 0x20
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#define QCOM_SCM_FLAG_WARMBOOT_CPU0 0x04
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#define QCOM_SCM_FLAG_WARMBOOT_CPU1 0x02
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#define QCOM_SCM_FLAG_WARMBOOT_CPU2 0x10
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#define QCOM_SCM_FLAG_WARMBOOT_CPU3 0x40
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struct qcom_scm_entry {
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int flag;
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void *entry;
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};
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static struct qcom_scm_entry qcom_scm_wb[] = {
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{ .flag = QCOM_SCM_FLAG_WARMBOOT_CPU0 },
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{ .flag = QCOM_SCM_FLAG_WARMBOOT_CPU1 },
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{ .flag = QCOM_SCM_FLAG_WARMBOOT_CPU2 },
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{ .flag = QCOM_SCM_FLAG_WARMBOOT_CPU3 },
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};
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static DEFINE_MUTEX(qcom_scm_lock);
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/**
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* struct qcom_scm_command - one SCM command buffer
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* @len: total available memory for command and response
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* @buf_offset: start of command buffer
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* @resp_hdr_offset: start of response buffer
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* @id: command to be executed
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* @buf: buffer returned from qcom_scm_get_command_buffer()
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*
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* An SCM command is laid out in memory as follows:
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*
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* ------------------- <--- struct qcom_scm_command
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* | command header |
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* ------------------- <--- qcom_scm_get_command_buffer()
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* | command buffer |
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* ------------------- <--- struct qcom_scm_response and
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* | response header | qcom_scm_command_to_response()
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* ------------------- <--- qcom_scm_get_response_buffer()
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* | response buffer |
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* -------------------
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*
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* There can be arbitrary padding between the headers and buffers so
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* you should always use the appropriate qcom_scm_get_*_buffer() routines
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* to access the buffers in a safe manner.
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*/
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struct qcom_scm_command {
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__le32 len;
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__le32 buf_offset;
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__le32 resp_hdr_offset;
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__le32 id;
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__le32 buf[0];
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};
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/**
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* struct qcom_scm_response - one SCM response buffer
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* @len: total available memory for response
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* @buf_offset: start of response data relative to start of qcom_scm_response
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* @is_complete: indicates if the command has finished processing
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*/
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struct qcom_scm_response {
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__le32 len;
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__le32 buf_offset;
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__le32 is_complete;
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};
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/**
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* alloc_qcom_scm_command() - Allocate an SCM command
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* @cmd_size: size of the command buffer
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* @resp_size: size of the response buffer
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*
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* Allocate an SCM command, including enough room for the command
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* and response headers as well as the command and response buffers.
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*
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* Returns a valid &qcom_scm_command on success or %NULL if the allocation fails.
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*/
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static struct qcom_scm_command *alloc_qcom_scm_command(size_t cmd_size, size_t resp_size)
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{
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struct qcom_scm_command *cmd;
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size_t len = sizeof(*cmd) + sizeof(struct qcom_scm_response) + cmd_size +
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resp_size;
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u32 offset;
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cmd = kzalloc(PAGE_ALIGN(len), GFP_KERNEL);
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if (cmd) {
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cmd->len = cpu_to_le32(len);
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offset = offsetof(struct qcom_scm_command, buf);
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cmd->buf_offset = cpu_to_le32(offset);
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cmd->resp_hdr_offset = cpu_to_le32(offset + cmd_size);
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}
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return cmd;
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}
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/**
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* free_qcom_scm_command() - Free an SCM command
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* @cmd: command to free
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*
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* Free an SCM command.
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*/
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static inline void free_qcom_scm_command(struct qcom_scm_command *cmd)
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{
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kfree(cmd);
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}
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/**
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* qcom_scm_command_to_response() - Get a pointer to a qcom_scm_response
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* @cmd: command
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*
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* Returns a pointer to a response for a command.
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*/
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static inline struct qcom_scm_response *qcom_scm_command_to_response(
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const struct qcom_scm_command *cmd)
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{
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return (void *)cmd + le32_to_cpu(cmd->resp_hdr_offset);
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}
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/**
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* qcom_scm_get_command_buffer() - Get a pointer to a command buffer
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* @cmd: command
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*
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* Returns a pointer to the command buffer of a command.
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*/
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static inline void *qcom_scm_get_command_buffer(const struct qcom_scm_command *cmd)
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{
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return (void *)cmd->buf;
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}
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/**
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* qcom_scm_get_response_buffer() - Get a pointer to a response buffer
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* @rsp: response
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*
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* Returns a pointer to a response buffer of a response.
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*/
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static inline void *qcom_scm_get_response_buffer(const struct qcom_scm_response *rsp)
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{
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return (void *)rsp + le32_to_cpu(rsp->buf_offset);
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}
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static int qcom_scm_remap_error(int err)
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{
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pr_err("qcom_scm_call failed with error code %d\n", err);
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switch (err) {
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case QCOM_SCM_ERROR:
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return -EIO;
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case QCOM_SCM_EINVAL_ADDR:
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case QCOM_SCM_EINVAL_ARG:
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return -EINVAL;
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case QCOM_SCM_EOPNOTSUPP:
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return -EOPNOTSUPP;
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case QCOM_SCM_ENOMEM:
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return -ENOMEM;
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}
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return -EINVAL;
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}
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static u32 smc(u32 cmd_addr)
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{
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int context_id;
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register u32 r0 asm("r0") = 1;
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register u32 r1 asm("r1") = (u32)&context_id;
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register u32 r2 asm("r2") = cmd_addr;
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do {
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asm volatile(
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__asmeq("%0", "r0")
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__asmeq("%1", "r0")
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__asmeq("%2", "r1")
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__asmeq("%3", "r2")
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#ifdef REQUIRES_SEC
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".arch_extension sec\n"
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#endif
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"smc #0 @ switch to secure world\n"
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: "=r" (r0)
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: "r" (r0), "r" (r1), "r" (r2)
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: "r3");
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} while (r0 == QCOM_SCM_INTERRUPTED);
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return r0;
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}
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static int __qcom_scm_call(const struct qcom_scm_command *cmd)
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{
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int ret;
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u32 cmd_addr = virt_to_phys(cmd);
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/*
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* Flush the command buffer so that the secure world sees
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* the correct data.
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*/
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__cpuc_flush_dcache_area((void *)cmd, cmd->len);
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outer_flush_range(cmd_addr, cmd_addr + cmd->len);
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ret = smc(cmd_addr);
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if (ret < 0)
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ret = qcom_scm_remap_error(ret);
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return ret;
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}
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static void qcom_scm_inv_range(unsigned long start, unsigned long end)
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{
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u32 cacheline_size, ctr;
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asm volatile("mrc p15, 0, %0, c0, c0, 1" : "=r" (ctr));
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cacheline_size = 4 << ((ctr >> 16) & 0xf);
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start = round_down(start, cacheline_size);
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end = round_up(end, cacheline_size);
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outer_inv_range(start, end);
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while (start < end) {
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asm ("mcr p15, 0, %0, c7, c6, 1" : : "r" (start)
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: "memory");
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start += cacheline_size;
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}
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dsb();
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isb();
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}
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/**
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* qcom_scm_call() - Send an SCM command
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* @svc_id: service identifier
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* @cmd_id: command identifier
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* @cmd_buf: command buffer
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* @cmd_len: length of the command buffer
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* @resp_buf: response buffer
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* @resp_len: length of the response buffer
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*
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* Sends a command to the SCM and waits for the command to finish processing.
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*
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* A note on cache maintenance:
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* Note that any buffers that are expected to be accessed by the secure world
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* must be flushed before invoking qcom_scm_call and invalidated in the cache
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* immediately after qcom_scm_call returns. Cache maintenance on the command
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* and response buffers is taken care of by qcom_scm_call; however, callers are
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* responsible for any other cached buffers passed over to the secure world.
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*/
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static int qcom_scm_call(u32 svc_id, u32 cmd_id, const void *cmd_buf,
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size_t cmd_len, void *resp_buf, size_t resp_len)
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{
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int ret;
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struct qcom_scm_command *cmd;
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struct qcom_scm_response *rsp;
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unsigned long start, end;
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cmd = alloc_qcom_scm_command(cmd_len, resp_len);
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if (!cmd)
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return -ENOMEM;
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cmd->id = cpu_to_le32((svc_id << 10) | cmd_id);
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|
if (cmd_buf)
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memcpy(qcom_scm_get_command_buffer(cmd), cmd_buf, cmd_len);
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|
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mutex_lock(&qcom_scm_lock);
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|
ret = __qcom_scm_call(cmd);
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mutex_unlock(&qcom_scm_lock);
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|
if (ret)
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goto out;
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|
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rsp = qcom_scm_command_to_response(cmd);
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start = (unsigned long)rsp;
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|
do {
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qcom_scm_inv_range(start, start + sizeof(*rsp));
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|
} while (!rsp->is_complete);
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|
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end = (unsigned long)qcom_scm_get_response_buffer(rsp) + resp_len;
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qcom_scm_inv_range(start, end);
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if (resp_buf)
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memcpy(resp_buf, qcom_scm_get_response_buffer(rsp), resp_len);
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|
out:
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|
free_qcom_scm_command(cmd);
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|
return ret;
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|
}
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|
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#define SCM_CLASS_REGISTER (0x2 << 8)
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|
#define SCM_MASK_IRQS BIT(5)
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|
#define SCM_ATOMIC(svc, cmd, n) (((((svc) << 10)|((cmd) & 0x3ff)) << 12) | \
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SCM_CLASS_REGISTER | \
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|
SCM_MASK_IRQS | \
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|
(n & 0xf))
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|
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||||||
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/**
|
||||||
|
* qcom_scm_call_atomic1() - Send an atomic SCM command with one argument
|
||||||
|
* @svc_id: service identifier
|
||||||
|
* @cmd_id: command identifier
|
||||||
|
* @arg1: first argument
|
||||||
|
*
|
||||||
|
* This shall only be used with commands that are guaranteed to be
|
||||||
|
* uninterruptable, atomic and SMP safe.
|
||||||
|
*/
|
||||||
|
static s32 qcom_scm_call_atomic1(u32 svc, u32 cmd, u32 arg1)
|
||||||
|
{
|
||||||
|
int context_id;
|
||||||
|
|
||||||
|
register u32 r0 asm("r0") = SCM_ATOMIC(svc, cmd, 1);
|
||||||
|
register u32 r1 asm("r1") = (u32)&context_id;
|
||||||
|
register u32 r2 asm("r2") = arg1;
|
||||||
|
|
||||||
|
asm volatile(
|
||||||
|
__asmeq("%0", "r0")
|
||||||
|
__asmeq("%1", "r0")
|
||||||
|
__asmeq("%2", "r1")
|
||||||
|
__asmeq("%3", "r2")
|
||||||
|
#ifdef REQUIRES_SEC
|
||||||
|
".arch_extension sec\n"
|
||||||
|
#endif
|
||||||
|
"smc #0 @ switch to secure world\n"
|
||||||
|
: "=r" (r0)
|
||||||
|
: "r" (r0), "r" (r1), "r" (r2)
|
||||||
|
: "r3");
|
||||||
|
return r0;
|
||||||
|
}
|
||||||
|
|
||||||
|
u32 qcom_scm_get_version(void)
|
||||||
|
{
|
||||||
|
int context_id;
|
||||||
|
static u32 version = -1;
|
||||||
|
register u32 r0 asm("r0");
|
||||||
|
register u32 r1 asm("r1");
|
||||||
|
|
||||||
|
if (version != -1)
|
||||||
|
return version;
|
||||||
|
|
||||||
|
mutex_lock(&qcom_scm_lock);
|
||||||
|
|
||||||
|
r0 = 0x1 << 8;
|
||||||
|
r1 = (u32)&context_id;
|
||||||
|
do {
|
||||||
|
asm volatile(
|
||||||
|
__asmeq("%0", "r0")
|
||||||
|
__asmeq("%1", "r1")
|
||||||
|
__asmeq("%2", "r0")
|
||||||
|
__asmeq("%3", "r1")
|
||||||
|
#ifdef REQUIRES_SEC
|
||||||
|
".arch_extension sec\n"
|
||||||
|
#endif
|
||||||
|
"smc #0 @ switch to secure world\n"
|
||||||
|
: "=r" (r0), "=r" (r1)
|
||||||
|
: "r" (r0), "r" (r1)
|
||||||
|
: "r2", "r3");
|
||||||
|
} while (r0 == QCOM_SCM_INTERRUPTED);
|
||||||
|
|
||||||
|
version = r1;
|
||||||
|
mutex_unlock(&qcom_scm_lock);
|
||||||
|
|
||||||
|
return version;
|
||||||
|
}
|
||||||
|
EXPORT_SYMBOL(qcom_scm_get_version);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Set the cold/warm boot address for one of the CPU cores.
|
||||||
|
*/
|
||||||
|
static int qcom_scm_set_boot_addr(u32 addr, int flags)
|
||||||
|
{
|
||||||
|
struct {
|
||||||
|
__le32 flags;
|
||||||
|
__le32 addr;
|
||||||
|
} cmd;
|
||||||
|
|
||||||
|
cmd.addr = cpu_to_le32(addr);
|
||||||
|
cmd.flags = cpu_to_le32(flags);
|
||||||
|
return qcom_scm_call(QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_ADDR,
|
||||||
|
&cmd, sizeof(cmd), NULL, 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* qcom_scm_set_cold_boot_addr() - Set the cold boot address for cpus
|
||||||
|
* @entry: Entry point function for the cpus
|
||||||
|
* @cpus: The cpumask of cpus that will use the entry point
|
||||||
|
*
|
||||||
|
* Set the cold boot address of the cpus. Any cpu outside the supported
|
||||||
|
* range would be removed from the cpu present mask.
|
||||||
|
*/
|
||||||
|
int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
|
||||||
|
{
|
||||||
|
int flags = 0;
|
||||||
|
int cpu;
|
||||||
|
int scm_cb_flags[] = {
|
||||||
|
QCOM_SCM_FLAG_COLDBOOT_CPU0,
|
||||||
|
QCOM_SCM_FLAG_COLDBOOT_CPU1,
|
||||||
|
QCOM_SCM_FLAG_COLDBOOT_CPU2,
|
||||||
|
QCOM_SCM_FLAG_COLDBOOT_CPU3,
|
||||||
|
};
|
||||||
|
|
||||||
|
if (!cpus || (cpus && cpumask_empty(cpus)))
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
for_each_cpu(cpu, cpus) {
|
||||||
|
if (cpu < ARRAY_SIZE(scm_cb_flags))
|
||||||
|
flags |= scm_cb_flags[cpu];
|
||||||
|
else
|
||||||
|
set_cpu_present(cpu, false);
|
||||||
|
}
|
||||||
|
|
||||||
|
return qcom_scm_set_boot_addr(virt_to_phys(entry), flags);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* qcom_scm_set_warm_boot_addr() - Set the warm boot address for cpus
|
||||||
|
* @entry: Entry point function for the cpus
|
||||||
|
* @cpus: The cpumask of cpus that will use the entry point
|
||||||
|
*
|
||||||
|
* Set the Linux entry point for the SCM to transfer control to when coming
|
||||||
|
* out of a power down. CPU power down may be executed on cpuidle or hotplug.
|
||||||
|
*/
|
||||||
|
int __qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
|
||||||
|
{
|
||||||
|
int ret;
|
||||||
|
int flags = 0;
|
||||||
|
int cpu;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Reassign only if we are switching from hotplug entry point
|
||||||
|
* to cpuidle entry point or vice versa.
|
||||||
|
*/
|
||||||
|
for_each_cpu(cpu, cpus) {
|
||||||
|
if (entry == qcom_scm_wb[cpu].entry)
|
||||||
|
continue;
|
||||||
|
flags |= qcom_scm_wb[cpu].flag;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* No change in entry function */
|
||||||
|
if (!flags)
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
ret = qcom_scm_set_boot_addr(virt_to_phys(entry), flags);
|
||||||
|
if (!ret) {
|
||||||
|
for_each_cpu(cpu, cpus)
|
||||||
|
qcom_scm_wb[cpu].entry = entry;
|
||||||
|
}
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* qcom_scm_cpu_power_down() - Power down the cpu
|
||||||
|
* @flags - Flags to flush cache
|
||||||
|
*
|
||||||
|
* This is an end point to power down cpu. If there was a pending interrupt,
|
||||||
|
* the control would return from this function, otherwise, the cpu jumps to the
|
||||||
|
* warm boot entry point set for this cpu upon reset.
|
||||||
|
*/
|
||||||
|
void __qcom_scm_cpu_power_down(u32 flags)
|
||||||
|
{
|
||||||
|
qcom_scm_call_atomic1(QCOM_SCM_SVC_BOOT, QCOM_SCM_CMD_TERMINATE_PC,
|
||||||
|
flags & QCOM_SCM_FLUSH_FLAG_MASK);
|
||||||
|
}
|
||||||
|
|
||||||
|
int __qcom_scm_is_call_available(u32 svc_id, u32 cmd_id)
|
||||||
|
{
|
||||||
|
int ret;
|
||||||
|
u32 svc_cmd = (svc_id << 10) | cmd_id;
|
||||||
|
u32 ret_val = 0;
|
||||||
|
|
||||||
|
ret = qcom_scm_call(QCOM_SCM_SVC_INFO, QCOM_IS_CALL_AVAIL_CMD, &svc_cmd,
|
||||||
|
sizeof(svc_cmd), &ret_val, sizeof(ret_val));
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
return ret_val;
|
||||||
|
}
|
||||||
|
|
||||||
|
int __qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp)
|
||||||
|
{
|
||||||
|
if (req_cnt > QCOM_SCM_HDCP_MAX_REQ_CNT)
|
||||||
|
return -ERANGE;
|
||||||
|
|
||||||
|
return qcom_scm_call(QCOM_SCM_SVC_HDCP, QCOM_SCM_CMD_HDCP,
|
||||||
|
req, req_cnt * sizeof(*req), resp, sizeof(*resp));
|
||||||
|
}
|
||||||
|
|
@ -1,4 +1,4 @@
|
||||||
/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
|
/* Copyright (c) 2010,2015, The Linux Foundation. All rights reserved.
|
||||||
* Copyright (C) 2015 Linaro Ltd.
|
* Copyright (C) 2015 Linaro Ltd.
|
||||||
*
|
*
|
||||||
* This program is free software; you can redistribute it and/or modify
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
|
@ -16,393 +16,12 @@
|
||||||
* 02110-1301, USA.
|
* 02110-1301, USA.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include <linux/slab.h>
|
#include <linux/cpumask.h>
|
||||||
#include <linux/io.h>
|
#include <linux/export.h>
|
||||||
#include <linux/module.h>
|
#include <linux/types.h>
|
||||||
#include <linux/mutex.h>
|
|
||||||
#include <linux/errno.h>
|
|
||||||
#include <linux/err.h>
|
|
||||||
#include <linux/qcom_scm.h>
|
#include <linux/qcom_scm.h>
|
||||||
|
|
||||||
#include <asm/outercache.h>
|
#include "qcom_scm.h"
|
||||||
#include <asm/cacheflush.h>
|
|
||||||
|
|
||||||
|
|
||||||
#define QCOM_SCM_ENOMEM -5
|
|
||||||
#define QCOM_SCM_EOPNOTSUPP -4
|
|
||||||
#define QCOM_SCM_EINVAL_ADDR -3
|
|
||||||
#define QCOM_SCM_EINVAL_ARG -2
|
|
||||||
#define QCOM_SCM_ERROR -1
|
|
||||||
#define QCOM_SCM_INTERRUPTED 1
|
|
||||||
|
|
||||||
#define QCOM_SCM_FLAG_COLDBOOT_CPU0 0x00
|
|
||||||
#define QCOM_SCM_FLAG_COLDBOOT_CPU1 0x01
|
|
||||||
#define QCOM_SCM_FLAG_COLDBOOT_CPU2 0x08
|
|
||||||
#define QCOM_SCM_FLAG_COLDBOOT_CPU3 0x20
|
|
||||||
|
|
||||||
#define QCOM_SCM_FLAG_WARMBOOT_CPU0 0x04
|
|
||||||
#define QCOM_SCM_FLAG_WARMBOOT_CPU1 0x02
|
|
||||||
#define QCOM_SCM_FLAG_WARMBOOT_CPU2 0x10
|
|
||||||
#define QCOM_SCM_FLAG_WARMBOOT_CPU3 0x40
|
|
||||||
|
|
||||||
struct qcom_scm_entry {
|
|
||||||
int flag;
|
|
||||||
void *entry;
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct qcom_scm_entry qcom_scm_wb[] = {
|
|
||||||
{ .flag = QCOM_SCM_FLAG_WARMBOOT_CPU0 },
|
|
||||||
{ .flag = QCOM_SCM_FLAG_WARMBOOT_CPU1 },
|
|
||||||
{ .flag = QCOM_SCM_FLAG_WARMBOOT_CPU2 },
|
|
||||||
{ .flag = QCOM_SCM_FLAG_WARMBOOT_CPU3 },
|
|
||||||
};
|
|
||||||
|
|
||||||
static DEFINE_MUTEX(qcom_scm_lock);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* struct qcom_scm_command - one SCM command buffer
|
|
||||||
* @len: total available memory for command and response
|
|
||||||
* @buf_offset: start of command buffer
|
|
||||||
* @resp_hdr_offset: start of response buffer
|
|
||||||
* @id: command to be executed
|
|
||||||
* @buf: buffer returned from qcom_scm_get_command_buffer()
|
|
||||||
*
|
|
||||||
* An SCM command is laid out in memory as follows:
|
|
||||||
*
|
|
||||||
* ------------------- <--- struct qcom_scm_command
|
|
||||||
* | command header |
|
|
||||||
* ------------------- <--- qcom_scm_get_command_buffer()
|
|
||||||
* | command buffer |
|
|
||||||
* ------------------- <--- struct qcom_scm_response and
|
|
||||||
* | response header | qcom_scm_command_to_response()
|
|
||||||
* ------------------- <--- qcom_scm_get_response_buffer()
|
|
||||||
* | response buffer |
|
|
||||||
* -------------------
|
|
||||||
*
|
|
||||||
* There can be arbitrary padding between the headers and buffers so
|
|
||||||
* you should always use the appropriate qcom_scm_get_*_buffer() routines
|
|
||||||
* to access the buffers in a safe manner.
|
|
||||||
*/
|
|
||||||
struct qcom_scm_command {
|
|
||||||
__le32 len;
|
|
||||||
__le32 buf_offset;
|
|
||||||
__le32 resp_hdr_offset;
|
|
||||||
__le32 id;
|
|
||||||
__le32 buf[0];
|
|
||||||
};
|
|
||||||
|
|
||||||
/**
|
|
||||||
* struct qcom_scm_response - one SCM response buffer
|
|
||||||
* @len: total available memory for response
|
|
||||||
* @buf_offset: start of response data relative to start of qcom_scm_response
|
|
||||||
* @is_complete: indicates if the command has finished processing
|
|
||||||
*/
|
|
||||||
struct qcom_scm_response {
|
|
||||||
__le32 len;
|
|
||||||
__le32 buf_offset;
|
|
||||||
__le32 is_complete;
|
|
||||||
};
|
|
||||||
|
|
||||||
/**
|
|
||||||
* alloc_qcom_scm_command() - Allocate an SCM command
|
|
||||||
* @cmd_size: size of the command buffer
|
|
||||||
* @resp_size: size of the response buffer
|
|
||||||
*
|
|
||||||
* Allocate an SCM command, including enough room for the command
|
|
||||||
* and response headers as well as the command and response buffers.
|
|
||||||
*
|
|
||||||
* Returns a valid &qcom_scm_command on success or %NULL if the allocation fails.
|
|
||||||
*/
|
|
||||||
static struct qcom_scm_command *alloc_qcom_scm_command(size_t cmd_size, size_t resp_size)
|
|
||||||
{
|
|
||||||
struct qcom_scm_command *cmd;
|
|
||||||
size_t len = sizeof(*cmd) + sizeof(struct qcom_scm_response) + cmd_size +
|
|
||||||
resp_size;
|
|
||||||
u32 offset;
|
|
||||||
|
|
||||||
cmd = kzalloc(PAGE_ALIGN(len), GFP_KERNEL);
|
|
||||||
if (cmd) {
|
|
||||||
cmd->len = cpu_to_le32(len);
|
|
||||||
offset = offsetof(struct qcom_scm_command, buf);
|
|
||||||
cmd->buf_offset = cpu_to_le32(offset);
|
|
||||||
cmd->resp_hdr_offset = cpu_to_le32(offset + cmd_size);
|
|
||||||
}
|
|
||||||
return cmd;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* free_qcom_scm_command() - Free an SCM command
|
|
||||||
* @cmd: command to free
|
|
||||||
*
|
|
||||||
* Free an SCM command.
|
|
||||||
*/
|
|
||||||
static inline void free_qcom_scm_command(struct qcom_scm_command *cmd)
|
|
||||||
{
|
|
||||||
kfree(cmd);
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* qcom_scm_command_to_response() - Get a pointer to a qcom_scm_response
|
|
||||||
* @cmd: command
|
|
||||||
*
|
|
||||||
* Returns a pointer to a response for a command.
|
|
||||||
*/
|
|
||||||
static inline struct qcom_scm_response *qcom_scm_command_to_response(
|
|
||||||
const struct qcom_scm_command *cmd)
|
|
||||||
{
|
|
||||||
return (void *)cmd + le32_to_cpu(cmd->resp_hdr_offset);
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* qcom_scm_get_command_buffer() - Get a pointer to a command buffer
|
|
||||||
* @cmd: command
|
|
||||||
*
|
|
||||||
* Returns a pointer to the command buffer of a command.
|
|
||||||
*/
|
|
||||||
static inline void *qcom_scm_get_command_buffer(const struct qcom_scm_command *cmd)
|
|
||||||
{
|
|
||||||
return (void *)cmd->buf;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* qcom_scm_get_response_buffer() - Get a pointer to a response buffer
|
|
||||||
* @rsp: response
|
|
||||||
*
|
|
||||||
* Returns a pointer to a response buffer of a response.
|
|
||||||
*/
|
|
||||||
static inline void *qcom_scm_get_response_buffer(const struct qcom_scm_response *rsp)
|
|
||||||
{
|
|
||||||
return (void *)rsp + le32_to_cpu(rsp->buf_offset);
|
|
||||||
}
|
|
||||||
|
|
||||||
static int qcom_scm_remap_error(int err)
|
|
||||||
{
|
|
||||||
pr_err("qcom_scm_call failed with error code %d\n", err);
|
|
||||||
switch (err) {
|
|
||||||
case QCOM_SCM_ERROR:
|
|
||||||
return -EIO;
|
|
||||||
case QCOM_SCM_EINVAL_ADDR:
|
|
||||||
case QCOM_SCM_EINVAL_ARG:
|
|
||||||
return -EINVAL;
|
|
||||||
case QCOM_SCM_EOPNOTSUPP:
|
|
||||||
return -EOPNOTSUPP;
|
|
||||||
case QCOM_SCM_ENOMEM:
|
|
||||||
return -ENOMEM;
|
|
||||||
}
|
|
||||||
return -EINVAL;
|
|
||||||
}
|
|
||||||
|
|
||||||
static u32 smc(u32 cmd_addr)
|
|
||||||
{
|
|
||||||
int context_id;
|
|
||||||
register u32 r0 asm("r0") = 1;
|
|
||||||
register u32 r1 asm("r1") = (u32)&context_id;
|
|
||||||
register u32 r2 asm("r2") = cmd_addr;
|
|
||||||
do {
|
|
||||||
asm volatile(
|
|
||||||
__asmeq("%0", "r0")
|
|
||||||
__asmeq("%1", "r0")
|
|
||||||
__asmeq("%2", "r1")
|
|
||||||
__asmeq("%3", "r2")
|
|
||||||
#ifdef REQUIRES_SEC
|
|
||||||
".arch_extension sec\n"
|
|
||||||
#endif
|
|
||||||
"smc #0 @ switch to secure world\n"
|
|
||||||
: "=r" (r0)
|
|
||||||
: "r" (r0), "r" (r1), "r" (r2)
|
|
||||||
: "r3");
|
|
||||||
} while (r0 == QCOM_SCM_INTERRUPTED);
|
|
||||||
|
|
||||||
return r0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int __qcom_scm_call(const struct qcom_scm_command *cmd)
|
|
||||||
{
|
|
||||||
int ret;
|
|
||||||
u32 cmd_addr = virt_to_phys(cmd);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Flush the command buffer so that the secure world sees
|
|
||||||
* the correct data.
|
|
||||||
*/
|
|
||||||
__cpuc_flush_dcache_area((void *)cmd, cmd->len);
|
|
||||||
outer_flush_range(cmd_addr, cmd_addr + cmd->len);
|
|
||||||
|
|
||||||
ret = smc(cmd_addr);
|
|
||||||
if (ret < 0)
|
|
||||||
ret = qcom_scm_remap_error(ret);
|
|
||||||
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
|
|
||||||
static void qcom_scm_inv_range(unsigned long start, unsigned long end)
|
|
||||||
{
|
|
||||||
u32 cacheline_size, ctr;
|
|
||||||
|
|
||||||
asm volatile("mrc p15, 0, %0, c0, c0, 1" : "=r" (ctr));
|
|
||||||
cacheline_size = 4 << ((ctr >> 16) & 0xf);
|
|
||||||
|
|
||||||
start = round_down(start, cacheline_size);
|
|
||||||
end = round_up(end, cacheline_size);
|
|
||||||
outer_inv_range(start, end);
|
|
||||||
while (start < end) {
|
|
||||||
asm ("mcr p15, 0, %0, c7, c6, 1" : : "r" (start)
|
|
||||||
: "memory");
|
|
||||||
start += cacheline_size;
|
|
||||||
}
|
|
||||||
dsb();
|
|
||||||
isb();
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* qcom_scm_call() - Send an SCM command
|
|
||||||
* @svc_id: service identifier
|
|
||||||
* @cmd_id: command identifier
|
|
||||||
* @cmd_buf: command buffer
|
|
||||||
* @cmd_len: length of the command buffer
|
|
||||||
* @resp_buf: response buffer
|
|
||||||
* @resp_len: length of the response buffer
|
|
||||||
*
|
|
||||||
* Sends a command to the SCM and waits for the command to finish processing.
|
|
||||||
*
|
|
||||||
* A note on cache maintenance:
|
|
||||||
* Note that any buffers that are expected to be accessed by the secure world
|
|
||||||
* must be flushed before invoking qcom_scm_call and invalidated in the cache
|
|
||||||
* immediately after qcom_scm_call returns. Cache maintenance on the command
|
|
||||||
* and response buffers is taken care of by qcom_scm_call; however, callers are
|
|
||||||
* responsible for any other cached buffers passed over to the secure world.
|
|
||||||
*/
|
|
||||||
static int qcom_scm_call(u32 svc_id, u32 cmd_id, const void *cmd_buf,
|
|
||||||
size_t cmd_len, void *resp_buf, size_t resp_len)
|
|
||||||
{
|
|
||||||
int ret;
|
|
||||||
struct qcom_scm_command *cmd;
|
|
||||||
struct qcom_scm_response *rsp;
|
|
||||||
unsigned long start, end;
|
|
||||||
|
|
||||||
cmd = alloc_qcom_scm_command(cmd_len, resp_len);
|
|
||||||
if (!cmd)
|
|
||||||
return -ENOMEM;
|
|
||||||
|
|
||||||
cmd->id = cpu_to_le32((svc_id << 10) | cmd_id);
|
|
||||||
if (cmd_buf)
|
|
||||||
memcpy(qcom_scm_get_command_buffer(cmd), cmd_buf, cmd_len);
|
|
||||||
|
|
||||||
mutex_lock(&qcom_scm_lock);
|
|
||||||
ret = __qcom_scm_call(cmd);
|
|
||||||
mutex_unlock(&qcom_scm_lock);
|
|
||||||
if (ret)
|
|
||||||
goto out;
|
|
||||||
|
|
||||||
rsp = qcom_scm_command_to_response(cmd);
|
|
||||||
start = (unsigned long)rsp;
|
|
||||||
|
|
||||||
do {
|
|
||||||
qcom_scm_inv_range(start, start + sizeof(*rsp));
|
|
||||||
} while (!rsp->is_complete);
|
|
||||||
|
|
||||||
end = (unsigned long)qcom_scm_get_response_buffer(rsp) + resp_len;
|
|
||||||
qcom_scm_inv_range(start, end);
|
|
||||||
|
|
||||||
if (resp_buf)
|
|
||||||
memcpy(resp_buf, qcom_scm_get_response_buffer(rsp), resp_len);
|
|
||||||
out:
|
|
||||||
free_qcom_scm_command(cmd);
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
|
|
||||||
#define SCM_CLASS_REGISTER (0x2 << 8)
|
|
||||||
#define SCM_MASK_IRQS BIT(5)
|
|
||||||
#define SCM_ATOMIC(svc, cmd, n) (((((svc) << 10)|((cmd) & 0x3ff)) << 12) | \
|
|
||||||
SCM_CLASS_REGISTER | \
|
|
||||||
SCM_MASK_IRQS | \
|
|
||||||
(n & 0xf))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* qcom_scm_call_atomic1() - Send an atomic SCM command with one argument
|
|
||||||
* @svc_id: service identifier
|
|
||||||
* @cmd_id: command identifier
|
|
||||||
* @arg1: first argument
|
|
||||||
*
|
|
||||||
* This shall only be used with commands that are guaranteed to be
|
|
||||||
* uninterruptable, atomic and SMP safe.
|
|
||||||
*/
|
|
||||||
static s32 qcom_scm_call_atomic1(u32 svc, u32 cmd, u32 arg1)
|
|
||||||
{
|
|
||||||
int context_id;
|
|
||||||
|
|
||||||
register u32 r0 asm("r0") = SCM_ATOMIC(svc, cmd, 1);
|
|
||||||
register u32 r1 asm("r1") = (u32)&context_id;
|
|
||||||
register u32 r2 asm("r2") = arg1;
|
|
||||||
|
|
||||||
asm volatile(
|
|
||||||
__asmeq("%0", "r0")
|
|
||||||
__asmeq("%1", "r0")
|
|
||||||
__asmeq("%2", "r1")
|
|
||||||
__asmeq("%3", "r2")
|
|
||||||
#ifdef REQUIRES_SEC
|
|
||||||
".arch_extension sec\n"
|
|
||||||
#endif
|
|
||||||
"smc #0 @ switch to secure world\n"
|
|
||||||
: "=r" (r0)
|
|
||||||
: "r" (r0), "r" (r1), "r" (r2)
|
|
||||||
: "r3");
|
|
||||||
return r0;
|
|
||||||
}
|
|
||||||
|
|
||||||
u32 qcom_scm_get_version(void)
|
|
||||||
{
|
|
||||||
int context_id;
|
|
||||||
static u32 version = -1;
|
|
||||||
register u32 r0 asm("r0");
|
|
||||||
register u32 r1 asm("r1");
|
|
||||||
|
|
||||||
if (version != -1)
|
|
||||||
return version;
|
|
||||||
|
|
||||||
mutex_lock(&qcom_scm_lock);
|
|
||||||
|
|
||||||
r0 = 0x1 << 8;
|
|
||||||
r1 = (u32)&context_id;
|
|
||||||
do {
|
|
||||||
asm volatile(
|
|
||||||
__asmeq("%0", "r0")
|
|
||||||
__asmeq("%1", "r1")
|
|
||||||
__asmeq("%2", "r0")
|
|
||||||
__asmeq("%3", "r1")
|
|
||||||
#ifdef REQUIRES_SEC
|
|
||||||
".arch_extension sec\n"
|
|
||||||
#endif
|
|
||||||
"smc #0 @ switch to secure world\n"
|
|
||||||
: "=r" (r0), "=r" (r1)
|
|
||||||
: "r" (r0), "r" (r1)
|
|
||||||
: "r2", "r3");
|
|
||||||
} while (r0 == QCOM_SCM_INTERRUPTED);
|
|
||||||
|
|
||||||
version = r1;
|
|
||||||
mutex_unlock(&qcom_scm_lock);
|
|
||||||
|
|
||||||
return version;
|
|
||||||
}
|
|
||||||
EXPORT_SYMBOL(qcom_scm_get_version);
|
|
||||||
|
|
||||||
#define QCOM_SCM_SVC_BOOT 0x1
|
|
||||||
#define QCOM_SCM_BOOT_ADDR 0x1
|
|
||||||
/*
|
|
||||||
* Set the cold/warm boot address for one of the CPU cores.
|
|
||||||
*/
|
|
||||||
static int qcom_scm_set_boot_addr(u32 addr, int flags)
|
|
||||||
{
|
|
||||||
struct {
|
|
||||||
__le32 flags;
|
|
||||||
__le32 addr;
|
|
||||||
} cmd;
|
|
||||||
|
|
||||||
cmd.addr = cpu_to_le32(addr);
|
|
||||||
cmd.flags = cpu_to_le32(flags);
|
|
||||||
return qcom_scm_call(QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_ADDR,
|
|
||||||
&cmd, sizeof(cmd), NULL, 0);
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* qcom_scm_set_cold_boot_addr() - Set the cold boot address for cpus
|
* qcom_scm_set_cold_boot_addr() - Set the cold boot address for cpus
|
||||||
|
|
@ -414,26 +33,7 @@ static int qcom_scm_set_boot_addr(u32 addr, int flags)
|
||||||
*/
|
*/
|
||||||
int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
|
int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
|
||||||
{
|
{
|
||||||
int flags = 0;
|
return __qcom_scm_set_cold_boot_addr(entry, cpus);
|
||||||
int cpu;
|
|
||||||
int scm_cb_flags[] = {
|
|
||||||
QCOM_SCM_FLAG_COLDBOOT_CPU0,
|
|
||||||
QCOM_SCM_FLAG_COLDBOOT_CPU1,
|
|
||||||
QCOM_SCM_FLAG_COLDBOOT_CPU2,
|
|
||||||
QCOM_SCM_FLAG_COLDBOOT_CPU3,
|
|
||||||
};
|
|
||||||
|
|
||||||
if (!cpus || (cpus && cpumask_empty(cpus)))
|
|
||||||
return -EINVAL;
|
|
||||||
|
|
||||||
for_each_cpu(cpu, cpus) {
|
|
||||||
if (cpu < ARRAY_SIZE(scm_cb_flags))
|
|
||||||
flags |= scm_cb_flags[cpu];
|
|
||||||
else
|
|
||||||
set_cpu_present(cpu, false);
|
|
||||||
}
|
|
||||||
|
|
||||||
return qcom_scm_set_boot_addr(virt_to_phys(entry), flags);
|
|
||||||
}
|
}
|
||||||
EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr);
|
EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr);
|
||||||
|
|
||||||
|
|
@ -447,37 +47,10 @@ EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr);
|
||||||
*/
|
*/
|
||||||
int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
|
int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
|
||||||
{
|
{
|
||||||
int ret;
|
return __qcom_scm_set_warm_boot_addr(entry, cpus);
|
||||||
int flags = 0;
|
|
||||||
int cpu;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Reassign only if we are switching from hotplug entry point
|
|
||||||
* to cpuidle entry point or vice versa.
|
|
||||||
*/
|
|
||||||
for_each_cpu(cpu, cpus) {
|
|
||||||
if (entry == qcom_scm_wb[cpu].entry)
|
|
||||||
continue;
|
|
||||||
flags |= qcom_scm_wb[cpu].flag;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* No change in entry function */
|
|
||||||
if (!flags)
|
|
||||||
return 0;
|
|
||||||
|
|
||||||
ret = qcom_scm_set_boot_addr(virt_to_phys(entry), flags);
|
|
||||||
if (!ret) {
|
|
||||||
for_each_cpu(cpu, cpus)
|
|
||||||
qcom_scm_wb[cpu].entry = entry;
|
|
||||||
}
|
|
||||||
|
|
||||||
return ret;
|
|
||||||
}
|
}
|
||||||
EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr);
|
EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr);
|
||||||
|
|
||||||
#define QCOM_SCM_CMD_TERMINATE_PC 0x2
|
|
||||||
#define QCOM_SCM_FLUSH_FLAG_MASK 0x3
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* qcom_scm_cpu_power_down() - Power down the cpu
|
* qcom_scm_cpu_power_down() - Power down the cpu
|
||||||
* @flags - Flags to flush cache
|
* @flags - Flags to flush cache
|
||||||
|
|
@ -488,7 +61,36 @@ EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr);
|
||||||
*/
|
*/
|
||||||
void qcom_scm_cpu_power_down(u32 flags)
|
void qcom_scm_cpu_power_down(u32 flags)
|
||||||
{
|
{
|
||||||
qcom_scm_call_atomic1(QCOM_SCM_SVC_BOOT, QCOM_SCM_CMD_TERMINATE_PC,
|
__qcom_scm_cpu_power_down(flags);
|
||||||
flags & QCOM_SCM_FLUSH_FLAG_MASK);
|
|
||||||
}
|
}
|
||||||
EXPORT_SYMBOL(qcom_scm_cpu_power_down);
|
EXPORT_SYMBOL(qcom_scm_cpu_power_down);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* qcom_scm_hdcp_available() - Check if secure environment supports HDCP.
|
||||||
|
*
|
||||||
|
* Return true if HDCP is supported, false if not.
|
||||||
|
*/
|
||||||
|
bool qcom_scm_hdcp_available(void)
|
||||||
|
{
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
ret = __qcom_scm_is_call_available(QCOM_SCM_SVC_HDCP,
|
||||||
|
QCOM_SCM_CMD_HDCP);
|
||||||
|
|
||||||
|
return (ret > 0) ? true : false;
|
||||||
|
}
|
||||||
|
EXPORT_SYMBOL(qcom_scm_hdcp_available);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* qcom_scm_hdcp_req() - Send HDCP request.
|
||||||
|
* @req: HDCP request array
|
||||||
|
* @req_cnt: HDCP request array count
|
||||||
|
* @resp: response buffer passed to SCM
|
||||||
|
*
|
||||||
|
* Write HDCP register(s) through SCM.
|
||||||
|
*/
|
||||||
|
int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp)
|
||||||
|
{
|
||||||
|
return __qcom_scm_hdcp_req(req, req_cnt, resp);
|
||||||
|
}
|
||||||
|
EXPORT_SYMBOL(qcom_scm_hdcp_req);
|
||||||
|
|
|
||||||
47
drivers/firmware/qcom_scm.h
Normal file
47
drivers/firmware/qcom_scm.h
Normal file
|
|
@ -0,0 +1,47 @@
|
||||||
|
/* Copyright (c) 2010-2015, The Linux Foundation. All rights reserved.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License version 2 and
|
||||||
|
* only version 2 as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*/
|
||||||
|
#ifndef __QCOM_SCM_INT_H
|
||||||
|
#define __QCOM_SCM_INT_H
|
||||||
|
|
||||||
|
#define QCOM_SCM_SVC_BOOT 0x1
|
||||||
|
#define QCOM_SCM_BOOT_ADDR 0x1
|
||||||
|
#define QCOM_SCM_BOOT_ADDR_MC 0x11
|
||||||
|
|
||||||
|
#define QCOM_SCM_FLAG_HLOS 0x01
|
||||||
|
#define QCOM_SCM_FLAG_COLDBOOT_MC 0x02
|
||||||
|
#define QCOM_SCM_FLAG_WARMBOOT_MC 0x04
|
||||||
|
extern int __qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus);
|
||||||
|
extern int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus);
|
||||||
|
|
||||||
|
#define QCOM_SCM_CMD_TERMINATE_PC 0x2
|
||||||
|
#define QCOM_SCM_FLUSH_FLAG_MASK 0x3
|
||||||
|
#define QCOM_SCM_CMD_CORE_HOTPLUGGED 0x10
|
||||||
|
extern void __qcom_scm_cpu_power_down(u32 flags);
|
||||||
|
|
||||||
|
#define QCOM_SCM_SVC_INFO 0x6
|
||||||
|
#define QCOM_IS_CALL_AVAIL_CMD 0x1
|
||||||
|
extern int __qcom_scm_is_call_available(u32 svc_id, u32 cmd_id);
|
||||||
|
|
||||||
|
#define QCOM_SCM_SVC_HDCP 0x11
|
||||||
|
#define QCOM_SCM_CMD_HDCP 0x01
|
||||||
|
extern int __qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
|
||||||
|
u32 *resp);
|
||||||
|
|
||||||
|
/* common error codes */
|
||||||
|
#define QCOM_SCM_ENOMEM -5
|
||||||
|
#define QCOM_SCM_EOPNOTSUPP -4
|
||||||
|
#define QCOM_SCM_EINVAL_ADDR -3
|
||||||
|
#define QCOM_SCM_EINVAL_ARG -2
|
||||||
|
#define QCOM_SCM_ERROR -1
|
||||||
|
#define QCOM_SCM_INTERRUPTED 1
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -10,3 +10,10 @@ config QCOM_GSBI
|
||||||
functions for connecting the underlying serial UART, SPI, and I2C
|
functions for connecting the underlying serial UART, SPI, and I2C
|
||||||
devices to the output pins.
|
devices to the output pins.
|
||||||
|
|
||||||
|
config QCOM_PM
|
||||||
|
bool "Qualcomm Power Management"
|
||||||
|
depends on ARCH_QCOM && !ARM64
|
||||||
|
help
|
||||||
|
QCOM Platform specific power driver to manage cores and L2 low power
|
||||||
|
modes. It interface with various system drivers to put the cores in
|
||||||
|
low power modes.
|
||||||
|
|
|
||||||
|
|
@ -1 +1,2 @@
|
||||||
obj-$(CONFIG_QCOM_GSBI) += qcom_gsbi.o
|
obj-$(CONFIG_QCOM_GSBI) += qcom_gsbi.o
|
||||||
|
obj-$(CONFIG_QCOM_PM) += spm.o
|
||||||
|
|
|
||||||
385
drivers/soc/qcom/spm.c
Normal file
385
drivers/soc/qcom/spm.c
Normal file
|
|
@ -0,0 +1,385 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2011-2014, The Linux Foundation. All rights reserved.
|
||||||
|
* Copyright (c) 2014,2015, Linaro Ltd.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License version 2 and
|
||||||
|
* only version 2 as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <linux/module.h>
|
||||||
|
#include <linux/kernel.h>
|
||||||
|
#include <linux/init.h>
|
||||||
|
#include <linux/io.h>
|
||||||
|
#include <linux/slab.h>
|
||||||
|
#include <linux/of.h>
|
||||||
|
#include <linux/of_address.h>
|
||||||
|
#include <linux/of_device.h>
|
||||||
|
#include <linux/err.h>
|
||||||
|
#include <linux/platform_device.h>
|
||||||
|
#include <linux/cpuidle.h>
|
||||||
|
#include <linux/cpu_pm.h>
|
||||||
|
#include <linux/qcom_scm.h>
|
||||||
|
|
||||||
|
#include <asm/cpuidle.h>
|
||||||
|
#include <asm/proc-fns.h>
|
||||||
|
#include <asm/suspend.h>
|
||||||
|
|
||||||
|
#define MAX_PMIC_DATA 2
|
||||||
|
#define MAX_SEQ_DATA 64
|
||||||
|
#define SPM_CTL_INDEX 0x7f
|
||||||
|
#define SPM_CTL_INDEX_SHIFT 4
|
||||||
|
#define SPM_CTL_EN BIT(0)
|
||||||
|
|
||||||
|
enum pm_sleep_mode {
|
||||||
|
PM_SLEEP_MODE_STBY,
|
||||||
|
PM_SLEEP_MODE_RET,
|
||||||
|
PM_SLEEP_MODE_SPC,
|
||||||
|
PM_SLEEP_MODE_PC,
|
||||||
|
PM_SLEEP_MODE_NR,
|
||||||
|
};
|
||||||
|
|
||||||
|
enum spm_reg {
|
||||||
|
SPM_REG_CFG,
|
||||||
|
SPM_REG_SPM_CTL,
|
||||||
|
SPM_REG_DLY,
|
||||||
|
SPM_REG_PMIC_DLY,
|
||||||
|
SPM_REG_PMIC_DATA_0,
|
||||||
|
SPM_REG_PMIC_DATA_1,
|
||||||
|
SPM_REG_VCTL,
|
||||||
|
SPM_REG_SEQ_ENTRY,
|
||||||
|
SPM_REG_SPM_STS,
|
||||||
|
SPM_REG_PMIC_STS,
|
||||||
|
SPM_REG_NR,
|
||||||
|
};
|
||||||
|
|
||||||
|
struct spm_reg_data {
|
||||||
|
const u8 *reg_offset;
|
||||||
|
u32 spm_cfg;
|
||||||
|
u32 spm_dly;
|
||||||
|
u32 pmic_dly;
|
||||||
|
u32 pmic_data[MAX_PMIC_DATA];
|
||||||
|
u8 seq[MAX_SEQ_DATA];
|
||||||
|
u8 start_index[PM_SLEEP_MODE_NR];
|
||||||
|
};
|
||||||
|
|
||||||
|
struct spm_driver_data {
|
||||||
|
void __iomem *reg_base;
|
||||||
|
const struct spm_reg_data *reg_data;
|
||||||
|
};
|
||||||
|
|
||||||
|
static const u8 spm_reg_offset_v2_1[SPM_REG_NR] = {
|
||||||
|
[SPM_REG_CFG] = 0x08,
|
||||||
|
[SPM_REG_SPM_CTL] = 0x30,
|
||||||
|
[SPM_REG_DLY] = 0x34,
|
||||||
|
[SPM_REG_SEQ_ENTRY] = 0x80,
|
||||||
|
};
|
||||||
|
|
||||||
|
/* SPM register data for 8974, 8084 */
|
||||||
|
static const struct spm_reg_data spm_reg_8974_8084_cpu = {
|
||||||
|
.reg_offset = spm_reg_offset_v2_1,
|
||||||
|
.spm_cfg = 0x1,
|
||||||
|
.spm_dly = 0x3C102800,
|
||||||
|
.seq = { 0x03, 0x0B, 0x0F, 0x00, 0x20, 0x80, 0x10, 0xE8, 0x5B, 0x03,
|
||||||
|
0x3B, 0xE8, 0x5B, 0x82, 0x10, 0x0B, 0x30, 0x06, 0x26, 0x30,
|
||||||
|
0x0F },
|
||||||
|
.start_index[PM_SLEEP_MODE_STBY] = 0,
|
||||||
|
.start_index[PM_SLEEP_MODE_SPC] = 3,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const u8 spm_reg_offset_v1_1[SPM_REG_NR] = {
|
||||||
|
[SPM_REG_CFG] = 0x08,
|
||||||
|
[SPM_REG_SPM_CTL] = 0x20,
|
||||||
|
[SPM_REG_PMIC_DLY] = 0x24,
|
||||||
|
[SPM_REG_PMIC_DATA_0] = 0x28,
|
||||||
|
[SPM_REG_PMIC_DATA_1] = 0x2C,
|
||||||
|
[SPM_REG_SEQ_ENTRY] = 0x80,
|
||||||
|
};
|
||||||
|
|
||||||
|
/* SPM register data for 8064 */
|
||||||
|
static const struct spm_reg_data spm_reg_8064_cpu = {
|
||||||
|
.reg_offset = spm_reg_offset_v1_1,
|
||||||
|
.spm_cfg = 0x1F,
|
||||||
|
.pmic_dly = 0x02020004,
|
||||||
|
.pmic_data[0] = 0x0084009C,
|
||||||
|
.pmic_data[1] = 0x00A4001C,
|
||||||
|
.seq = { 0x03, 0x0F, 0x00, 0x24, 0x54, 0x10, 0x09, 0x03, 0x01,
|
||||||
|
0x10, 0x54, 0x30, 0x0C, 0x24, 0x30, 0x0F },
|
||||||
|
.start_index[PM_SLEEP_MODE_STBY] = 0,
|
||||||
|
.start_index[PM_SLEEP_MODE_SPC] = 2,
|
||||||
|
};
|
||||||
|
|
||||||
|
static DEFINE_PER_CPU(struct spm_driver_data *, cpu_spm_drv);
|
||||||
|
|
||||||
|
typedef int (*idle_fn)(int);
|
||||||
|
static DEFINE_PER_CPU(idle_fn*, qcom_idle_ops);
|
||||||
|
|
||||||
|
static inline void spm_register_write(struct spm_driver_data *drv,
|
||||||
|
enum spm_reg reg, u32 val)
|
||||||
|
{
|
||||||
|
if (drv->reg_data->reg_offset[reg])
|
||||||
|
writel_relaxed(val, drv->reg_base +
|
||||||
|
drv->reg_data->reg_offset[reg]);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Ensure a guaranteed write, before return */
|
||||||
|
static inline void spm_register_write_sync(struct spm_driver_data *drv,
|
||||||
|
enum spm_reg reg, u32 val)
|
||||||
|
{
|
||||||
|
u32 ret;
|
||||||
|
|
||||||
|
if (!drv->reg_data->reg_offset[reg])
|
||||||
|
return;
|
||||||
|
|
||||||
|
do {
|
||||||
|
writel_relaxed(val, drv->reg_base +
|
||||||
|
drv->reg_data->reg_offset[reg]);
|
||||||
|
ret = readl_relaxed(drv->reg_base +
|
||||||
|
drv->reg_data->reg_offset[reg]);
|
||||||
|
if (ret == val)
|
||||||
|
break;
|
||||||
|
cpu_relax();
|
||||||
|
} while (1);
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline u32 spm_register_read(struct spm_driver_data *drv,
|
||||||
|
enum spm_reg reg)
|
||||||
|
{
|
||||||
|
return readl_relaxed(drv->reg_base + drv->reg_data->reg_offset[reg]);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void spm_set_low_power_mode(struct spm_driver_data *drv,
|
||||||
|
enum pm_sleep_mode mode)
|
||||||
|
{
|
||||||
|
u32 start_index;
|
||||||
|
u32 ctl_val;
|
||||||
|
|
||||||
|
start_index = drv->reg_data->start_index[mode];
|
||||||
|
|
||||||
|
ctl_val = spm_register_read(drv, SPM_REG_SPM_CTL);
|
||||||
|
ctl_val &= ~(SPM_CTL_INDEX << SPM_CTL_INDEX_SHIFT);
|
||||||
|
ctl_val |= start_index << SPM_CTL_INDEX_SHIFT;
|
||||||
|
ctl_val |= SPM_CTL_EN;
|
||||||
|
spm_register_write_sync(drv, SPM_REG_SPM_CTL, ctl_val);
|
||||||
|
}
|
||||||
|
|
||||||
|
static int qcom_pm_collapse(unsigned long int unused)
|
||||||
|
{
|
||||||
|
qcom_scm_cpu_power_down(QCOM_SCM_CPU_PWR_DOWN_L2_ON);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Returns here only if there was a pending interrupt and we did not
|
||||||
|
* power down as a result.
|
||||||
|
*/
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int qcom_cpu_spc(int cpu)
|
||||||
|
{
|
||||||
|
int ret;
|
||||||
|
struct spm_driver_data *drv = per_cpu(cpu_spm_drv, cpu);
|
||||||
|
|
||||||
|
spm_set_low_power_mode(drv, PM_SLEEP_MODE_SPC);
|
||||||
|
ret = cpu_suspend(0, qcom_pm_collapse);
|
||||||
|
/*
|
||||||
|
* ARM common code executes WFI without calling into our driver and
|
||||||
|
* if the SPM mode is not reset, then we may accidently power down the
|
||||||
|
* cpu when we intended only to gate the cpu clock.
|
||||||
|
* Ensure the state is set to standby before returning.
|
||||||
|
*/
|
||||||
|
spm_set_low_power_mode(drv, PM_SLEEP_MODE_STBY);
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int qcom_idle_enter(int cpu, unsigned long index)
|
||||||
|
{
|
||||||
|
return per_cpu(qcom_idle_ops, cpu)[index](cpu);
|
||||||
|
}
|
||||||
|
|
||||||
|
static const struct of_device_id qcom_idle_state_match[] __initconst = {
|
||||||
|
{ .compatible = "qcom,idle-state-spc", .data = qcom_cpu_spc },
|
||||||
|
{ },
|
||||||
|
};
|
||||||
|
|
||||||
|
static int __init qcom_cpuidle_init(struct device_node *cpu_node, int cpu)
|
||||||
|
{
|
||||||
|
const struct of_device_id *match_id;
|
||||||
|
struct device_node *state_node;
|
||||||
|
int i;
|
||||||
|
int state_count = 1;
|
||||||
|
idle_fn idle_fns[CPUIDLE_STATE_MAX];
|
||||||
|
idle_fn *fns;
|
||||||
|
cpumask_t mask;
|
||||||
|
bool use_scm_power_down = false;
|
||||||
|
|
||||||
|
for (i = 0; ; i++) {
|
||||||
|
state_node = of_parse_phandle(cpu_node, "cpu-idle-states", i);
|
||||||
|
if (!state_node)
|
||||||
|
break;
|
||||||
|
|
||||||
|
if (!of_device_is_available(state_node))
|
||||||
|
continue;
|
||||||
|
|
||||||
|
if (i == CPUIDLE_STATE_MAX) {
|
||||||
|
pr_warn("%s: cpuidle states reached max possible\n",
|
||||||
|
__func__);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
match_id = of_match_node(qcom_idle_state_match, state_node);
|
||||||
|
if (!match_id)
|
||||||
|
return -ENODEV;
|
||||||
|
|
||||||
|
idle_fns[state_count] = match_id->data;
|
||||||
|
|
||||||
|
/* Check if any of the states allow power down */
|
||||||
|
if (match_id->data == qcom_cpu_spc)
|
||||||
|
use_scm_power_down = true;
|
||||||
|
|
||||||
|
state_count++;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (state_count == 1)
|
||||||
|
goto check_spm;
|
||||||
|
|
||||||
|
fns = devm_kcalloc(get_cpu_device(cpu), state_count, sizeof(*fns),
|
||||||
|
GFP_KERNEL);
|
||||||
|
if (!fns)
|
||||||
|
return -ENOMEM;
|
||||||
|
|
||||||
|
for (i = 1; i < state_count; i++)
|
||||||
|
fns[i] = idle_fns[i];
|
||||||
|
|
||||||
|
if (use_scm_power_down) {
|
||||||
|
/* We have atleast one power down mode */
|
||||||
|
cpumask_clear(&mask);
|
||||||
|
cpumask_set_cpu(cpu, &mask);
|
||||||
|
qcom_scm_set_warm_boot_addr(cpu_resume, &mask);
|
||||||
|
}
|
||||||
|
|
||||||
|
per_cpu(qcom_idle_ops, cpu) = fns;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* SPM probe for the cpu should have happened by now, if the
|
||||||
|
* SPM device does not exist, return -ENXIO to indicate that the
|
||||||
|
* cpu does not support idle states.
|
||||||
|
*/
|
||||||
|
check_spm:
|
||||||
|
return per_cpu(cpu_spm_drv, cpu) ? 0 : -ENXIO;
|
||||||
|
}
|
||||||
|
|
||||||
|
static struct cpuidle_ops qcom_cpuidle_ops __initdata = {
|
||||||
|
.suspend = qcom_idle_enter,
|
||||||
|
.init = qcom_cpuidle_init,
|
||||||
|
};
|
||||||
|
|
||||||
|
CPUIDLE_METHOD_OF_DECLARE(qcom_idle_v1, "qcom,kpss-acc-v1", &qcom_cpuidle_ops);
|
||||||
|
CPUIDLE_METHOD_OF_DECLARE(qcom_idle_v2, "qcom,kpss-acc-v2", &qcom_cpuidle_ops);
|
||||||
|
|
||||||
|
static struct spm_driver_data *spm_get_drv(struct platform_device *pdev,
|
||||||
|
int *spm_cpu)
|
||||||
|
{
|
||||||
|
struct spm_driver_data *drv = NULL;
|
||||||
|
struct device_node *cpu_node, *saw_node;
|
||||||
|
int cpu;
|
||||||
|
bool found;
|
||||||
|
|
||||||
|
for_each_possible_cpu(cpu) {
|
||||||
|
cpu_node = of_cpu_device_node_get(cpu);
|
||||||
|
if (!cpu_node)
|
||||||
|
continue;
|
||||||
|
saw_node = of_parse_phandle(cpu_node, "qcom,saw", 0);
|
||||||
|
found = (saw_node == pdev->dev.of_node);
|
||||||
|
of_node_put(saw_node);
|
||||||
|
of_node_put(cpu_node);
|
||||||
|
if (found)
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (found) {
|
||||||
|
drv = devm_kzalloc(&pdev->dev, sizeof(*drv), GFP_KERNEL);
|
||||||
|
if (drv)
|
||||||
|
*spm_cpu = cpu;
|
||||||
|
}
|
||||||
|
|
||||||
|
return drv;
|
||||||
|
}
|
||||||
|
|
||||||
|
static const struct of_device_id spm_match_table[] = {
|
||||||
|
{ .compatible = "qcom,msm8974-saw2-v2.1-cpu",
|
||||||
|
.data = &spm_reg_8974_8084_cpu },
|
||||||
|
{ .compatible = "qcom,apq8084-saw2-v2.1-cpu",
|
||||||
|
.data = &spm_reg_8974_8084_cpu },
|
||||||
|
{ .compatible = "qcom,apq8064-saw2-v1.1-cpu",
|
||||||
|
.data = &spm_reg_8064_cpu },
|
||||||
|
{ },
|
||||||
|
};
|
||||||
|
|
||||||
|
static int spm_dev_probe(struct platform_device *pdev)
|
||||||
|
{
|
||||||
|
struct spm_driver_data *drv;
|
||||||
|
struct resource *res;
|
||||||
|
const struct of_device_id *match_id;
|
||||||
|
void __iomem *addr;
|
||||||
|
int cpu;
|
||||||
|
|
||||||
|
drv = spm_get_drv(pdev, &cpu);
|
||||||
|
if (!drv)
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||||
|
drv->reg_base = devm_ioremap_resource(&pdev->dev, res);
|
||||||
|
if (IS_ERR(drv->reg_base))
|
||||||
|
return PTR_ERR(drv->reg_base);
|
||||||
|
|
||||||
|
match_id = of_match_node(spm_match_table, pdev->dev.of_node);
|
||||||
|
if (!match_id)
|
||||||
|
return -ENODEV;
|
||||||
|
|
||||||
|
drv->reg_data = match_id->data;
|
||||||
|
|
||||||
|
/* Write the SPM sequences first.. */
|
||||||
|
addr = drv->reg_base + drv->reg_data->reg_offset[SPM_REG_SEQ_ENTRY];
|
||||||
|
__iowrite32_copy(addr, drv->reg_data->seq,
|
||||||
|
ARRAY_SIZE(drv->reg_data->seq) / 4);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* ..and then the control registers.
|
||||||
|
* On some SoC if the control registers are written first and if the
|
||||||
|
* CPU was held in reset, the reset signal could trigger the SPM state
|
||||||
|
* machine, before the sequences are completely written.
|
||||||
|
*/
|
||||||
|
spm_register_write(drv, SPM_REG_CFG, drv->reg_data->spm_cfg);
|
||||||
|
spm_register_write(drv, SPM_REG_DLY, drv->reg_data->spm_dly);
|
||||||
|
spm_register_write(drv, SPM_REG_PMIC_DLY, drv->reg_data->pmic_dly);
|
||||||
|
spm_register_write(drv, SPM_REG_PMIC_DATA_0,
|
||||||
|
drv->reg_data->pmic_data[0]);
|
||||||
|
spm_register_write(drv, SPM_REG_PMIC_DATA_1,
|
||||||
|
drv->reg_data->pmic_data[1]);
|
||||||
|
|
||||||
|
/* Set up Standby as the default low power mode */
|
||||||
|
spm_set_low_power_mode(drv, PM_SLEEP_MODE_STBY);
|
||||||
|
|
||||||
|
per_cpu(cpu_spm_drv, cpu) = drv;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static struct platform_driver spm_driver = {
|
||||||
|
.probe = spm_dev_probe,
|
||||||
|
.driver = {
|
||||||
|
.name = "saw",
|
||||||
|
.of_match_table = spm_match_table,
|
||||||
|
},
|
||||||
|
};
|
||||||
|
module_platform_driver(spm_driver);
|
||||||
|
|
||||||
|
MODULE_LICENSE("GPL v2");
|
||||||
|
MODULE_DESCRIPTION("SAW power controller driver");
|
||||||
|
MODULE_ALIAS("platform:saw");
|
||||||
|
|
@ -1,4 +1,4 @@
|
||||||
/* Copyright (c) 2010-2014, The Linux Foundation. All rights reserved.
|
/* Copyright (c) 2010-2015, The Linux Foundation. All rights reserved.
|
||||||
* Copyright (C) 2015 Linaro Ltd.
|
* Copyright (C) 2015 Linaro Ltd.
|
||||||
*
|
*
|
||||||
* This program is free software; you can redistribute it and/or modify
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
|
@ -16,6 +16,17 @@
|
||||||
extern int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus);
|
extern int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus);
|
||||||
extern int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus);
|
extern int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus);
|
||||||
|
|
||||||
|
#define QCOM_SCM_HDCP_MAX_REQ_CNT 5
|
||||||
|
|
||||||
|
struct qcom_scm_hdcp_req {
|
||||||
|
u32 addr;
|
||||||
|
u32 val;
|
||||||
|
};
|
||||||
|
|
||||||
|
extern bool qcom_scm_hdcp_available(void);
|
||||||
|
extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
|
||||||
|
u32 *resp);
|
||||||
|
|
||||||
#define QCOM_SCM_CPU_PWR_DOWN_L2_ON 0x0
|
#define QCOM_SCM_CPU_PWR_DOWN_L2_ON 0x0
|
||||||
#define QCOM_SCM_CPU_PWR_DOWN_L2_OFF 0x1
|
#define QCOM_SCM_CPU_PWR_DOWN_L2_OFF 0x1
|
||||||
|
|
||||||
|
|
|
||||||
Loading…
Add table
Reference in a new issue