drm/msm: Remember the state of A5XX hardware clock gating
Remember if the A5XX hardware clock gating is currently enabled or disabled to avoid inadvertently enabling it. Change-Id: Ic0dedbada3734a257ac966c041d06695f3521ad4 Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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2 changed files with 7 additions and 0 deletions
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@ -375,6 +375,7 @@ static const struct {
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void a5xx_set_hwcg(struct msm_gpu *gpu, bool state)
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{
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu);
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unsigned int i;
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for (i = 0; i < ARRAY_SIZE(a5xx_hwcg); i++)
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@ -391,6 +392,11 @@ void a5xx_set_hwcg(struct msm_gpu *gpu, bool state)
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gpu_write(gpu, REG_A5XX_RBBM_CLOCK_CNTL, state ? 0xAAA8AA00 : 0);
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gpu_write(gpu, REG_A5XX_RBBM_ISDB_CNT, state ? 0x182 : 0x180);
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if (state)
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set_bit(A5XX_HWCG_ENABLED, &a5xx_gpu->flags);
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else
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clear_bit(A5XX_HWCG_ENABLED, &a5xx_gpu->flags);
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}
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static int a5xx_me_init(struct msm_gpu *gpu)
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@ -23,6 +23,7 @@
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enum {
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A5XX_ZAP_SHADER_LOADED = 1,
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A5XX_HWCG_ENABLED = 2,
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};
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struct a5xx_gpu {
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