From a14e4b541bd5244c6268b7c81293f97d2a122c21 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Fri, 2 Dec 2016 11:38:27 +0530 Subject: [PATCH] clk: qcom: Add additional delay while enabling votable clocks During the GDSC enable sequence, the GDS_HW_CTRL forces some clocks to be on to trigger the handshake to unhalt the SMMU and NOC. Once the handshake completes, the controller asserts the PWR_ON status and disables the clocks. If the clock driver tries enabling the SMMU ahb/axi clocks immediately, there is a possibility that these clocks might still not have gone through their disable sequence; especially if the AXI/AHB rates are very low. If this happens, the clock driver falsely assumes that the clocks are on and returns. Any SMMU accesses/traffic at this point might lead to a failure since the clock could turn off. Change-Id: I544ca82e20e1c026d0ff1881c96edd33bf362b7d Signed-off-by: Taniya Das --- drivers/clk/qcom/clk-branch.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/clk/qcom/clk-branch.c b/drivers/clk/qcom/clk-branch.c index ec3d02e8dcb1..cffaf46d732f 100644 --- a/drivers/clk/qcom/clk-branch.c +++ b/drivers/clk/qcom/clk-branch.c @@ -83,6 +83,15 @@ static int clk_branch_wait(const struct clk_branch *br, bool enabling, if (clk_branch_in_hwcg_mode(br)) return 0; + /* + * Some of the BRANCH_VOTED clocks could be controlled by other + * masters via voting registers, and would require to add delay + * polling for the status bit to allow previous clk_disable + * by the GDS controller to go through. + */ + if (enabling && voted) + udelay(5); + if (br->halt_check == BRANCH_HALT_DELAY || (!enabling && voted)) { udelay(10); } else if (br->halt_check == BRANCH_HALT_ENABLE ||