clk: msm: mdss: fix DSI PLL post vco divider configuration
The post vco divider clock in the DSI PLL can only be configured to a fixed value of 1 or 4. Current implementation can result in the divider being set to any value between 1 and 4 which can result in failures while enabling the DSI pixel clock. Fix this by replacing the post vco divider with a fixed /1 and /4 dividers followed by a mux clock. CRs-Fixed: 1064277 Change-Id: I01bc7304e446c622849c678c64a3fd6881413e89 Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
This commit is contained in:
Aravind Venkateswaran
parent
773f15cdab
commit
a17f1f9338
2 changed files with 103 additions and 27 deletions
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@ -1016,19 +1016,19 @@ static struct clk_mux_ops mdss_mux_ops = {
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* | vco_clk |
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* +-------+-------+
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* |
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* +--------------------------------------+
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* | |
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* +-------v-------+ |
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* | bitclk_src | |
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* | DIV(1..15) | |
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* +-------+-------+ |
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* | |
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* +--------------------+ |
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* Shadow Path | | |
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* + +-------v-------+ +------v------+ +------v-------+
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* | | byteclk_src | |post_bit_div | |post_vco_div |
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* | | DIV(8) | |DIV(1,2) | |DIV(1,4) |
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* | +-------+-------+ +------+------+ +------+-------+
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* +----------------------+------------------+
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* | | |
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* +-------v-------+ +-------v-------+ +-------v-------+
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* | bitclk_src | | post_vco_div1 | | post_vco_div4 |
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* | DIV(1..15) | +-------+-------+ +-------+-------+
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* +-------+-------+ | |
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* | +------------+ |
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* +--------------------+ | |
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* Shadow Path | | | |
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* + +-------v-------+ +------v------+ +---v-----v------+
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* | | byteclk_src | |post_bit_div | \ post_vco_mux /
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* | | DIV(8) | |DIV(1,2) | \ /
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* | +-------+-------+ +------+------+ +---+------+
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* | | | |
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* | | +------+ +----+
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* | +--------+ | |
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@ -1085,19 +1085,51 @@ static struct div_clk dsi0pll_bitclk_src = {
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}
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};
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static struct div_clk dsi0pll_post_vco_div = {
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static struct div_clk dsi0pll_post_vco_div1 = {
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.data = {
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.div = 1,
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.min_div = 1,
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.max_div = 1,
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},
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.ops = &clk_post_vco_div_ops,
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.c = {
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.parent = &dsi0pll_vco_clk.c,
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.dbg_name = "dsi0pll_post_vco_div1",
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.ops = &clk_ops_post_vco_div_c,
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.flags = CLKFLAG_NO_RATE_CACHE,
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CLK_INIT(dsi0pll_post_vco_div1.c),
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}
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};
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static struct div_clk dsi0pll_post_vco_div4 = {
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.data = {
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.div = 4,
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.min_div = 4,
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.max_div = 4,
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},
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.ops = &clk_post_vco_div_ops,
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.c = {
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.parent = &dsi0pll_vco_clk.c,
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.dbg_name = "dsi0pll_post_vco_div",
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.dbg_name = "dsi0pll_post_vco_div4",
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.ops = &clk_ops_post_vco_div_c,
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.flags = CLKFLAG_NO_RATE_CACHE,
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CLK_INIT(dsi0pll_post_vco_div.c),
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CLK_INIT(dsi0pll_post_vco_div4.c),
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}
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};
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static struct mux_clk dsi0pll_post_vco_mux = {
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.num_parents = 2,
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.parents = (struct clk_src[]) {
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{&dsi0pll_post_vco_div1.c, 0},
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{&dsi0pll_post_vco_div4.c, 1},
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},
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.ops = &mdss_mux_ops,
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.c = {
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.parent = &dsi0pll_post_vco_div1.c,
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.dbg_name = "dsi0pll_post_vco_mux",
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.ops = &clk_ops_gen_mux,
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.flags = CLKFLAG_NO_RATE_CACHE,
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CLK_INIT(dsi0pll_post_vco_mux.c),
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}
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};
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@ -1121,7 +1153,7 @@ static struct mux_clk dsi0pll_pclk_src_mux = {
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.num_parents = 2,
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.parents = (struct clk_src[]) {
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{&dsi0pll_post_bit_div.c, 0},
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{&dsi0pll_post_vco_div.c, 1},
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{&dsi0pll_post_vco_mux.c, 1},
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},
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.ops = &mdss_mux_ops,
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.c = {
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@ -1222,19 +1254,51 @@ static struct div_clk dsi1pll_bitclk_src = {
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}
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};
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static struct div_clk dsi1pll_post_vco_div = {
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static struct div_clk dsi1pll_post_vco_div1 = {
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.data = {
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.div = 1,
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.min_div = 1,
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.max_div = 1,
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},
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.ops = &clk_post_vco_div_ops,
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.c = {
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.parent = &dsi1pll_vco_clk.c,
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.dbg_name = "dsi1pll_post_vco_div1",
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.ops = &clk_ops_post_vco_div_c,
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.flags = CLKFLAG_NO_RATE_CACHE,
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CLK_INIT(dsi1pll_post_vco_div1.c),
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}
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};
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static struct div_clk dsi1pll_post_vco_div4 = {
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.data = {
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.div = 4,
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.min_div = 4,
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.max_div = 4,
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},
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.ops = &clk_post_vco_div_ops,
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.c = {
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.parent = &dsi1pll_vco_clk.c,
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.dbg_name = "dsi1pll_post_vco_div",
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.dbg_name = "dsi1pll_post_vco_div4",
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.ops = &clk_ops_post_vco_div_c,
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.flags = CLKFLAG_NO_RATE_CACHE,
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CLK_INIT(dsi1pll_post_vco_div.c),
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CLK_INIT(dsi1pll_post_vco_div4.c),
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}
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};
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static struct mux_clk dsi1pll_post_vco_mux = {
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.num_parents = 2,
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.parents = (struct clk_src[]) {
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{&dsi1pll_post_vco_div1.c, 0},
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{&dsi1pll_post_vco_div4.c, 1},
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},
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.ops = &mdss_mux_ops,
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.c = {
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.parent = &dsi1pll_post_vco_div1.c,
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.dbg_name = "dsi1pll_post_vco_mux",
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.ops = &clk_ops_gen_mux,
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.flags = CLKFLAG_NO_RATE_CACHE,
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CLK_INIT(dsi1pll_post_vco_mux.c),
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}
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};
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@ -1258,7 +1322,7 @@ static struct mux_clk dsi1pll_pclk_src_mux = {
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.num_parents = 2,
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.parents = (struct clk_src[]) {
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{&dsi1pll_post_bit_div.c, 0},
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{&dsi1pll_post_vco_div.c, 1},
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{&dsi1pll_post_vco_mux.c, 1},
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},
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.ops = &mdss_mux_ops,
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.c = {
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@ -1338,7 +1402,9 @@ static struct clk_lookup mdss_dsi_pll0cc_cobalt[] = {
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CLK_LIST(dsi0pll_pclk_src),
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CLK_LIST(dsi0pll_pclk_src_mux),
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CLK_LIST(dsi0pll_post_bit_div),
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CLK_LIST(dsi0pll_post_vco_div),
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CLK_LIST(dsi0pll_post_vco_mux),
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CLK_LIST(dsi0pll_post_vco_div1),
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CLK_LIST(dsi0pll_post_vco_div4),
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CLK_LIST(dsi0pll_bitclk_src),
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CLK_LIST(dsi0pll_vco_clk),
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};
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@ -1349,7 +1415,9 @@ static struct clk_lookup mdss_dsi_pll1cc_cobalt[] = {
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CLK_LIST(dsi1pll_pclk_src),
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CLK_LIST(dsi1pll_pclk_src_mux),
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CLK_LIST(dsi1pll_post_bit_div),
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CLK_LIST(dsi1pll_post_vco_div),
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CLK_LIST(dsi1pll_post_vco_mux),
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CLK_LIST(dsi1pll_post_vco_div1),
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CLK_LIST(dsi1pll_post_vco_div4),
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CLK_LIST(dsi1pll_bitclk_src),
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CLK_LIST(dsi1pll_vco_clk),
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};
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@ -1407,7 +1475,9 @@ int dsi_pll_clock_register_cobalt(struct platform_device *pdev,
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dsi0pll_pclk_src.priv = pll_res;
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dsi0pll_pclk_src_mux.priv = pll_res;
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dsi0pll_post_bit_div.priv = pll_res;
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dsi0pll_post_vco_div.priv = pll_res;
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dsi0pll_post_vco_mux.priv = pll_res;
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dsi0pll_post_vco_div1.priv = pll_res;
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dsi0pll_post_vco_div4.priv = pll_res;
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dsi0pll_bitclk_src.priv = pll_res;
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dsi0pll_vco_clk.priv = pll_res;
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@ -1421,7 +1491,9 @@ int dsi_pll_clock_register_cobalt(struct platform_device *pdev,
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dsi1pll_pclk_src.priv = pll_res;
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dsi1pll_pclk_src_mux.priv = pll_res;
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dsi1pll_post_bit_div.priv = pll_res;
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dsi1pll_post_vco_div.priv = pll_res;
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dsi1pll_post_vco_mux.priv = pll_res;
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dsi1pll_post_vco_div1.priv = pll_res;
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dsi1pll_post_vco_div4.priv = pll_res;
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dsi1pll_bitclk_src.priv = pll_res;
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dsi1pll_vco_clk.priv = pll_res;
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@ -447,7 +447,9 @@
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#define clk_dsi0pll_pclk_src 0x5efd85d4
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#define clk_dsi0pll_pclk_src_mux 0x84b14663
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#define clk_dsi0pll_post_bit_div 0xf46dcf27
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#define clk_dsi0pll_post_vco_div 0x8ee956ff
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#define clk_dsi0pll_post_vco_mux 0xfaf9bd1f
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#define clk_dsi0pll_post_vco_div1 0xabb50b2a
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#define clk_dsi0pll_post_vco_div4 0xbe51c091
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#define clk_dsi0pll_bitclk_src 0x36c3c437
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#define clk_dsi0pll_vco_clk 0x15940d40
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@ -457,7 +459,9 @@
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#define clk_dsi1pll_pclk_src 0xeddcd80e
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#define clk_dsi1pll_pclk_src_mux 0x3651feb3
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#define clk_dsi1pll_post_bit_div 0x712f0260
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#define clk_dsi1pll_post_vco_div 0x623e04de
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#define clk_dsi1pll_post_vco_mux 0xc6a90d20
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#define clk_dsi1pll_post_vco_div1 0x6f47ca7d
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#define clk_dsi1pll_post_vco_div4 0x90628974
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#define clk_dsi1pll_bitclk_src 0x13ab045b
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#define clk_dsi1pll_vco_clk 0x99797b50
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