From a2434b9ba0136ceb1ac189b2acbe2dbae0e633dc Mon Sep 17 00:00:00 2001 From: Rajesh Kemisetti Date: Sun, 15 Jan 2017 15:07:48 +0530 Subject: [PATCH] ARM: dts: msm: Vote for BIMC GFX clock for SDM660 GPU Enable BIMC GFX clock when A512 GPU is ready to access data from DDR on SDM660. Change-Id: Ib76ef7a4fd5362f8cb972f1e4e070157a59c2c27 Signed-off-by: Rajesh Kemisetti --- arch/arm/boot/dts/qcom/sdm660-gpu.dtsi | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/qcom/sdm660-gpu.dtsi b/arch/arm/boot/dts/qcom/sdm660-gpu.dtsi index e3a3835ae809..d347f033b12d 100644 --- a/arch/arm/boot/dts/qcom/sdm660-gpu.dtsi +++ b/arch/arm/boot/dts/qcom/sdm660-gpu.dtsi @@ -65,6 +65,7 @@ /* */ qcom,idle-timeout = <80>; + qcom,no-nap; qcom,highest-bank-bit = <14>; @@ -75,11 +76,11 @@ <&clock_gcc GCC_GPU_CFG_AHB_CLK>, <&clock_gfx GPUCC_RBBMTIMER_CLK>, <&clock_gcc GCC_GPU_BIMC_GFX_CLK>, - <&clock_gcc GCC_GPU_BIMC_GFX_SRC_CLK>, + <&clock_gcc GCC_BIMC_GFX_CLK>, <&clock_gpu GPUCC_RBCPR_CLK>; clock-names = "core_clk", "iface_clk", "rbbmtimer_clk", - "mem_clk", "mem_iface_clk", "rbcpr_clk"; + "mem_clk", "alt_mem_iface_clk", "rbcpr_clk"; /* Bus Scale Settings */ qcom,gpubw-dev = <&gpubw>; @@ -248,9 +249,9 @@ clocks =<&clock_gcc GCC_GPU_CFG_AHB_CLK>, <&clock_gcc GCC_GPU_BIMC_GFX_CLK>, - <&clock_gcc GCC_GPU_BIMC_GFX_SRC_CLK>; + <&clock_gcc GCC_BIMC_GFX_CLK>; - clock-names = "iface_clk", "mem_clk", "mem_iface_clk"; + clock-names = "iface_clk", "mem_clk", "alt_mem_iface_clk"; qcom,secure_align_mask = <0xfff>; qcom,retention;