ARM: dts: msm: Update SDCC bus voting for SDM660

SDM660 target has a dual DDR channel of width 16 bits.
Update DDR bus bandwidth voting considering per channel
voting and update CNOC bus voting to support LOW_SVS
(i.e freq 33.33 MHz) considering bus width of 4 bytes.

Change-Id: Iff0a40016f58c82d0823fd0c1968f1af6978f68c
Signed-off-by: Sayali Lokhande <sayalil@codeaurora.org>
This commit is contained in:
Sayali Lokhande 2017-03-14 12:09:20 +05:30
parent 687a4eb82b
commit a2bc826fed
2 changed files with 56 additions and 56 deletions

View file

@ -479,26 +479,26 @@
/* No vote */ /* No vote */
<78 512 0 0>, <1 606 0 0>, <78 512 0 0>, <1 606 0 0>,
/* 400 KB/s*/ /* 400 KB/s*/
<78 512 1046 3200>, <78 512 1046 1600>,
<1 606 1046 3200>, <1 606 1600 1600>,
/* 20 MB/s */ /* 20 MB/s */
<78 512 52286 160000>, <78 512 52286 80000>,
<1 606 52286 160000>, <1 606 80000 80000>,
/* 25 MB/s */ /* 25 MB/s */
<78 512 65360 200000>, <78 512 65360 100000>,
<1 606 65360 200000>, <1 606 100000 100000>,
/* 50 MB/s */ /* 50 MB/s */
<78 512 130718 400000>, <78 512 130718 200000>,
<1 606 130718 400000>, <1 606 133320 133320>,
/* 100 MB/s */ /* 100 MB/s */
<78 512 130718 400000>, <78 512 130718 200000>,
<1 606 130718 400000>, <1 606 150000 150000>,
/* 200 MB/s */ /* 200 MB/s */
<78 512 261438 800000>, <78 512 261438 400000>,
<1 606 261438 800000>, <1 606 300000 300000>,
/* 400 MB/s */ /* 400 MB/s */
<78 512 261438 800000>, <78 512 261438 400000>,
<1 606 261438 800000>, <1 606 300000 300000>,
/* Max. bandwidth */ /* Max. bandwidth */
<78 512 1338562 4096000>, <78 512 1338562 4096000>,
<1 606 1338562 4096000>; <1 606 1338562 4096000>;
@ -516,7 +516,7 @@
qcom,nonremovable; qcom,nonremovable;
qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v"; qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v";
qcom,ice-clk-rates = <300000000 150000000>; qcom,ice-clk-rates = <300000000 75000000>;
status = "disabled"; status = "disabled";
}; };
@ -538,24 +538,24 @@
qcom,msm-bus,vectors-KBps = qcom,msm-bus,vectors-KBps =
/* No vote */ /* No vote */
<81 512 0 0>, <1 608 0 0>, <81 512 0 0>, <1 608 0 0>,
/* 400 KB/s */ /* 400 KB/s*/
<81 512 1046 3200>, <81 512 1046 1600>,
<1 608 1046 3200>, <1 608 1600 1600>,
/* 20 MB/s */ /* 20 MB/s */
<81 512 52286 160000>, <81 512 52286 80000>,
<1 608 52286 160000>, <1 608 80000 80000>,
/* 25 MB/s */ /* 25 MB/s */
<81 512 65360 200000>, <81 512 65360 100000>,
<1 608 65360 200000>, <1 608 100000 100000>,
/* 50 MB/s */ /* 50 MB/s */
<81 512 130718 400000>, <81 512 130718 200000>,
<1 608 130718 400000>, <1 608 133320 133320>,
/* 100 MB/s */ /* 100 MB/s */
<81 512 261438 800000>, <81 512 261438 200000>,
<1 608 261438 800000>, <1 608 150000 150000>,
/* 200 MB/s */ /* 200 MB/s */
<81 512 261438 800000>, <81 512 261438 400000>,
<1 608 261438 800000>, <1 608 300000 300000>,
/* Max. bandwidth */ /* Max. bandwidth */
<81 512 1338562 4096000>, <81 512 1338562 4096000>,
<1 608 1338562 4096000>; <1 608 1338562 4096000>;

View file

@ -1339,26 +1339,26 @@
/* No vote */ /* No vote */
<78 512 0 0>, <1 606 0 0>, <78 512 0 0>, <1 606 0 0>,
/* 400 KB/s*/ /* 400 KB/s*/
<78 512 1046 3200>, <78 512 1046 1600>,
<1 606 1046 3200>, <1 606 1600 1600>,
/* 20 MB/s */ /* 20 MB/s */
<78 512 52286 160000>, <78 512 52286 80000>,
<1 606 52286 160000>, <1 606 80000 80000>,
/* 25 MB/s */ /* 25 MB/s */
<78 512 65360 200000>, <78 512 65360 100000>,
<1 606 65360 200000>, <1 606 100000 100000>,
/* 50 MB/s */ /* 50 MB/s */
<78 512 130718 400000>, <78 512 130718 200000>,
<1 606 130718 400000>, <1 606 133320 133320>,
/* 100 MB/s */ /* 100 MB/s */
<78 512 130718 400000>, <78 512 130718 200000>,
<1 606 130718 400000>, <1 606 150000 150000>,
/* 200 MB/s */ /* 200 MB/s */
<78 512 261438 800000>, <78 512 261438 400000>,
<1 606 261438 800000>, <1 606 300000 300000>,
/* 400 MB/s */ /* 400 MB/s */
<78 512 261438 800000>, <78 512 261438 400000>,
<1 606 261438 800000>, <1 606 300000 300000>,
/* Max. bandwidth */ /* Max. bandwidth */
<78 512 1338562 4096000>, <78 512 1338562 4096000>,
<1 606 1338562 4096000>; <1 606 1338562 4096000>;
@ -1369,7 +1369,7 @@
<&clock_gcc GCC_SDCC1_APPS_CLK>, <&clock_gcc GCC_SDCC1_APPS_CLK>,
<&clock_gcc GCC_SDCC1_ICE_CORE_CLK>; <&clock_gcc GCC_SDCC1_ICE_CORE_CLK>;
clock-names = "iface_clk", "core_clk", "ice_core_clk"; clock-names = "iface_clk", "core_clk", "ice_core_clk";
qcom,ice-clk-rates = <300000000 150000000>; qcom,ice-clk-rates = <300000000 75000000>;
status = "disabled"; status = "disabled";
}; };
@ -1391,24 +1391,24 @@
qcom,msm-bus,vectors-KBps = qcom,msm-bus,vectors-KBps =
/* No vote */ /* No vote */
<81 512 0 0>, <1 608 0 0>, <81 512 0 0>, <1 608 0 0>,
/* 400 KB/s */ /* 400 KB/s*/
<81 512 1046 3200>, <81 512 1046 1600>,
<1 608 1046 3200>, <1 608 1600 1600>,
/* 20 MB/s */ /* 20 MB/s */
<81 512 52286 160000>, <81 512 52286 80000>,
<1 608 52286 160000>, <1 608 80000 80000>,
/* 25 MB/s */ /* 25 MB/s */
<81 512 65360 200000>, <81 512 65360 100000>,
<1 608 65360 200000>, <1 608 100000 100000>,
/* 50 MB/s */ /* 50 MB/s */
<81 512 130718 400000>, <81 512 130718 200000>,
<1 608 130718 400000>, <1 608 133320 133320>,
/* 100 MB/s */ /* 100 MB/s */
<81 512 261438 800000>, <81 512 261438 200000>,
<1 608 261438 800000>, <1 608 150000 150000>,
/* 200 MB/s */ /* 200 MB/s */
<81 512 261438 800000>, <81 512 261438 400000>,
<1 608 261438 800000>, <1 608 300000 300000>,
/* Max. bandwidth */ /* Max. bandwidth */
<81 512 1338562 4096000>, <81 512 1338562 4096000>,
<1 608 1338562 4096000>; <1 608 1338562 4096000>;