staging: comedi: ni_stc.h: tidy up AI_*_Load_[AB]_Registers
Rename the CamelCase. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Reviewed-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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2 changed files with 18 additions and 18 deletions
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@ -330,12 +330,12 @@ static const struct mio_regmap m_series_stc_write_regmap[] = {
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[NISTC_DIO_CTRL_REG] = { 0, 0 }, /* DOES NOT MAP CLEANLY */
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[NISTC_DIO_CTRL_REG] = { 0, 0 }, /* DOES NOT MAP CLEANLY */
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[NISTC_AI_MODE1_REG] = { 0x118, 2 },
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[NISTC_AI_MODE1_REG] = { 0x118, 2 },
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[NISTC_AI_MODE2_REG] = { 0x11a, 2 },
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[NISTC_AI_MODE2_REG] = { 0x11a, 2 },
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[AI_SI_Load_A_Registers] = { 0x11c, 4 },
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[NISTC_AI_SI_LOADA_REG] = { 0x11c, 4 },
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[AI_SI_Load_B_Registers] = { 0x120, 4 },
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[NISTC_AI_SI_LOADB_REG] = { 0x120, 4 },
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[AI_SC_Load_A_Registers] = { 0x124, 4 },
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[NISTC_AI_SC_LOADA_REG] = { 0x124, 4 },
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[AI_SC_Load_B_Registers] = { 0x128, 4 },
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[NISTC_AI_SC_LOADB_REG] = { 0x128, 4 },
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[AI_SI2_Load_A_Register] = { 0x12c, 4 },
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[NISTC_AI_SI2_LOADA_REG] = { 0x12c, 4 },
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[AI_SI2_Load_B_Register] = { 0x130, 4 },
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[NISTC_AI_SI2_LOADB_REG] = { 0x130, 4 },
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[G_Mode_Register(0)] = { 0x134, 2 },
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[G_Mode_Register(0)] = { 0x134, 2 },
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[G_Mode_Register(1)] = { 0x136, 2 },
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[G_Mode_Register(1)] = { 0x136, 2 },
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[G_Load_A_Register(0)] = { 0x138, 4 },
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[G_Load_A_Register(0)] = { 0x138, 4 },
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@ -2337,7 +2337,7 @@ static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
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stop_count += num_adc_stages_611x;
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stop_count += num_adc_stages_611x;
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}
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}
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/* stage number of scans */
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/* stage number of scans */
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ni_stc_writel(dev, stop_count, AI_SC_Load_A_Registers);
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ni_stc_writel(dev, stop_count, NISTC_AI_SC_LOADA_REG);
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mode1 |= NISTC_AI_MODE1_START_STOP |
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mode1 |= NISTC_AI_MODE1_START_STOP |
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NISTC_AI_MODE1_RSVD |
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NISTC_AI_MODE1_RSVD |
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@ -2357,7 +2357,7 @@ static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
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break;
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break;
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case TRIG_NONE:
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case TRIG_NONE:
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/* stage number of scans */
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/* stage number of scans */
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ni_stc_writel(dev, 0, AI_SC_Load_A_Registers);
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ni_stc_writel(dev, 0, NISTC_AI_SC_LOADA_REG);
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mode1 |= NISTC_AI_MODE1_START_STOP |
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mode1 |= NISTC_AI_MODE1_START_STOP |
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NISTC_AI_MODE1_RSVD |
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NISTC_AI_MODE1_RSVD |
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@ -2397,7 +2397,7 @@ static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
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/* load SI */
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/* load SI */
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timer = ni_ns_to_timer(dev, cmd->scan_begin_arg,
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timer = ni_ns_to_timer(dev, cmd->scan_begin_arg,
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CMDF_ROUND_NEAREST);
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CMDF_ROUND_NEAREST);
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ni_stc_writel(dev, timer, AI_SI_Load_A_Registers);
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ni_stc_writel(dev, timer, NISTC_AI_SI_LOADA_REG);
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ni_stc_writew(dev, NISTC_AI_CMD1_SI_LOAD, NISTC_AI_CMD1_REG);
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ni_stc_writew(dev, NISTC_AI_CMD1_SI_LOAD, NISTC_AI_CMD1_REG);
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break;
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break;
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case TRIG_EXT:
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case TRIG_EXT:
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@ -2426,8 +2426,8 @@ static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
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timer = ni_ns_to_timer(dev, cmd->convert_arg,
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timer = ni_ns_to_timer(dev, cmd->convert_arg,
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CMDF_ROUND_NEAREST);
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CMDF_ROUND_NEAREST);
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/* 0,0 does not work */
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/* 0,0 does not work */
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ni_stc_writew(dev, 1, AI_SI2_Load_A_Register);
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ni_stc_writew(dev, 1, NISTC_AI_SI2_LOADA_REG);
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ni_stc_writew(dev, timer, AI_SI2_Load_B_Register);
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ni_stc_writew(dev, timer, NISTC_AI_SI2_LOADB_REG);
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mode2 &= ~NISTC_AI_MODE2_SI2_INIT_LOAD_SRC; /* A */
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mode2 &= ~NISTC_AI_MODE2_SI2_INIT_LOAD_SRC; /* A */
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mode2 |= NISTC_AI_MODE2_SI2_RELOAD_MODE; /* alternate */
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mode2 |= NISTC_AI_MODE2_SI2_RELOAD_MODE; /* alternate */
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@ -204,6 +204,13 @@
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#define NISTC_AI_MODE2_SC_RELOAD_MODE BIT(1)
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#define NISTC_AI_MODE2_SC_RELOAD_MODE BIT(1)
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#define NISTC_AI_MODE2_SC_WR_SWITCH BIT(0)
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#define NISTC_AI_MODE2_SC_WR_SWITCH BIT(0)
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#define NISTC_AI_SI_LOADA_REG 14
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#define NISTC_AI_SI_LOADB_REG 16
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#define NISTC_AI_SC_LOADA_REG 18
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#define NISTC_AI_SC_LOADB_REG 20
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#define NISTC_AI_SI2_LOADA_REG 23
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#define NISTC_AI_SI2_LOADB_REG 25
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#define AI_Status_1_Register 2
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#define AI_Status_1_Register 2
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#define Interrupt_A_St 0x8000
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#define Interrupt_A_St 0x8000
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#define AI_FIFO_Full_St 0x4000
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#define AI_FIFO_Full_St 0x4000
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@ -246,16 +253,9 @@
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#define DIO_Parallel_Input_Register 7
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#define DIO_Parallel_Input_Register 7
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#define AI_SI_Load_A_Registers 14
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#define AI_SI_Load_B_Registers 16
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#define AI_SC_Load_A_Registers 18
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#define AI_SC_Load_B_Registers 20
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#define AI_SI_Save_Registers 64
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#define AI_SI_Save_Registers 64
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#define AI_SC_Save_Registers 66
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#define AI_SC_Save_Registers 66
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#define AI_SI2_Load_A_Register 23
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#define AI_SI2_Load_B_Register 25
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#define Joint_Status_1_Register 27
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#define Joint_Status_1_Register 27
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#define DIO_Serial_IO_In_Progress_St _bit12
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#define DIO_Serial_IO_In_Progress_St _bit12
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