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scsi: ufshcd: reduce clock scaling polling time window

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Clock scaling polling time window is currently 100ms which is more than
the clock gating time which is 50ms and during clock gating, clock scaling
logic would be disabled. This may make the clocks to remain scaled down
for longer period of time, fix this by reducing the clock scaling polling
window less than clock gating timeout.

Change-Id: I8365470c7a6bd4950c1decbd418272359475c366
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
This commit is contained in:
Subhash Jadavani 2015-03-04 12:02:57 -08:00 • committed by David Keitel
parent 14e40e8800
commit a5711f5c0d
1 changed files with 1 additions and 1 deletions
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drivers/scsi/ufs/ufshcd.c
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@ -8605,7 +8605,7 @@ static void *gov_data;
#endif
static struct devfreq_dev_profile ufs_devfreq_profile = {
.polling_ms = 100,
.polling_ms = 40,
.target = ufshcd_devfreq_target,
.get_dev_status = ufshcd_devfreq_get_dev_status,
};