arm64: errata: Enable #845719 Errataum for Kryo2xx Silver
Errata#845719 is also applicable for Kryo2xx Silver. Enable the appropriate entry for it with rAp4 revision. Please note that default midr_range logic depends on the less or greather than logic with "min" and "max" range, assuming that rX where X will be zero only. This is not true for all the processors and since it is 4-bit field it can be greater than the the "max" or pY bits. We are specifying the direct match values like 0xA00004 instead here to keep the logic consistent. CRs-Fixed: 969563 Change-Id: I16b0c2106ae649b8a23b7ebb534c967aebd72774 Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
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@ -24,6 +24,8 @@
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#define MIDR_CORTEX_A53 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
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#define MIDR_CORTEX_A57 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
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#define MIDR_THUNDERX MIDR_CPU_PART(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
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#define MIDR_KRYO2XX_SILVER \
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MIDR_CPU_PART(ARM_CPU_IMP_QCOM, ARM_CPU_PART_KRYO2XX_SILVER)
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#define CPU_MODEL_MASK (MIDR_IMPLEMENTOR_MASK | MIDR_PARTNUM_MASK | \
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MIDR_ARCHITECTURE_MASK)
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@ -91,6 +93,12 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
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.capability = ARM64_WORKAROUND_845719,
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MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x04),
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},
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{
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/* Kryo2xx Silver rAp4 */
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.desc = "Kryo2xx Silver erratum 845719",
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.capability = ARM64_WORKAROUND_845719,
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MIDR_RANGE(MIDR_KRYO2XX_SILVER, 0xA00004, 0xA00004),
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},
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#endif
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#ifdef CONFIG_CAVIUM_ERRATUM_23154
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{
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