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arm64: errata: Enable #845719 Errataum for Kryo2xx Silver

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Errata#845719 is also applicable for Kryo2xx Silver. Enable
the appropriate entry for it with rAp4 revision.

Please note that default midr_range logic depends on the
less or greather than logic with "min" and "max" range,
assuming that rX where X will be zero only. This is not
true for all the processors and since it is 4-bit field
it can be greater than the the "max" or pY bits.

We are specifying the direct match values like
0xA00004 instead here to keep the logic consistent.

CRs-Fixed: 969563
Change-Id: I16b0c2106ae649b8a23b7ebb534c967aebd72774
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
This commit is contained in:
Trilok Soni 2016-01-27 18:23:25 -08:00 • committed by Jeevan Shriram
parent c42e1feb92
commit a63df78642
1 changed files with 8 additions and 0 deletions
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8
arch/arm64/kernel/cpu_errata.c
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@ -24,6 +24,8 @@
#define MIDR_CORTEX_A53 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53) #define MIDR_CORTEX_A53 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
#define MIDR_CORTEX_A57 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57) #define MIDR_CORTEX_A57 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
#define MIDR_THUNDERX MIDR_CPU_PART(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) #define MIDR_THUNDERX MIDR_CPU_PART(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
#define MIDR_KRYO2XX_SILVER \
MIDR_CPU_PART(ARM_CPU_IMP_QCOM, ARM_CPU_PART_KRYO2XX_SILVER)
#define CPU_MODEL_MASK (MIDR_IMPLEMENTOR_MASK | MIDR_PARTNUM_MASK | \ #define CPU_MODEL_MASK (MIDR_IMPLEMENTOR_MASK | MIDR_PARTNUM_MASK | \
MIDR_ARCHITECTURE_MASK) MIDR_ARCHITECTURE_MASK)
@ -91,6 +93,12 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
.capability = ARM64_WORKAROUND_845719, .capability = ARM64_WORKAROUND_845719,
MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x04), MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x04),
}, },
{
/* Kryo2xx Silver rAp4 */
.desc = "Kryo2xx Silver erratum 845719",
.capability = ARM64_WORKAROUND_845719,
MIDR_RANGE(MIDR_KRYO2XX_SILVER, 0xA00004, 0xA00004),
},
#endif #endif
#ifdef CONFIG_CAVIUM_ERRATUM_23154 #ifdef CONFIG_CAVIUM_ERRATUM_23154
{ {