staging: comedi: adl_pci8164: simplify (*insn_{read,write})
The (*insn_read) and (*insn_write) functions for all the subdevices in this driver are the same except for the 'offset' that is added to the iobase and channel to read/write a register on the board. Pass the 'offset' in s->private so we can use the same (*insn_read) and (*insn->write) functions for all the subdevices. Also, fix the (*insn_read) and (*insn_write) functions so they work correctly. The comedi core expects them to read/write insn->n data values and then return the number of values used. For aesthetic reasons, add some whitespace to the subdevice init. Remove the dev_info() noise at the end of the attach. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Cc: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
H Hartley Sweeten
Greg Kroah-Hartman
parent
d99fc2c372
commit
a6c57d2ed7
1 changed files with 58 additions and 132 deletions
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@ -39,117 +39,41 @@ Configuration Options: not applicable, uses PCI auto config
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#include "8253.h"
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#define PCI8164_AXIS(x) ((x) * 0x08)
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#define PCI8164_MSTS 0x00
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#define PCI8164_SSTS 0x02
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#define PCI8164_BUF0 0x04
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#define PCI8164_BUF1 0x06
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#define PCI8164_CMD 0x00
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#define PCI8164_OTP 0x02
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#define PCI8164_CMD_MSTS_REG 0x00
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#define PCI8164_OTP_SSTS_REG 0x02
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#define PCI8164_BUF0_REG 0x04
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#define PCI8164_BUF1_REG 0x06
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#define PCI_DEVICE_ID_PCI8164 0x8164
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/*
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all the read commands are the same except for the addition a constant
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* const to the data for inw()
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*/
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static void adl_pci8164_insn_read(struct comedi_device *dev,
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struct comedi_subdevice *s,
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struct comedi_insn *insn,
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unsigned int *data,
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char *action, unsigned short offset)
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{
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unsigned int chan = CR_CHAN(insn->chanspec);
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data[0] = inw(dev->iobase + PCI8164_AXIS(chan) + offset);
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}
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static int adl_pci8164_insn_read_msts(struct comedi_device *dev,
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struct comedi_subdevice *s,
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struct comedi_insn *insn,
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unsigned int *data)
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{
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adl_pci8164_insn_read(dev, s, insn, data, "MSTS", PCI8164_MSTS);
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return 2;
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}
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static int adl_pci8164_insn_read_ssts(struct comedi_device *dev,
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struct comedi_subdevice *s,
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struct comedi_insn *insn,
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unsigned int *data)
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{
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adl_pci8164_insn_read(dev, s, insn, data, "SSTS", PCI8164_SSTS);
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return 2;
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}
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static int adl_pci8164_insn_read_buf0(struct comedi_device *dev,
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struct comedi_subdevice *s,
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struct comedi_insn *insn,
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unsigned int *data)
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{
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adl_pci8164_insn_read(dev, s, insn, data, "BUF0", PCI8164_BUF0);
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return 2;
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}
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static int adl_pci8164_insn_read_buf1(struct comedi_device *dev,
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struct comedi_subdevice *s,
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struct comedi_insn *insn,
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unsigned int *data)
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{
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adl_pci8164_insn_read(dev, s, insn, data, "BUF1", PCI8164_BUF1);
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return 2;
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}
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/*
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all the write commands are the same except for the addition a constant
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* const to the data for outw()
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*/
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static void adl_pci8164_insn_out(struct comedi_device *dev,
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static int adl_pci8164_insn_read(struct comedi_device *dev,
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struct comedi_subdevice *s,
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struct comedi_insn *insn,
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unsigned int *data,
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char *action, unsigned short offset)
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unsigned int *data)
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{
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unsigned long offset = (unsigned long)s->private;
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unsigned int chan = CR_CHAN(insn->chanspec);
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int i;
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outw(data[0], dev->iobase + PCI8164_AXIS(chan) + offset);
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for (i = 0; i < insn->n; i++)
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data[i] = inw(dev->iobase + PCI8164_AXIS(chan) + offset);
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return insn->n;
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}
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static int adl_pci8164_insn_write_cmd(struct comedi_device *dev,
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struct comedi_subdevice *s,
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struct comedi_insn *insn,
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unsigned int *data)
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static int adl_pci8164_insn_write(struct comedi_device *dev,
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struct comedi_subdevice *s,
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struct comedi_insn *insn,
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unsigned int *data)
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{
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adl_pci8164_insn_out(dev, s, insn, data, "CMD", PCI8164_CMD);
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return 2;
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}
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unsigned long offset = (unsigned long)s->private;
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unsigned int chan = CR_CHAN(insn->chanspec);
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int i;
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static int adl_pci8164_insn_write_otp(struct comedi_device *dev,
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struct comedi_subdevice *s,
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struct comedi_insn *insn,
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unsigned int *data)
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{
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adl_pci8164_insn_out(dev, s, insn, data, "OTP", PCI8164_OTP);
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return 2;
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}
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for (i = 0; i < insn->n; i++)
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outw(data[i], dev->iobase + PCI8164_AXIS(chan) + offset);
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static int adl_pci8164_insn_write_buf0(struct comedi_device *dev,
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struct comedi_subdevice *s,
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struct comedi_insn *insn,
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unsigned int *data)
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{
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adl_pci8164_insn_out(dev, s, insn, data, "BUF0", PCI8164_BUF0);
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return 2;
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}
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static int adl_pci8164_insn_write_buf1(struct comedi_device *dev,
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struct comedi_subdevice *s,
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struct comedi_insn *insn,
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unsigned int *data)
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{
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adl_pci8164_insn_out(dev, s, insn, data, "BUF1", PCI8164_BUF1);
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return 2;
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return insn->n;
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}
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static int adl_pci8164_auto_attach(struct comedi_device *dev,
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@ -170,47 +94,49 @@ static int adl_pci8164_auto_attach(struct comedi_device *dev,
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if (ret)
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return ret;
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/* read MSTS register / write CMD register for each axis (channel) */
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s = &dev->subdevices[0];
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s->type = COMEDI_SUBD_PROC;
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s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
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s->n_chan = 4;
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s->maxdata = 0xffff;
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s->len_chanlist = 4;
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/* s->range_table = &range_axis; */
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s->insn_read = adl_pci8164_insn_read_msts;
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s->insn_write = adl_pci8164_insn_write_cmd;
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s->type = COMEDI_SUBD_PROC;
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s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
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s->n_chan = 4;
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s->maxdata = 0xffff;
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s->len_chanlist = 4;
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s->insn_read = adl_pci8164_insn_read;
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s->insn_write = adl_pci8164_insn_write;
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s->private = (void *)PCI8164_CMD_MSTS_REG;
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/* read SSTS register / write OTP register for each axis (channel) */
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s = &dev->subdevices[1];
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s->type = COMEDI_SUBD_PROC;
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s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
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s->n_chan = 4;
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s->maxdata = 0xffff;
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s->len_chanlist = 4;
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/* s->range_table = &range_axis; */
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s->insn_read = adl_pci8164_insn_read_ssts;
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s->insn_write = adl_pci8164_insn_write_otp;
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s->type = COMEDI_SUBD_PROC;
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s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
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s->n_chan = 4;
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s->maxdata = 0xffff;
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s->len_chanlist = 4;
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s->insn_read = adl_pci8164_insn_read;
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s->insn_write = adl_pci8164_insn_write;
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s->private = (void *)PCI8164_OTP_SSTS_REG;
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/* read/write BUF0 register for each axis (channel) */
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s = &dev->subdevices[2];
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s->type = COMEDI_SUBD_PROC;
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s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
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s->n_chan = 4;
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s->maxdata = 0xffff;
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s->len_chanlist = 4;
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/* s->range_table = &range_axis; */
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s->insn_read = adl_pci8164_insn_read_buf0;
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s->insn_write = adl_pci8164_insn_write_buf0;
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s->type = COMEDI_SUBD_PROC;
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s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
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s->n_chan = 4;
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s->maxdata = 0xffff;
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s->len_chanlist = 4;
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s->insn_read = adl_pci8164_insn_read;
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s->insn_write = adl_pci8164_insn_write;
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s->private = (void *)PCI8164_BUF0_REG;
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/* read/write BUF1 register for each axis (channel) */
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s = &dev->subdevices[3];
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s->type = COMEDI_SUBD_PROC;
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s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
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s->n_chan = 4;
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s->maxdata = 0xffff;
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s->len_chanlist = 4;
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/* s->range_table = &range_axis; */
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s->insn_read = adl_pci8164_insn_read_buf1;
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s->insn_write = adl_pci8164_insn_write_buf1;
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dev_info(dev->class_dev, "%s attached\n", dev->board_name);
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s->type = COMEDI_SUBD_PROC;
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s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
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s->n_chan = 4;
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s->maxdata = 0xffff;
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s->len_chanlist = 4;
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s->insn_read = adl_pci8164_insn_read;
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s->insn_write = adl_pci8164_insn_write;
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s->private = (void *)PCI8164_BUF1_REG;
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return 0;
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}
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