From a7038394461fbc869a1f9015040aa475fd1fab8f Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Wed, 11 May 2016 17:51:00 -0700 Subject: [PATCH] msm: pcie: update misc register offsets on msmcobalt Some msmcobalt PCIe configuration registers have different offsets than other chipsets. Update these offsets so that PCIe can be correctly configured on msmcobalt. Change-Id: I42c7f545a48e6a431ccdba062399776e8c1c64f2 Signed-off-by: Tony Truong --- drivers/pci/host/pci-msm.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/pci/host/pci-msm.c b/drivers/pci/host/pci-msm.c index 4b62d466140f..c9c092dc4c5c 100644 --- a/drivers/pci/host/pci-msm.c +++ b/drivers/pci/host/pci-msm.c @@ -50,6 +50,7 @@ #define PCIE_VENDOR_ID_RCP 0x17cb #define PCIE_DEVICE_ID_RCP 0x0302 +#define PCIE20_L1SUB_CONTROL1 0x158 #define PCIE20_PARF_DBI_BASE_ADDR 0x350 #define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x358 @@ -62,6 +63,10 @@ #define PCIE_VENDOR_ID_RCP 0x17cb #define PCIE_DEVICE_ID_RCP 0x0105 +#define PCIE20_L1SUB_CONTROL1 0x1E4 +#define PCIE20_PARF_DBI_BASE_ADDR 0x350 +#define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x358 + #define TX_BASE 0 #define RX_BASE 0 #define PCS_BASE 0x800 @@ -71,6 +76,7 @@ #define PCIE_VENDOR_ID_RCP 0x17cb #define PCIE_DEVICE_ID_RCP 0x0104 +#define PCIE20_L1SUB_CONTROL1 0x158 #define PCIE20_PARF_DBI_BASE_ADDR 0x168 #define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16C @@ -234,7 +240,6 @@ #define PCIE20_BUSNUMBERS 0x18 #define PCIE20_MEMORY_BASE_LIMIT 0x20 #define PCIE20_BRIDGE_CTRL 0x3C -#define PCIE20_L1SUB_CONTROL1 0x158 #define PCIE20_DEVICE_CONTROL_STATUS 0x78 #define PCIE20_DEVICE_CONTROL2_STATUS2 0x98