PM / devfreq: Add Krait L2 cache HW monitor
This is a snapshot of the Krait L2 cache HW monitor driver as of msm-3.10 commit: acdce027751d5a7488b283f0ce3111f873a5816d (Merge "defconfig: arm64: Enable ONESHOT_SYNC for msm8994") Signed-off-by: Kumar Gala <galak@codeaurora.org>
This commit is contained in:
Kumar Gala
David Keitel
parent
413a953778
commit
a770f34aad
2 changed files with 447 additions and 0 deletions
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@ -5,6 +5,7 @@ obj-$(CONFIG_DEVFREQ_GOV_PERFORMANCE) += governor_performance.o
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obj-$(CONFIG_DEVFREQ_GOV_POWERSAVE) += governor_powersave.o
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obj-$(CONFIG_DEVFREQ_GOV_USERSPACE) += governor_userspace.o
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obj-$(CONFIG_DEVFREQ_GOV_QCOM_ADRENO_TZ) += governor_msm_adreno_tz.o
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obj-$(CONFIG_ARCH_MSM_KRAIT) += krait-l2pm.o
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obj-$(CONFIG_DEVFREQ_GOV_MSM_CACHE_HWMON) += governor_cache_hwmon.o
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# DEVFREQ Drivers
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446
drivers/devfreq/krait-l2pm.c
Normal file
446
drivers/devfreq/krait-l2pm.c
Normal file
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@ -0,0 +1,446 @@
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/*
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* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define pr_fmt(fmt) "krait-l2pm: " fmt
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <linux/spinlock.h>
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#include "governor_bw_hwmon.h"
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#include "governor_cache_hwmon.h"
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#include <mach/msm-krait-l2-accessors.h>
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#define L2PMRESR(n) (0x410 + n)
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#define L2PMCR 0x400
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#define L2PMCNTENCLR 0x402
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#define L2PMCNTENSET 0x403
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#define L2PMINTENCLR 0x404
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#define L2PMINTENSET 0x405
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#define L2PMOVSR 0x406
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#define L2PMOVSSET 0x407
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#define L2PMCCNTR 0x409
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#define L2PMnEVCNTCR(n) (0x420 + n * 0x10)
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#define L2PMnEVCNTR(n) (0x421 + n * 0x10)
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#define L2PMnEVCNTSR(n) (0x422 + n * 0x10)
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#define L2PMnEVFILTER(n) (0x423 + n * 0x10)
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#define L2PMnEVTYPER(n) (0x424 + n * 0x10)
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static DEFINE_SPINLOCK(mon_lock);
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static void global_mon_enable(bool en)
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{
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static unsigned int cnt;
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u32 regval;
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spin_lock(&mon_lock);
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if (en) {
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cnt++;
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} else {
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if (cnt)
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cnt--;
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}
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/* Global counter enable */
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regval = get_l2_indirect_reg(L2PMCR);
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if (cnt)
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regval |= BIT(0);
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else
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regval &= ~BIT(0);
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set_l2_indirect_reg(L2PMCR, regval);
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spin_unlock(&mon_lock);
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}
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static void mon_enable(int n)
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{
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/* Clear previous overflow state for event counter n */
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set_l2_indirect_reg(L2PMOVSR, BIT(n));
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/* Enable event counter n */
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set_l2_indirect_reg(L2PMCNTENSET, BIT(n));
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}
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static void mon_disable(int n)
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{
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/* Disable event counter n */
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set_l2_indirect_reg(L2PMCNTENCLR, BIT(n));
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}
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static void mon_irq_enable(int n, bool en)
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{
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if (en)
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set_l2_indirect_reg(L2PMINTENSET, BIT(n));
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else
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set_l2_indirect_reg(L2PMINTENCLR, BIT(n));
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}
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static int mon_overflow(int n)
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{
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return get_l2_indirect_reg(L2PMOVSR) & BIT(n);
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}
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/* Returns start counter value to be used with mon_get_count() */
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static u32 mon_set_limit(int n, u32 count)
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{
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u32 regval;
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regval = 0xFFFFFFFF - count;
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set_l2_indirect_reg(n == 31 ? L2PMCCNTR : L2PMnEVCNTR(n), regval);
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pr_debug("EV%d start val: %x\n", n, regval);
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return regval;
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}
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static long mon_get_count(int n, u32 start_val)
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{
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u32 overflow, count;
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count = get_l2_indirect_reg(n == 31 ? L2PMCCNTR : L2PMnEVCNTR(n));
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overflow = get_l2_indirect_reg(L2PMOVSR);
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pr_debug("EV%d ov: %x, cnt: %x\n", n, overflow, count);
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if (overflow & BIT(n))
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return 0xFFFFFFFF - start_val + count;
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else
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return count - start_val;
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}
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#define RD_MON 0
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#define WR_MON 1
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#define L2_H_REQ_MON 2
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#define L2_M_REQ_MON 3
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#define L2_CYC_MON 31
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/* ********** CPUBW specific code ********** */
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static u32 bytes_per_beat;
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static u32 prev_r_start_val;
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static u32 prev_w_start_val;
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static int bw_irq;
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static void mon_bw_init(void)
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{
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/* Set up counters 0/1 to count write/read beats */
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set_l2_indirect_reg(L2PMRESR(2), 0x8B0B0000);
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set_l2_indirect_reg(L2PMnEVCNTCR(RD_MON), 0x0);
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set_l2_indirect_reg(L2PMnEVCNTCR(WR_MON), 0x0);
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set_l2_indirect_reg(L2PMnEVCNTR(RD_MON), 0xFFFFFFFF);
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set_l2_indirect_reg(L2PMnEVCNTR(WR_MON), 0xFFFFFFFF);
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set_l2_indirect_reg(L2PMnEVFILTER(RD_MON), 0xF003F);
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set_l2_indirect_reg(L2PMnEVFILTER(WR_MON), 0xF003F);
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set_l2_indirect_reg(L2PMnEVTYPER(RD_MON), 0xA);
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set_l2_indirect_reg(L2PMnEVTYPER(WR_MON), 0xB);
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}
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/* Returns MBps of read/writes for the sampling window. */
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static unsigned int beats_to_mbps(long long beats, unsigned int us)
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{
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beats *= USEC_PER_SEC;
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beats *= bytes_per_beat;
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do_div(beats, us);
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beats = DIV_ROUND_UP_ULL(beats, SZ_1M);
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return beats;
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}
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static unsigned int mbps_to_beats(unsigned long mbps, unsigned int ms,
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unsigned int tolerance_percent)
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{
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mbps *= (100 + tolerance_percent) * ms;
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mbps /= 100;
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mbps = DIV_ROUND_UP(mbps, MSEC_PER_SEC);
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mbps = mult_frac(mbps, SZ_1M, bytes_per_beat);
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return mbps;
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}
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static unsigned long meas_bw_and_set_irq(struct bw_hwmon *hw,
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unsigned int tol, unsigned int us)
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{
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unsigned long r_mbps, w_mbps;
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u32 r_limit, w_limit;
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unsigned int sample_ms = hw->df->profile->polling_ms;
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mon_disable(RD_MON);
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mon_disable(WR_MON);
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r_mbps = mon_get_count(RD_MON, prev_r_start_val);
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r_mbps = beats_to_mbps(r_mbps, us);
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w_mbps = mon_get_count(WR_MON, prev_w_start_val);
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w_mbps = beats_to_mbps(w_mbps, us);
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r_limit = mbps_to_beats(r_mbps, sample_ms, tol);
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w_limit = mbps_to_beats(w_mbps, sample_ms, tol);
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prev_r_start_val = mon_set_limit(RD_MON, r_limit);
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prev_w_start_val = mon_set_limit(WR_MON, w_limit);
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mon_enable(RD_MON);
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mon_enable(WR_MON);
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pr_debug("R/W = %ld/%ld\n", r_mbps, w_mbps);
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return r_mbps + w_mbps;
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}
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static irqreturn_t bwmon_intr_handler(int irq, void *dev)
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{
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if (mon_overflow(RD_MON) || mon_overflow(WR_MON)) {
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update_bw_hwmon(dev);
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return IRQ_HANDLED;
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}
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return IRQ_NONE;
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}
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static int start_bw_hwmon(struct bw_hwmon *hw, unsigned long mbps)
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{
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u32 limit;
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int ret;
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ret = request_threaded_irq(bw_irq, NULL, bwmon_intr_handler,
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IRQF_ONESHOT | IRQF_SHARED,
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"bw_hwmon", hw);
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if (ret) {
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pr_err("Unable to register interrupt handler!\n");
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return ret;
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}
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mon_bw_init();
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mon_disable(RD_MON);
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mon_disable(WR_MON);
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limit = mbps_to_beats(mbps, hw->df->profile->polling_ms, 0);
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limit /= 2;
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prev_r_start_val = mon_set_limit(RD_MON, limit);
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prev_w_start_val = mon_set_limit(WR_MON, limit);
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mon_irq_enable(RD_MON, true);
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mon_irq_enable(WR_MON, true);
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mon_enable(RD_MON);
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mon_enable(WR_MON);
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global_mon_enable(true);
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return 0;
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}
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static void stop_bw_hwmon(struct bw_hwmon *hw)
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{
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disable_irq(bw_irq);
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free_irq(bw_irq, hw);
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global_mon_enable(false);
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mon_disable(RD_MON);
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mon_disable(WR_MON);
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mon_irq_enable(RD_MON, false);
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mon_irq_enable(WR_MON, false);
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}
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static struct devfreq_governor devfreq_gov_cpubw_hwmon = {
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.name = "cpubw_hwmon",
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};
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static struct bw_hwmon cpubw_hwmon = {
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.start_hwmon = &start_bw_hwmon,
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.stop_hwmon = &stop_bw_hwmon,
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.meas_bw_and_set_irq = &meas_bw_and_set_irq,
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.gov = &devfreq_gov_cpubw_hwmon,
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};
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/* ********** Cache reqs specific code ********** */
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static u32 prev_req_start_val;
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static void mon_mrps_init(void)
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{
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/* Cache bank requests */
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set_l2_indirect_reg(L2PMRESR(0), 0x86000001);
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set_l2_indirect_reg(L2PMnEVCNTCR(L2_H_REQ_MON), 0x0);
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set_l2_indirect_reg(L2PMnEVCNTR(L2_H_REQ_MON), 0x0);
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set_l2_indirect_reg(L2PMnEVFILTER(L2_H_REQ_MON), 0xF003F);
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set_l2_indirect_reg(L2PMnEVTYPER(L2_H_REQ_MON), 0x0);
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set_l2_indirect_reg(L2PMnEVCNTCR(L2_M_REQ_MON), 0x0);
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set_l2_indirect_reg(L2PMnEVCNTR(L2_M_REQ_MON), 0x0);
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set_l2_indirect_reg(L2PMnEVFILTER(L2_M_REQ_MON), 0xF003F);
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set_l2_indirect_reg(L2PMnEVTYPER(L2_M_REQ_MON), 0x3);
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}
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/* Returns million requests/sec for the sampling window. */
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static int count_to_mrps(long long count, unsigned int us)
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{
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do_div(count, us);
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count++;
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return count;
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}
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static unsigned int mrps_to_count(unsigned int mrps, unsigned int ms,
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unsigned int tolerance)
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{
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mrps += tolerance;
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mrps *= ms * USEC_PER_MSEC;
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return mrps;
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}
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static unsigned long meas_mrps_and_set_irq(struct devfreq *df,
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unsigned int tol, unsigned int us,
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struct mrps_stats *mrps)
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{
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u32 limit;
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unsigned int sample_ms = df->profile->polling_ms;
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unsigned long f = df->previous_freq;
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unsigned long t_mrps, m_mrps, l2_cyc;
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mon_disable(L2_H_REQ_MON);
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mon_disable(L2_M_REQ_MON);
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mon_disable(L2_CYC_MON);
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t_mrps = mon_get_count(L2_H_REQ_MON, prev_req_start_val);
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t_mrps = count_to_mrps(t_mrps, us);
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m_mrps = mon_get_count(L2_M_REQ_MON, 0);
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m_mrps = count_to_mrps(m_mrps, us);
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l2_cyc = mon_get_count(L2_CYC_MON, 0);
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limit = mrps_to_count(t_mrps, sample_ms, tol);
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prev_req_start_val = mon_set_limit(L2_H_REQ_MON, limit);
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mon_set_limit(L2_M_REQ_MON, 0xFFFFFFFF);
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mon_set_limit(L2_CYC_MON, 0xFFFFFFFF);
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mon_enable(L2_H_REQ_MON);
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mon_enable(L2_M_REQ_MON);
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mon_enable(L2_CYC_MON);
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mrps->high = t_mrps - m_mrps;
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mrps->med = m_mrps;
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mrps->low = 0;
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mrps->busy_percent = mult_frac(l2_cyc, 1000, us) * 100 / f;
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return 0;
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}
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static bool is_valid_mrps_irq(struct devfreq *df)
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{
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return mon_overflow(L2_H_REQ_MON) || mon_overflow(L2_M_REQ_MON);
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}
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static int start_mrps_hwmon(struct devfreq *df, struct mrps_stats *mrps)
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{
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u32 limit;
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mon_mrps_init();
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mon_disable(L2_H_REQ_MON);
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mon_disable(L2_M_REQ_MON);
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mon_disable(L2_CYC_MON);
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limit = mrps_to_count(mrps->high, df->profile->polling_ms, 0);
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prev_req_start_val = mon_set_limit(L2_H_REQ_MON, limit);
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mon_set_limit(L2_M_REQ_MON, 0xFFFFFFFF);
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mon_set_limit(L2_CYC_MON, 0xFFFFFFFF);
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mon_irq_enable(L2_H_REQ_MON, true);
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mon_irq_enable(L2_M_REQ_MON, true);
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mon_enable(L2_H_REQ_MON);
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mon_enable(L2_M_REQ_MON);
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mon_enable(L2_CYC_MON);
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global_mon_enable(true);
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return 0;
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}
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static void stop_mrps_hwmon(struct devfreq *df)
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{
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global_mon_enable(false);
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mon_disable(L2_H_REQ_MON);
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mon_disable(L2_M_REQ_MON);
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mon_disable(L2_CYC_MON);
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mon_irq_enable(L2_H_REQ_MON, false);
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mon_irq_enable(L2_M_REQ_MON, false);
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}
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static struct cache_hwmon mrps_hwmon = {
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.start_hwmon = &start_mrps_hwmon,
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.stop_hwmon = &stop_mrps_hwmon,
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.is_valid_irq = &is_valid_mrps_irq,
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.meas_mrps_and_set_irq = &meas_mrps_and_set_irq,
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};
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/*************************************************************************/
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static int krait_l2pm_driver_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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int ret, ret2;
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bw_irq = platform_get_irq(pdev, 0);
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if (bw_irq < 0) {
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pr_err("Unable to get IRQ number\n");
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return bw_irq;
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}
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mrps_hwmon.irq = bw_irq;
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ret = of_property_read_u32(dev->of_node, "qcom,bytes-per-beat",
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&bytes_per_beat);
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if (ret) {
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pr_err("Unable to read bytes per beat\n");
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return ret;
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}
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ret = register_bw_hwmon(dev, &cpubw_hwmon);
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if (ret)
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pr_err("CPUBW hwmon registration failed\n");
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ret2 = register_cache_hwmon(&mrps_hwmon);
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if (ret2)
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pr_err("Cache hwmon registration failed\n");
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if (ret && ret2)
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return ret2;
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return 0;
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}
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static struct of_device_id match_table[] = {
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{ .compatible = "qcom,kraitbw-l2pm" },
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{}
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};
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static struct platform_driver krait_l2pm_driver = {
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.probe = krait_l2pm_driver_probe,
|
||||
.driver = {
|
||||
.name = "kraitbw-l2pm",
|
||||
.of_match_table = match_table,
|
||||
.owner = THIS_MODULE,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init krait_l2pm_init(void)
|
||||
{
|
||||
return platform_driver_register(&krait_l2pm_driver);
|
||||
}
|
||||
module_init(krait_l2pm_init);
|
||||
|
||||
static void __exit krait_l2pm_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&krait_l2pm_driver);
|
||||
}
|
||||
module_exit(krait_l2pm_exit);
|
||||
|
||||
MODULE_DESCRIPTION("Krait L2 performance monitor driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
Loading…
Add table
Reference in a new issue