evie/android_kernel_oneplus_msm8998
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msm: mdss: fix logic to flush timing engine

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Fix logic to avoid timing engine flush in the first
commit when continuous splash is enabled.

Change-Id: I12b4969e9ec1ca421fa9b72cabbe9fee7d6061fb
Signed-off-by: Ingrid Gallardo <ingridg@codeaurora.org>
This commit is contained in:
Ingrid Gallardo 2014-08-25 19:57:32 -07:00 • committed by David Keitel
parent 649fad848a
commit a83b3a245c
2 changed files with 11 additions and 20 deletions
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8
drivers/video/fbdev/msm/mdss_mdp_ctl.c
View file

@ -1649,9 +1649,6 @@ static inline int mdss_mdp_set_split_ctl(struct mdss_mdp_ctl *ctl,
* original ctl can work the same way as dual pipe solution */
ctl->mixer_right = split_ctl->mixer_left;
if ((mdata->mdp_rev >= MDSS_MDP_HW_REV_103) && ctl->is_video_mode)
ctl->split_flush_en = true;
return 0;
}
@ -2059,10 +2056,13 @@ static void mdss_mdp_ctl_split_display_enable(int enable,
writel_relaxed(enable, main_ctl->mdata->mdp_base +
MDSS_MDP_REG_SPLIT_DISPLAY_EN);
if (main_ctl->split_flush_en)
if ((main_ctl->mdata->mdp_rev >= MDSS_MDP_HW_REV_103)
&& main_ctl->is_video_mode) {
main_ctl->split_flush_en = true;
writel_relaxed(enable ? 0x1 : 0x0,
main_ctl->mdata->mdp_base +
MMSS_MDP_MDP_SSPP_SPARE_0);
}
}
static void mdss_mdp_ctl_dst_split_display_enable(int enable,

13
drivers/video/fbdev/msm/mdss_mdp_intf_video.c
View file

@ -126,8 +126,6 @@ static int mdss_mdp_video_timegen_setup(struct mdss_mdp_ctl *ctl,
u32 den_polarity, hsync_polarity, vsync_polarity;
u32 display_hctl, active_hctl, hsync_ctl, polarity_ctl;
struct mdss_mdp_video_ctx *ctx;
struct mdss_mdp_ctl *sctl = NULL;
u32 flush_bits;
ctx = ctl->priv_data;
hsync_period = p->hsync_pulse_width + p->h_back_porch +
@ -145,16 +143,9 @@ static int mdss_mdp_video_timegen_setup(struct mdss_mdp_ctl *ctl,
display_v_end -= p->h_front_porch;
}
sctl = mdss_mdp_get_split_ctl(ctl);
flush_bits = mdss_mdp_ctl_read(ctl, MDSS_MDP_REG_CTL_FLUSH);
flush_bits |= BIT(31) >>
ctl->flush_bits |= BIT(31) >>
(ctl->intf_num - MDSS_MDP_INTF0);
if (sctl)
flush_bits |= BIT(31) >>
(sctl->intf_num - MDSS_MDP_INTF0);
hsync_start_x = p->h_back_porch + p->hsync_pulse_width;
hsync_end_x = hsync_period - p->h_front_porch - 1;
@ -220,7 +211,6 @@ static int mdss_mdp_video_timegen_setup(struct mdss_mdp_ctl *ctl,
mdp_video_write(ctx, MDSS_MDP_REG_INTF_HSYNC_SKEW, p->hsync_skew);
mdp_video_write(ctx, MDSS_MDP_REG_INTF_POLARITY_CTL, polarity_ctl);
mdp_video_write(ctx, MDSS_MDP_REG_INTF_FRAME_LINE_COUNT_EN, 0x3);
mdss_mdp_ctl_write(ctl, MDSS_MDP_REG_CTL_FLUSH, flush_bits);
return 0;
}
@ -985,6 +975,7 @@ static int mdss_mdp_video_intfs_setup(struct mdss_mdp_ctl *ctl,
pinfo->bpp);
itp.vsync_pulse_width = pinfo->lcdc.v_pulse_width;
if (!ctl->panel_data->panel_info.cont_splash_enabled)
if (mdss_mdp_video_timegen_setup(ctl, &itp)) {
pr_err("unable to set timing parameters intfs: %d\n",
(inum + MDSS_MDP_INTF0));