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ARM: dts: msm: Change GPU clock plan for msmcobalt interposer

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Change GPU clock plan based on requirements for msmcobalt
interposer platform versions.

Change-Id: I817859817eeb76c565d1604fcb1cc11b0df2dd30
Signed-off-by: Rajesh Kemisetti <rajeshk@codeaurora.org>
This commit is contained in:
Rajesh Kemisetti 2016-11-14 01:09:26 +05:30
parent ace335774a
commit a852ef6625
2 changed files with 52 additions and 39 deletions
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45
arch/arm/boot/dts/qcom/msmcobalt-interposer-msmfalcon.dtsi
View file

@ -3088,3 +3088,48 @@
#include "msmcobalt-mdss-pll.dtsi"
#include "msmcobalt-blsp.dtsi"
#include "msmcobalt-audio.dtsi"
/* GPU overrides */
&msm_gpu {
qcom,initial-pwrlevel = <0>;
qcom,gpu-pwrlevels {
#address-cells = <1>;
#size-cells = <0>;
compatible = "qcom,gpu-pwrlevels";
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <332000000>;
qcom,bus-freq = <7>;
qcom,bus-min = <6>;
qcom,bus-max = <8>;
};
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <251000000>;
qcom,bus-freq = <4>;
qcom,bus-min = <3>;
qcom,bus-max = <5>;
};
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-freq = <171000000>;
qcom,bus-freq = <3>;
qcom,bus-min = <1>;
qcom,bus-max = <4>;
};
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-freq = <27000000>;
qcom,bus-freq = <0>;
qcom,bus-min = <0>;
qcom,bus-max = <0>;
};
};
};

46
arch/arm/boot/dts/qcom/msmcobalt-v2-interposer-msmfalcon.dtsi
View file

@ -750,7 +750,7 @@
&msm_gpu {
/* Updated chip ID */
qcom,chipid = <0x05040001>;
qcom,initial-pwrlevel = <5>;
qcom,initial-pwrlevel = <0>;
qcom,gpu-pwrlevels {
#address-cells = <1>;
@ -760,61 +760,29 @@
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <670000000>;
qcom,bus-freq = <12>;
qcom,bus-min = <11>;
qcom,bus-max = <12>;
};
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <596000000>;
qcom,bus-freq = <11>;
qcom,bus-min = <9>;
qcom,bus-max = <12>;
};
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-freq = <515000000>;
qcom,bus-freq = <11>;
qcom,bus-min = <9>;
qcom,bus-max = <12>;
};
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-freq = <414000000>;
qcom,bus-freq = <9>;
qcom,bus-min = <8>;
qcom,bus-max = <11>;
};
qcom,gpu-pwrlevel@4 {
reg = <4>;
qcom,gpu-freq = <342000000>;
qcom,bus-freq = <8>;
qcom,bus-min = <5>;
qcom,bus-max = <9>;
};
qcom,gpu-pwrlevel@5 {
reg = <5>;
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <257000000>;
qcom,bus-freq = <5>;
qcom,bus-min = <3>;
qcom,bus-max = <8>;
};
qcom,gpu-pwrlevel@6 {
reg = <6>;
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-freq = <180000000>;
qcom,bus-freq = <3>;
qcom,bus-min = <1>;
qcom,bus-max = <5>;
};
qcom,gpu-pwrlevel@7 {
reg = <7>;
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-freq = <27000000>;
qcom,bus-freq = <0>;
qcom,bus-min = <0>;