spmi: msm: add virtual SPMI interrupt support
Add interrupt support for virtual SPMI front-end driver. It will co-work with backend to serve interrupts of GPIOs and VADC on PMIC. Change-Id: I7404b18b553f58c8a645a0e300633828de41cfb3 Signed-off-by: Yimin Peng <yiminp@codeaurora.org>
This commit is contained in:
Yimin Peng
parent
3967069a45
commit
a8c4fabd93
1 changed files with 544 additions and 10 deletions
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@ -15,6 +15,9 @@
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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@ -31,6 +34,10 @@
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#define VPMIC_ARB_DATA0 0x08
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#define VPMIC_ARB_DATA1 0x10
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/* Mapping Table */
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#define PMIC_ARB_MAX_PPID BIT(12) /* PPID is 12bit */
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#define PMIC_ARB_CHAN_VALID BIT(15)
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/* Channel Status fields */
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enum pmic_arb_chnl_status {
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PMIC_ARB_STATUS_DONE = BIT(0),
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@ -39,9 +46,6 @@ enum pmic_arb_chnl_status {
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PMIC_ARB_STATUS_DROPPED = BIT(3),
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};
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/* Command register fields */
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#define PMIC_ARB_CMD_MAX_BYTE_COUNT 8
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/* Command Opcodes */
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enum pmic_arb_cmd_op_code {
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PMIC_ARB_OP_EXT_WRITEL = 0,
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@ -74,21 +78,68 @@ enum pmic_arb_channel {
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#define PMIC_ARB_TIMEOUT_US 100
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#define PMIC_ARB_MAX_TRANS_BYTES (8)
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#define PMIC_ARB_APID_MASK 0xFF
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#define PMIC_ARB_PPID_MASK 0xFFF
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/* interrupt enable bit */
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#define SPMI_PIC_ACC_ENABLE_BIT BIT(0)
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#define HWIRQ(slave_id, periph_id, irq_id, apid) \
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((((slave_id) & 0xF) << 28) | \
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(((periph_id) & 0xFF) << 20) | \
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(((irq_id) & 0x7) << 16) | \
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(((apid) & 0x1FF) << 0))
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#define HWIRQ_SID(hwirq) (((hwirq) >> 28) & 0xF)
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#define HWIRQ_PER(hwirq) (((hwirq) >> 20) & 0xFF)
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#define HWIRQ_IRQ(hwirq) (((hwirq) >> 16) & 0x7)
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#define HWIRQ_APID(hwirq) (((hwirq) >> 0) & 0x1FF)
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struct vspmi_backend_driver_ver_ops;
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struct apid_data {
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u16 ppid;
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u8 write_owner;
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u8 irq_owner;
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};
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/**
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* vspmi_pmic_arb - Virtual SPMI PMIC Arbiter object
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*
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* @wr_base: on v1 "core", on v2 "chnls" register base off DT.
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* @intr: address of the SPMI interrupt control registers.
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* @acc_status: address of SPMI ACC interrupt status registers.
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* @lock: lock to synchronize accesses.
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* @irq: PMIC ARB interrupt.
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* @min_apid: minimum APID (used for bounding IRQ search)
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* @max_apid: maximum APID
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* @max_periph: maximum number of PMIC peripherals supported by HW.
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* @mapping_table: in-memory copy of PPID -> APID mapping table.
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* @domain: irq domain object for PMIC IRQ domain
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* @spmic: SPMI controller object
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* @ver_ops: backend version dependent operations.
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* @ppid_to_apid in-memory copy of PPID -> channel (APID) mapping table.
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*/
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struct vspmi_pmic_arb {
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void __iomem *wr_base;
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void __iomem *core;
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void __iomem *intr;
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void __iomem *acc_status;
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resource_size_t core_size;
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raw_spinlock_t lock;
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u8 channel;
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int irq;
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u16 min_apid;
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u16 max_apid;
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u16 max_periph;
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u32 *mapping_table;
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DECLARE_BITMAP(mapping_table_valid, PMIC_ARB_MAX_PERIPHS);
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struct irq_domain *domain;
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struct spmi_controller *spmic;
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const struct vspmi_backend_driver_ver_ops *ver_ops;
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u16 *ppid_to_apid;
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u16 last_apid;
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struct apid_data apid_data[PMIC_ARB_MAX_PERIPHS];
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};
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static struct vspmi_pmic_arb *the_pa;
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@ -96,11 +147,22 @@ static struct vspmi_pmic_arb *the_pa;
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* pmic_arb_ver: version dependent functionality.
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*
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* @ver_str: version string.
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* @ppid_to_apid: finds the apid for a given ppid.
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* @fmt_cmd: formats a GENI/SPMI command.
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* @acc_enable: offset of SPMI_PIC_ACC_ENABLEn.
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* @irq_status: offset of SPMI_PIC_IRQ_STATUSn.
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* @irq_clear: offset of SPMI_PIC_IRQ_CLEARn.
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* @channel_map_offset: offset of PMIC_ARB_REG_CHNLn
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*/
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struct vspmi_backend_driver_ver_ops {
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const char *ver_str;
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int (*ppid_to_apid)(struct vspmi_pmic_arb *pa, u8 sid, u16 addr,
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u16 *apid);
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u32 (*fmt_cmd)(u8 opc, u8 sid, u16 addr, u8 bc);
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u32 (*acc_enable)(u16 n);
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u32 (*irq_status)(u16 n);
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u32 (*irq_clear)(u16 n);
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u32 (*channel_map_offset)(u16 n);
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};
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/**
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@ -112,7 +174,7 @@ struct vspmi_backend_driver_ver_ops {
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static void
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vspmi_pa_read_data(struct vspmi_pmic_arb *pa, u8 *buf, u32 reg, u8 bc)
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{
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u32 data = __raw_readl(pa->core + reg);
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u32 data = __raw_readl(pa->wr_base + reg);
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memcpy(buf, &data, (bc & 3) + 1);
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}
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@ -129,7 +191,7 @@ vspmi_pa_write_data(struct vspmi_pmic_arb *pa, const u8 *buf, u32 reg, u8 bc)
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u32 data = 0;
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memcpy(&data, buf, (bc & 3) + 1);
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writel_relaxed(data, pa->core + reg);
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writel_relaxed(data, pa->wr_base + reg);
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}
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static int vspmi_pmic_arb_wait_for_done(struct spmi_controller *ctrl,
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@ -207,8 +269,8 @@ static int vspmi_pmic_arb_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
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cmd = pa->ver_ops->fmt_cmd(opc, sid, addr, bc);
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raw_spin_lock_irqsave(&pa->lock, flags);
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writel_relaxed(cmd, pa->core + VPMIC_ARB_CMD);
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rc = vspmi_pmic_arb_wait_for_done(ctrl, pa->core, sid, addr,
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writel_relaxed(cmd, pa->wr_base + VPMIC_ARB_CMD);
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rc = vspmi_pmic_arb_wait_for_done(ctrl, pa->wr_base, sid, addr,
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PMIC_ARB_CHANNEL_OBS);
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if (rc)
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goto done;
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@ -260,23 +322,415 @@ static int vspmi_pmic_arb_write_cmd(struct spmi_controller *ctrl, u8 opc,
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vspmi_pa_write_data(pa, buf + 4, VPMIC_ARB_DATA1, bc - 4);
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/* Start the transaction */
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writel_relaxed(cmd, pa->core + VPMIC_ARB_CMD);
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rc = vspmi_pmic_arb_wait_for_done(ctrl, pa->core, sid, addr,
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writel_relaxed(cmd, pa->wr_base + VPMIC_ARB_CMD);
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rc = vspmi_pmic_arb_wait_for_done(ctrl, pa->wr_base, sid, addr,
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PMIC_ARB_CHANNEL_RW);
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raw_spin_unlock_irqrestore(&pa->lock, flags);
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return rc;
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}
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enum qpnpint_regs {
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QPNPINT_REG_RT_STS = 0x10,
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QPNPINT_REG_SET_TYPE = 0x11,
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QPNPINT_REG_POLARITY_HIGH = 0x12,
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QPNPINT_REG_POLARITY_LOW = 0x13,
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QPNPINT_REG_LATCHED_CLR = 0x14,
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QPNPINT_REG_EN_SET = 0x15,
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QPNPINT_REG_EN_CLR = 0x16,
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QPNPINT_REG_LATCHED_STS = 0x18,
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};
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struct spmi_pmic_arb_qpnpint_type {
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u8 type; /* 1 -> edge */
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u8 polarity_high;
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u8 polarity_low;
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} __packed;
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/* Simplified accessor functions for irqchip callbacks */
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static void qpnpint_spmi_write(struct irq_data *d, u8 reg, void *buf,
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size_t len)
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{
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struct vspmi_pmic_arb *pa = irq_data_get_irq_chip_data(d);
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u8 sid = HWIRQ_SID(d->hwirq);
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u8 per = HWIRQ_PER(d->hwirq);
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if (vspmi_pmic_arb_write_cmd(pa->spmic, SPMI_CMD_EXT_WRITEL, sid,
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(per << 8) + reg, buf, len))
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dev_err_ratelimited(&pa->spmic->dev,
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"failed irqchip transaction on %x\n",
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d->irq);
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}
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static void qpnpint_spmi_read(struct irq_data *d, u8 reg, void *buf, size_t len)
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{
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struct vspmi_pmic_arb *pa = irq_data_get_irq_chip_data(d);
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u8 sid = HWIRQ_SID(d->hwirq);
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u8 per = HWIRQ_PER(d->hwirq);
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if (vspmi_pmic_arb_read_cmd(pa->spmic, SPMI_CMD_EXT_READL, sid,
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(per << 8) + reg, buf, len))
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dev_err_ratelimited(&pa->spmic->dev,
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"failed irqchip transaction on %x\n",
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d->irq);
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}
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static void cleanup_irq(struct vspmi_pmic_arb *pa, u16 apid, int id)
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{
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u16 ppid = pa->apid_data[apid].ppid;
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u8 sid = ppid >> 8;
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u8 per = ppid & 0xFF;
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u8 irq_mask = BIT(id);
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dev_err_ratelimited(&pa->spmic->dev,
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"cleanup_irq apid=%d sid=0x%x per=0x%x irq=%d\n",
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apid, sid, per, id);
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writel_relaxed(irq_mask, pa->intr + pa->ver_ops->irq_clear(apid));
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}
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static void periph_interrupt(struct vspmi_pmic_arb *pa, u16 apid, bool show)
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{
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unsigned int irq;
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u32 status;
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int id;
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u8 sid = (pa->apid_data[apid].ppid >> 8) & 0xF;
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u8 per = pa->apid_data[apid].ppid & 0xFF;
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status = readl_relaxed(pa->intr + pa->ver_ops->irq_status(apid));
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while (status) {
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id = ffs(status) - 1;
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status &= ~BIT(id);
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irq = irq_find_mapping(pa->domain, HWIRQ(sid, per, id, apid));
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if (irq == 0) {
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cleanup_irq(pa, apid, id);
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continue;
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}
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if (show) {
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struct irq_desc *desc;
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const char *name = "null";
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desc = irq_to_desc(irq);
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if (desc == NULL)
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name = "stray irq";
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else if (desc->action && desc->action->name)
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name = desc->action->name;
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pr_warn("spmi_show_resume_irq: %d triggered [0x%01x, 0x%02x, 0x%01x] %s\n",
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irq, sid, per, id, name);
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} else {
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generic_handle_irq(irq);
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}
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}
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}
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static void __pmic_arb_chained_irq(struct vspmi_pmic_arb *pa, bool show)
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{
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u32 enable;
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int i;
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/* status based dispatch */
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bool acc_valid = false;
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u32 irq_status = 0;
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/* ACC_STATUS is empty but IRQ fired check IRQ_STATUS */
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if (!acc_valid) {
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for (i = pa->min_apid; i <= pa->max_apid; i++) {
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irq_status = readl_relaxed(pa->intr +
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pa->ver_ops->irq_status(i));
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if (irq_status) {
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enable = readl_relaxed(pa->intr +
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pa->ver_ops->acc_enable(i));
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if (enable & SPMI_PIC_ACC_ENABLE_BIT) {
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dev_dbg(&pa->spmic->dev,
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"Dispatching IRQ for apid=%d status=%x\n",
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i, irq_status);
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periph_interrupt(pa, i, show);
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}
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}
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}
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}
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}
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static void pmic_arb_chained_irq(struct irq_desc *desc)
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{
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struct vspmi_pmic_arb *pa = irq_desc_get_handler_data(desc);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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chained_irq_enter(chip, desc);
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__pmic_arb_chained_irq(pa, false);
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chained_irq_exit(chip, desc);
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}
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static void qpnpint_irq_ack(struct irq_data *d)
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{
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struct vspmi_pmic_arb *pa = irq_data_get_irq_chip_data(d);
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u8 irq = HWIRQ_IRQ(d->hwirq);
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u16 apid = HWIRQ_APID(d->hwirq);
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u8 data;
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writel_relaxed(BIT(irq), pa->intr + pa->ver_ops->irq_clear(apid));
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data = BIT(irq);
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qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &data, 1);
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}
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static void qpnpint_irq_mask(struct irq_data *d)
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{
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u8 irq = HWIRQ_IRQ(d->hwirq);
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u8 data = BIT(irq);
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qpnpint_spmi_write(d, QPNPINT_REG_EN_CLR, &data, 1);
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}
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static void qpnpint_irq_unmask(struct irq_data *d)
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{
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struct vspmi_pmic_arb *pa = irq_data_get_irq_chip_data(d);
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u8 irq = HWIRQ_IRQ(d->hwirq);
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u16 apid = HWIRQ_APID(d->hwirq);
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u8 buf[2];
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writel_relaxed(SPMI_PIC_ACC_ENABLE_BIT,
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pa->intr + pa->ver_ops->acc_enable(apid));
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qpnpint_spmi_read(d, QPNPINT_REG_EN_SET, &buf[0], 1);
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if (!(buf[0] & BIT(irq))) {
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/*
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* Since the interrupt is currently disabled, write to both the
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* LATCHED_CLR and EN_SET registers so that a spurious interrupt
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* cannot be triggered when the interrupt is enabled
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*/
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buf[0] = BIT(irq);
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buf[1] = BIT(irq);
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qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &buf, 2);
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}
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}
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static int qpnpint_irq_set_type(struct irq_data *d, unsigned int flow_type)
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{
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struct spmi_pmic_arb_qpnpint_type type;
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u8 irq = HWIRQ_IRQ(d->hwirq);
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u8 bit_mask_irq = BIT(irq);
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qpnpint_spmi_read(d, QPNPINT_REG_SET_TYPE, &type, sizeof(type));
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if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
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type.type |= bit_mask_irq;
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if (flow_type & IRQF_TRIGGER_RISING)
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type.polarity_high |= bit_mask_irq;
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if (flow_type & IRQF_TRIGGER_FALLING)
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type.polarity_low |= bit_mask_irq;
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} else {
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if ((flow_type & (IRQF_TRIGGER_HIGH)) &&
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(flow_type & (IRQF_TRIGGER_LOW)))
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return -EINVAL;
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type.type &= ~bit_mask_irq; /* level trig */
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if (flow_type & IRQF_TRIGGER_HIGH)
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type.polarity_high |= bit_mask_irq;
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else
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type.polarity_low |= bit_mask_irq;
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}
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qpnpint_spmi_write(d, QPNPINT_REG_SET_TYPE, &type, sizeof(type));
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if (flow_type & IRQ_TYPE_EDGE_BOTH)
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irq_set_handler_locked(d, handle_edge_irq);
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else
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irq_set_handler_locked(d, handle_level_irq);
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return 0;
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}
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static int qpnpint_get_irqchip_state(struct irq_data *d,
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enum irqchip_irq_state which,
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bool *state)
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{
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u8 irq = HWIRQ_IRQ(d->hwirq);
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u8 status = 0;
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if (which != IRQCHIP_STATE_LINE_LEVEL)
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return -EINVAL;
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qpnpint_spmi_read(d, QPNPINT_REG_RT_STS, &status, 1);
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*state = !!(status & BIT(irq));
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return 0;
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}
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static struct irq_chip pmic_arb_irqchip = {
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.name = "pmic_arb",
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.irq_ack = qpnpint_irq_ack,
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.irq_mask = qpnpint_irq_mask,
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.irq_unmask = qpnpint_irq_unmask,
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.irq_set_type = qpnpint_irq_set_type,
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.irq_get_irqchip_state = qpnpint_get_irqchip_state,
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.flags = IRQCHIP_MASK_ON_SUSPEND
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| IRQCHIP_SKIP_SET_WAKE,
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};
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static void qpnpint_irq_domain_activate(struct irq_domain *domain,
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struct irq_data *d)
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{
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u8 irq = HWIRQ_IRQ(d->hwirq);
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u8 buf;
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|
||||
buf = BIT(irq);
|
||||
qpnpint_spmi_write(d, QPNPINT_REG_EN_CLR, &buf, 1);
|
||||
qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &buf, 1);
|
||||
}
|
||||
|
||||
static int qpnpint_irq_domain_dt_translate(struct irq_domain *d,
|
||||
struct device_node *controller,
|
||||
const u32 *intspec,
|
||||
unsigned int intsize,
|
||||
unsigned long *out_hwirq,
|
||||
unsigned int *out_type)
|
||||
{
|
||||
struct vspmi_pmic_arb *pa = d->host_data;
|
||||
int rc;
|
||||
u16 apid;
|
||||
|
||||
dev_dbg(&pa->spmic->dev,
|
||||
"intspec[0] 0x%1x intspec[1] 0x%02x intspec[2] 0x%02x\n",
|
||||
intspec[0], intspec[1], intspec[2]);
|
||||
|
||||
if (irq_domain_get_of_node(d) != controller)
|
||||
return -EINVAL;
|
||||
if (intsize != 4)
|
||||
return -EINVAL;
|
||||
if (intspec[0] > 0xF || intspec[1] > 0xFF || intspec[2] > 0x7)
|
||||
return -EINVAL;
|
||||
|
||||
rc = pa->ver_ops->ppid_to_apid(pa, intspec[0],
|
||||
(intspec[1] << 8), &apid);
|
||||
if (rc < 0) {
|
||||
dev_err(&pa->spmic->dev,
|
||||
"failed to xlate sid = 0x%x, periph = 0x%x, irq = %u rc = %d\n",
|
||||
intspec[0], intspec[1], intspec[2], rc);
|
||||
return rc;
|
||||
}
|
||||
|
||||
/* Keep track of {max,min}_apid for bounding search during interrupt */
|
||||
if (apid > pa->max_apid)
|
||||
pa->max_apid = apid;
|
||||
if (apid < pa->min_apid)
|
||||
pa->min_apid = apid;
|
||||
|
||||
*out_hwirq = HWIRQ(intspec[0], intspec[1], intspec[2], apid);
|
||||
*out_type = intspec[3] & IRQ_TYPE_SENSE_MASK;
|
||||
|
||||
dev_dbg(&pa->spmic->dev, "out_hwirq = %lu\n", *out_hwirq);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int qpnpint_irq_domain_map(struct irq_domain *d,
|
||||
unsigned int virq,
|
||||
irq_hw_number_t hwirq)
|
||||
{
|
||||
struct vspmi_pmic_arb *pa = d->host_data;
|
||||
|
||||
dev_dbg(&pa->spmic->dev, "virq = %u, hwirq = %lu\n", virq, hwirq);
|
||||
|
||||
irq_set_chip_and_handler(virq, &pmic_arb_irqchip, handle_level_irq);
|
||||
irq_set_chip_data(virq, d->host_data);
|
||||
irq_set_noprobe(virq);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static u16 pmic_arb_find_apid(struct vspmi_pmic_arb *pa, u16 ppid)
|
||||
{
|
||||
u32 regval, offset;
|
||||
u16 apid;
|
||||
u16 id;
|
||||
|
||||
/*
|
||||
* PMIC_ARB_REG_CHNL is a table in HW mapping channel to ppid.
|
||||
* ppid_to_apid is an in-memory invert of that table.
|
||||
*/
|
||||
for (apid = pa->last_apid; apid < pa->max_periph; apid++) {
|
||||
offset = pa->ver_ops->channel_map_offset(apid);
|
||||
if (offset >= pa->core_size)
|
||||
break;
|
||||
|
||||
regval = readl_relaxed(pa->core + offset);
|
||||
if (!regval) {
|
||||
/* If this regval is 0, it means that this apid is
|
||||
* unused. Write the current ppid to this reg to
|
||||
* use this apid to map to the given ppid.
|
||||
*/
|
||||
writel_relaxed(ppid, pa->core + offset);
|
||||
regval = ppid;
|
||||
}
|
||||
|
||||
id = regval & PMIC_ARB_PPID_MASK;
|
||||
pa->ppid_to_apid[id] = apid | PMIC_ARB_CHAN_VALID;
|
||||
pa->apid_data[apid].ppid = id;
|
||||
if (id == ppid) {
|
||||
apid |= PMIC_ARB_CHAN_VALID;
|
||||
break;
|
||||
}
|
||||
}
|
||||
pa->last_apid = apid & ~PMIC_ARB_CHAN_VALID;
|
||||
|
||||
return apid;
|
||||
}
|
||||
|
||||
static int
|
||||
pmic_arb_ppid_to_apid_v2(struct vspmi_pmic_arb *pa, u8 sid, u16 addr, u16 *apid)
|
||||
{
|
||||
u16 ppid = (sid << 8) | (addr >> 8);
|
||||
u16 apid_valid;
|
||||
|
||||
apid_valid = pa->ppid_to_apid[ppid];
|
||||
if (!(apid_valid & PMIC_ARB_CHAN_VALID))
|
||||
apid_valid = pmic_arb_find_apid(pa, ppid);
|
||||
if (!(apid_valid & PMIC_ARB_CHAN_VALID))
|
||||
return -ENODEV;
|
||||
|
||||
*apid = (apid_valid & ~PMIC_ARB_CHAN_VALID);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static u32 vspmi_pmic_arb_fmt_cmd_v1(u8 opc, u8 sid, u16 addr, u8 bc)
|
||||
{
|
||||
return (opc << 27) | ((sid & 0xf) << 20) | (addr << 4) |
|
||||
((bc & 0x7) + 1);
|
||||
}
|
||||
|
||||
static u32 pmic_arb_acc_enable_v2(u16 n)
|
||||
{
|
||||
return 0x1000 * n;
|
||||
}
|
||||
|
||||
static u32 pmic_arb_irq_status_v2(u16 n)
|
||||
{
|
||||
return 0x4 + 0x1000 * n;
|
||||
}
|
||||
|
||||
static u32 pmic_arb_irq_clear_v2(u16 n)
|
||||
{
|
||||
return 0x8 + 0x1000 * n;
|
||||
}
|
||||
|
||||
static u32 pmic_arb_channel_map_offset_v2(u16 n)
|
||||
{
|
||||
return 0x800 + 0x4 * n;
|
||||
}
|
||||
|
||||
static const struct vspmi_backend_driver_ver_ops pmic_arb_v1 = {
|
||||
.ver_str = "v1",
|
||||
.ppid_to_apid = pmic_arb_ppid_to_apid_v2,
|
||||
.fmt_cmd = vspmi_pmic_arb_fmt_cmd_v1,
|
||||
.acc_enable = pmic_arb_acc_enable_v2,
|
||||
.irq_status = pmic_arb_irq_status_v2,
|
||||
.irq_clear = pmic_arb_irq_clear_v2,
|
||||
.channel_map_offset = pmic_arb_channel_map_offset_v2,
|
||||
};
|
||||
|
||||
static const struct irq_domain_ops pmic_arb_irq_domain_ops = {
|
||||
.map = qpnpint_irq_domain_map,
|
||||
.xlate = qpnpint_irq_domain_dt_translate,
|
||||
.activate = qpnpint_irq_domain_activate,
|
||||
};
|
||||
|
||||
static int vspmi_pmic_arb_probe(struct platform_device *pdev)
|
||||
|
|
@ -285,6 +739,7 @@ static int vspmi_pmic_arb_probe(struct platform_device *pdev)
|
|||
struct spmi_controller *ctrl;
|
||||
struct resource *res;
|
||||
u32 backend_ver;
|
||||
u32 channel;
|
||||
int err;
|
||||
|
||||
ctrl = spmi_controller_alloc(&pdev->dev, sizeof(*pa));
|
||||
|
|
@ -313,22 +768,101 @@ static int vspmi_pmic_arb_probe(struct platform_device *pdev)
|
|||
if (backend_ver == VPMIC_ARB_VERSION)
|
||||
pa->ver_ops = &pmic_arb_v1;
|
||||
|
||||
/* the apid to ppid table starts at PMIC_ARB_REG_CHNL0 */
|
||||
pa->max_periph
|
||||
= (pa->core_size - pa->ver_ops->channel_map_offset(0)) / 4;
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
|
||||
"chnls");
|
||||
pa->wr_base = devm_ioremap_resource(&ctrl->dev, res);
|
||||
if (IS_ERR(pa->wr_base)) {
|
||||
err = PTR_ERR(pa->wr_base);
|
||||
goto err_put_ctrl;
|
||||
}
|
||||
|
||||
pa->ppid_to_apid = devm_kcalloc(&ctrl->dev,
|
||||
PMIC_ARB_MAX_PPID,
|
||||
sizeof(*pa->ppid_to_apid),
|
||||
GFP_KERNEL);
|
||||
if (!pa->ppid_to_apid) {
|
||||
err = -ENOMEM;
|
||||
goto err_put_ctrl;
|
||||
}
|
||||
|
||||
|
||||
dev_info(&ctrl->dev, "PMIC arbiter version %s (0x%x)\n",
|
||||
pa->ver_ops->ver_str, backend_ver);
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "intr");
|
||||
pa->intr = devm_ioremap_resource(&ctrl->dev, res);
|
||||
if (IS_ERR(pa->intr)) {
|
||||
err = PTR_ERR(pa->intr);
|
||||
goto err_put_ctrl;
|
||||
}
|
||||
pa->acc_status = pa->intr;
|
||||
|
||||
pa->irq = platform_get_irq_byname(pdev, "periph_irq");
|
||||
if (pa->irq < 0) {
|
||||
err = pa->irq;
|
||||
goto err_put_ctrl;
|
||||
}
|
||||
|
||||
err = of_property_read_u32(pdev->dev.of_node, "qcom,channel", &channel);
|
||||
if (err) {
|
||||
dev_err(&pdev->dev, "channel unspecified.\n");
|
||||
goto err_put_ctrl;
|
||||
}
|
||||
|
||||
if (channel > 5) {
|
||||
dev_err(&pdev->dev, "invalid channel (%u) specified.\n",
|
||||
channel);
|
||||
err = -EINVAL;
|
||||
goto err_put_ctrl;
|
||||
}
|
||||
|
||||
pa->channel = channel;
|
||||
|
||||
pa->mapping_table = devm_kcalloc(&ctrl->dev, PMIC_ARB_MAX_PERIPHS - 1,
|
||||
sizeof(*pa->mapping_table), GFP_KERNEL);
|
||||
if (!pa->mapping_table) {
|
||||
err = -ENOMEM;
|
||||
goto err_put_ctrl;
|
||||
}
|
||||
|
||||
/* Initialize max_apid/min_apid to the opposite bounds, during
|
||||
* the irq domain translation, we are sure to update these.
|
||||
*/
|
||||
pa->max_apid = 0;
|
||||
pa->min_apid = PMIC_ARB_MAX_PERIPHS - 1;
|
||||
|
||||
platform_set_drvdata(pdev, ctrl);
|
||||
raw_spin_lock_init(&pa->lock);
|
||||
|
||||
ctrl->read_cmd = vspmi_pmic_arb_read_cmd;
|
||||
ctrl->write_cmd = vspmi_pmic_arb_write_cmd;
|
||||
|
||||
dev_dbg(&pdev->dev, "adding irq domain\n");
|
||||
pa->domain = irq_domain_add_tree(pdev->dev.of_node,
|
||||
&pmic_arb_irq_domain_ops, pa);
|
||||
if (!pa->domain) {
|
||||
dev_err(&pdev->dev, "unable to create irq_domain\n");
|
||||
err = -ENOMEM;
|
||||
goto err_put_ctrl;
|
||||
}
|
||||
|
||||
irq_set_chained_handler_and_data(pa->irq, pmic_arb_chained_irq, pa);
|
||||
enable_irq_wake(pa->irq);
|
||||
|
||||
err = spmi_controller_add(ctrl);
|
||||
if (err)
|
||||
goto err_put_ctrl;
|
||||
goto err_domain_remove;
|
||||
|
||||
the_pa = pa;
|
||||
return 0;
|
||||
|
||||
err_domain_remove:
|
||||
irq_set_chained_handler_and_data(pa->irq, NULL, NULL);
|
||||
irq_domain_remove(pa->domain);
|
||||
err_put_ctrl:
|
||||
spmi_controller_put(ctrl);
|
||||
return err;
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue