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drm/i915/skl: Derive the max CDCLK from DFSM

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Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Damien Lespiau 2015-06-04 18:21:30 +01:00 • committed by Jani Nikula
parent 70d0c57420
commit a9419e846b
2 changed files with 19 additions and 1 deletions
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7
drivers/gpu/drm/i915/i915_reg.h
View file

@ -5761,6 +5761,13 @@ enum skl_disp_power_wells {
#define HSW_NDE_RSTWRN_OPT 0x46408 #define HSW_NDE_RSTWRN_OPT 0x46408
#define RESET_PCH_HANDSHAKE_ENABLE (1<<4) #define RESET_PCH_HANDSHAKE_ENABLE (1<<4)
#define SKL_DFSM 0x51000
#define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23)
#define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23)
#define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)
#define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23)
#define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23)
#define FF_SLICE_CS_CHICKEN2 0x20e4 #define FF_SLICE_CS_CHICKEN2 0x20e4
#define GEN9_TSG_BARRIER_ACK_DISABLE (1<<8) #define GEN9_TSG_BARRIER_ACK_DISABLE (1<<8)

13
drivers/gpu/drm/i915/intel_display.c
View file

@ -5751,7 +5751,18 @@ static void intel_update_max_cdclk(struct drm_device *dev)
{ {
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
if (IS_BROADWELL(dev)) { if (IS_SKYLAKE(dev)) {
u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
if (limit == SKL_DFSM_CDCLK_LIMIT_675)
dev_priv->max_cdclk_freq = 675000;
else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
dev_priv->max_cdclk_freq = 540000;
else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
dev_priv->max_cdclk_freq = 450000;
else
dev_priv->max_cdclk_freq = 337500;
} else if (IS_BROADWELL(dev)) {
/* /*
* FIXME with extra cooling we can allow * FIXME with extra cooling we can allow
* 540 MHz for ULX and 675 Mhz for ULT. * 540 MHz for ULX and 675 Mhz for ULT.