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CRs      Change ID                                   Subject
--------------------------------------------------------------------------------------------------------------
1104858   I482bbf480d4129cdc6a1dfe08f37a1ec56c3131e   clk: qcom: Add FORCE_ENABLE_RCGR & CLK_ENABLE_HAND_OFF f
1104679   I53ac153ba9f7ae81bb0657b17e0e798fd3fe4f48   power_supply: Add SOC_REPORTING_READY property
1104679   I415e322e99bacd61c4e9ac921643d87d3eec4b3e   power: qpnp-fg-gen3: add SOC_REPORTING_READY property
1068294   I779074d0aba35827e1a8264385149967cb9973f3   regulator: cpr4-mmss: Add mmss CPR platform specific dri
1105323   I073ab59cc4ef1b71545a9e77b76d94f09d659aac   msm_11ad: Add option to enable SMMU fastmap
1102641   I39a1266f4158e71238f374b6cba49e1a8c2b1a3b   leds: qpnp-wled: Update WLED config
1104760   I2f9b4e9d45f95066ec93bb5fab179a14bc2c62ee   power: reset: Store KASLR offset in IMEM
986540   I711354941b4168f3f6ffe2d29185597bdad4da89   spi: spi_qsd: Fix the register peek/poke debug feature
1102726   I806456737485dfcbca8a71d59db0927bbd843708   clk: qcom: add MDSS PLL support for msmfalcon
1093863   I47cfe2cd7d93ba5db57365cf250c600dac22bab1   i2c-msm-v2:Synchronise runtime PM callback operations
1102841   I2661a639c19dd451f22c9a29d7d75d9b3fb98114   msm: mdss: Initialize mdss v3 pp driver ops for msmfalco
1101084   I334fd782a2c5d604cafb94f44832d9c700891ba2   msm: thermal: Update error handling of device offline
1105169   Ib089e7ddd38d0d15285ed65c8a29039451cfc3c5   ARM: dts: msm: Add initial support for msm8998 QRD SKUK
1104865   Ib1291524c53c4ec757a494a1e08cb0925720e1a6   msm: rtb: record counter timestamp for every log record
1081961   I5680dc5333c9664e1316c29a91e29231f15eb4f1   defconfig: msm: Add support for CPU OSM clock
1094763   Ifd41990058f8bbce8ba488770ffbfcd9b6067ad6   ASoC: msm: add support for WCD interrupt config via LPI
1103739   Ie5474c42ccdd88df4c101b2113ca8d924eddf037   usb: phy: qusb2: Switch to SE clk from diff clk upon sus
1068294   I2111fe55c9335d57ac91f18f4a4fb3689d80660d   defconfig: Compile GFX LDO regulator driver for msmfalco
1046799   I47db9f66c95846dbff882f631b915655c33c3d55   spi: spi_qsd: Don't restrict first transfer in FIFO mode
1104607   Ie85f7ede2d91767d0d5d20c90a481e6365ad7189   ARM: dts: msm: Add thermal mitigation properties to msmt
1104981   I476397d88e0f9d2b32ae375afc6f15eca4b9ec95   ARM: dts: msm: Add initial support for msm8998 QRD SKUK
1098662   I214bb19385f855af61da628fdf1cf7efc5dd08d6   msm: mdss: dp: fix calculation of link rate
1102900   Ide652165711eec23644d36837f3847d896293709   msm: mdss: Add mdss capabilities for msmfalcon
1104876   I9a707d953a85c16c9c5be82fd36960b49da36e3c   smcinvoke: support listener service request
1104976   Ic8c9657752271026d796ecd6c3b9f9f46f831f37   ARM: dts: msm: update icnss device node for msm8998-inte
1052835   I7f1419c8f7fd7c371767f6921afe0cd8cfaad18f   msm: camera: Change %p into %pK
1081961   I0aca021e51ef9ae59dedce855430a63937eb98c6   ARM: dts: msm: Add support for CPU clocks for msmfalcon
1076516   I290ec786bbe5c45873265ea74290eefcd3d16cb1   msm: mdss: dp: add support for PHY compliance tests
1100632   Iab69062336966e61683117a17974f46cd8f513aa   ARM: dts: msm: Allocate memory for diag client for msmfa
1103405   Iaaa69a56f13db9304640f115863bb882c72551a8   ARM: dts: msm: Update VA range for venus_ns and modify c
1083444   Ie2702223379b9c77ce4fe30376d446c63223dbc8   diag: dci: Fix possible dangling reference
1102776   I77f8e6de6f1b5c447a3516380c51db9c7129d2f3   spcom: abort any read() operation on SSR
1094456   Ib5247f6bceb1f555c03103f061af089755b2de62   clk: introduce CLK_ENABLE_HAND_OFF flag
1094763   Ib17d8bbd5894be5fbf3fa0cafdbec958abc42649   ARM: dts: msm: Enable audio internal codec nodes for msm
1103891   Iec6247a69c3258660eae398d6e3fe8215e3f254a   ARM: dts: msm: Add TP device node into msm8998 interpose
1104880 868394   I885ae66be2d8cca17bcc0b87b7635a71c734e4b2   usb/xhci: Add support for EHSET tests for host complianc
1094456   I7d527571c2eb4d53d58d82126989bd673de12e2d   clk: move check for CLK_ENABLE_HAND_OFF at unused tree
1093271   I472449c52bff40d48f7d65b05e145cc47cba9357   msm: crypto: fix AEAD issues for HW crypto driver on msm
1105038   I45d13b40fab9bf6686277c0c26a07668410cdfb2   usb: gadget: u_data_ipa: Fix condition check for IPA pip
1081961   I389cc9e93a26a434be752cf74444d6c0985ff36d   clk: qcom: Support CPU clock for OSM for common clock fr
1104001   Ib4cc69afb32a7654bbdd98f2efff901729c4d3da   clk: qcom: Add voltage voting for MSM8996 GCC driver
1104876   Ifeed957b99d2becd986629f60e145d6fdb717244   qseecom: support listener request for smcinvoke
1105100   Ic64d89b960c5effada93118d67a30cc051640be2   ARM: dts: msm: set rcu_expedited for msmfalcon and msmtr
1104853   If624bf14e8588e50fa6a97d29b528d7d02ef64dc   ARM: dts: msm: disable soft hot JEITA for 8998 QRD SKUK
1099484   I58c30a50c7834e7897daa2849b9885b3e797cf07   ARM: dts: msm: enable vdd and vdd-io for sdhc_2 on msm89
1099101   I41ab0baf1bbe6ccda6b8da2ecd077bea2a388e56   ASoC: msm: Check prepare state to avoid duplicate channe
1104977   I575aecb616a56974ec2680e5888190adb40c969a   ARM: dts: msm: set wled string/full scale current for QR
1092969   I6e315eec256f01c143ffc8b463279f2b30e64610   input: qpnp-power-on: Set ship mode in system_pwr_off
1104886   Ic44359e224e0f9070238748bd9b16eed35974ba6   ARM: dts: msm: add support of PM3FALCON based MSMFALCON
1097878   I3f895deaae3acf329088cf8135859cc41e781763   drivers: soc: qcom: Add error handling in function avtim
1104880   I88f2748f0c8cf96fe7f6ab9ebaa82d51ec97f4fd   defconfig: msmcortex: Enable EHSET Test Fixture device d
1104760   I456c62764c88149b785ecf1d65691ea5a775c1db   ARM: dts: msm: Add kaslr offset IMEM entry for msm8998
1104607   I780f9187256596d6f5d93b3847dc98a3c410a51e   ARM: dts: msm: Configure lmh hardware for msmtriton
1104928   I6aad9916c92d2f775632406374dbb803063148de   input: misc: fix heap overflow issue in hbtp_input.c
1101260   I6d59c7804d0dac5087e9b0e6c4a0cdacb5ddf3db   ARM: dts: msm: Add support for new flash mode on msm8998
1100528   I1fd7b7e7324b79544608a9d9ce73aa53608d1f3e   RM: dts: Update SD card Detect GPIO for msmfalcon
1104880   I638ca552f6dae735147378f3e6f6068e0003094b   usb: xhci: Add support for SINGLE_STEP_SET_FEATURE test
1103468   I547d792b38649aa1d60525b0dc335791b37989fd   msm: kgsl: Do a midframe sampling of power stats if enab
1104607   Id65a720d20fb34b9b5dccf8626af00a1d0519ce3   ARM: dts: msm: Add thermal sensor info for msmtriton
1100213   I29572841624c1cb96d85e2dcfe620b455867d41e   ARM: dts: msm: add devfreq nodes to msmfalcon target
1100018   I8e7c4be090107618cd6cbac394a57f109f8a1ced   usb: gadget: f_qc_rndis: Fix double-free in qcrndis_free
1084177   I2bbe7be3daedef45a5990c23168df5185e72e82f   msm: sensor: correcting return value for get actuator in
1102137   I2fce80cec72e3bd8b1561fd46fa1a1520cddd294   msm: mdss: dp: fix handling of link training mutex
1102584   Idd40a0b471293048833b34dda3ac5044a87fc3c9   ASoC: wcd934x: Fix headset TX mode setting
1103939   I03e4a8e10452ef53d8e35e7cee44bdf51f53483b   ARM: dts: msm: Add support for home hard key at QRD8998H
1098041   I8cc22af138a343cd387f4400cff487faa66b3da0   ASoC: wcd934x: Update class-H parameters based on headph
1095411   Ie639a26543e2f20b61d6dfc73b3bcbd6a43b24be   msm: mdss: Move PP programming after mdp wait for ping p
1093271   I406a41ac961757d31209ae0a0a4b4d9cc4d31a1e   defconfig: msm: disable CRYPTO_DEC_QCE device on msm8998
1104183   I58e19def0042022046e730dd97008a9e1c25b6d6   icnss: Add EXEC permission when assigning the MSA0 back
1104001   Ie596ddee60aac3e6fc996f9a3e8dc988b0f4aa88   clk: qcom: Add smd-rpm voter & voter branch clocks for M
1102726   I49efddea0228e3129d36eabc102d6df0fcd53d12   ARM: dts: msm: add mdss node for msmfalcon target
1099101   I1e76eb2e1c575b433e3899ae2471719bf68ab1c1   ASoC: msm: decrement slim channel ref to set the propert
1105246   I4de26881620dde4230d0a907bd0fd39bebe2bb3d   wil6210: missing reinit_completion in wmi_call

Change-Id: I0c6d90c668b09a08de714b3bcd03e1e513f1853a
CRs-Fixed: 1102584, 986540, 1104976, 1076516, 1104977, 1100018, 1102841, 1105100, 1104880, 1102900, 1081961, 1103939, 1104865, 1104679, 1105169, 1084177, 1105038, 1102641, 1099484, 1046799, 1052835, 1102137, 1098662, 1104853, 1098041, 1095411, 1083444, 1100632, 1104981, 1104858, 1100213, 1104607, 1093271, 1104928, 1102726, 1104876, 1093863, 1099101, 1103891, 1092969, 868394, 1094763, 1105246, 1103739, 1105323, 1094456, 1104760, 1101260, 1100528, 1097878, 1104886, 1104001, 1103468, 1102776, 1068294, 1101084, 1104183, 1103405
This commit is contained in:
Linux Build Service Account 2016-12-27 21:28:55 -07:00
commit aa36bb38fc
134 changed files with 5862 additions and 1105 deletions
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11
Documentation/devicetree/bindings/arm/msm/imem.txt
View file

@ -63,6 +63,11 @@ Emergency Download Mode:
-compatible: "qcom,msm-imem-emergency_download_mode"
-reg: start address and size of emergency_download_mode region in imem
Kaslr Offset:
------------------------
-compatible: "qcom,msm-imem-kaslr_offset"
-reg: start address and size of kaslr_offset region in imem
USB Diag Cookies:
-----------------
Memory region used to store USB PID and serial numbers to be used by
@ -101,6 +106,12 @@ Example:
reg = <0x6b0 32>;
};
kaslr_offset@6d0 {
compatible = "qcom,msm-imem-kaslr_offset";
reg = <0x6d0 12>;
};
pil@94c {
compatible = "qcom,msm-imem-pil";
reg = <0x94c 200>;

5
Documentation/devicetree/bindings/arm/msm/qcom,osm.txt
View file

@ -9,8 +9,9 @@ Properties:
- compatible
Usage: required
Value type: <string>
Definition: must be "qcom,cpu-clock-osm-msm8998-v1" or
"qcom,cpu-clock-osm-msm8998-v2".
Definition: must be "qcom,cpu-clock-osm-msm8998-v1",
"qcom,cpu-clock-osm-msm8998-v2" or
"qcom,clk-cpu-osm".
- reg
Usage: required

2
Documentation/devicetree/bindings/fb/mdss-pll.txt
View file

@ -15,7 +15,7 @@ Required properties:
"qcom,mdss_hdmi_pll_8996_v2", "qcom,mdss_dsi_pll_8996_v2",
"qcom,mdss_hdmi_pll_8996_v3", "qcom,mdss_hdmi_pll_8996_v3_1p8",
"qcom,mdss_dsi_pll_8998", "qcom,mdss_dp_pll_8998",
"qcom,mdss_hdmi_pll_8998"
"qcom,mdss_hdmi_pll_8998", "qcom,mdss_dsi_pll_msmfalcon"
- cell-index: Specifies the controller used
- reg: offset and length of the register set for the device.
- reg-names : names to refer to register sets related to this device

6
Documentation/devicetree/bindings/gpu/adreno.txt
View file

@ -143,6 +143,12 @@ Optional Properties:
Specify the name of GPU temperature sensor. This name will be used
to get the temperature from the thermal driver API.
- qcom,enable-midframe-timer:
Boolean. Enables the use of midframe sampling timer. This timer
samples the GPU powerstats if the cmdbatch expiry takes longer than
the threshold set by KGSL_GOVERNOR_CALL_INTERVAL. Enable only if
target has NAP state enabled.
GPU Quirks:
- qcom,gpu-quirk-two-pass-use-wfi:
Signal the GPU to set Set TWOPASSUSEWFI bit in

321
Documentation/devicetree/bindings/regulator/cpr4-mmss-ldo-regulator.txt Normal file
View file

@ -0,0 +1,321 @@
Qualcomm Technologies, Inc. CPR4 Regulator - MMSS LDO Specific Bindings
MMSS LDO CPR4 controllers each support one CPR thread that monitors the voltage
of the graphics processor (MMSS) supply regulator. The CPR open-loop voltages
are stored in hardware fuses for MMSS CPR4 controllers. However, the CPR target
quotients must be defined in device tree.
This document describes the MMSS LDO specific CPR4 bindings.
=======================
Required Node Structure
=======================
CPR3 regulators must be described in three levels of devices nodes. The first
level describes the CPR3 controller. The second level describes exacly one
hardware thread managed by the controller. The third level describes one or
more logical regulators handled by the CPR thread.
All platform independent cpr3-regulator binding guidelines defined in
cpr3-regulator.txt also apply to cpr4-mmss-ldo-regulator devices.
====================================
First Level Nodes - CPR3 Controllers
====================================
MMSS LDO specific properties:
- compatible
Usage: required
Value type: <string>
Definition: should be the following:
"qcom,cpr4-msmfalcon-mmss-ldo-regulator".
- clocks
Usage: required
Value type: <prop-encoded-array>
Definition: Array of clock tuples in which each tuple consists of a
phandle to a clock device and a clock ID number. The
following clocks must be specified: MMSS RBCPR and MMSS
RBCPR AHB.
- clock-names
Usage: required
Value type: <stringlist>
Definition: Clock names. This list must match up 1-to-1 with the clocks
specified in the 'clocks' property. "core_clk", and "bus_clk"
must be specified.
- qcom,cpr-step-quot-fixed
Usage: Optional
Value type: <u32>
Definition: Fixed step quotient value used by controller for applying
the SDELTA margin adjustments on the programmed target
quotient values. The step quotient is the number of
additional ring oscillator ticks observed for each
qcom,voltage-step increase in vdd-supply output voltage.
Supported values: 0 - 63.
=================================================
Second Level Nodes - CPR Threads for a Controller
=================================================
MMSS specific properties:
N/A
===============================================
Third Level Nodes - CPR Regulators for a Thread
===============================================
MMSS specific properties:
- qcom,cpr-fuse-corners
Usage: required
Value type: <u32>
Definition: Specifies the number of fuse corners. This value must be 6
for msmfalcon GFX LDO. These fuse corners are: MinSVS,
LowSVS, SVS, SVSP, NOM and NOMP. The open-loop voltage fuses
are allocated for LowSVS, SVS, NOM and NOMP corners. The
open-loop voltages for MinSVS and SVSP are derived by
applying fixed offset from LowSVS and NOM open-loop voltages
respectively. The closed-loop offset voltage fuses are
allocated for LowSVS, SVS, NOM and NOMP corners. The MinSVS
and SVSP corners use the closed-loop offset voltage fuses of
LowSVS and NOM corners respectively.
- qcom,cpr-fuse-combos
Usage: required
Value type: <u32>
Definition: Specifies the number of fuse combinations being supported by
the device. This value is utilized by several other
properties. Supported values are 1 up to the maximum
possible for a given regulator type. For MMSS the maximum
supported value is 8. These combos correspond to CPR
revision fuse values from 0 to 7 in order.
- qcom,mem-acc-voltage
Usage: required if mem-acc-supply is specified for the CPR3 controller
containing this CPR3 regulator
Value type: <prop-encoded-array>
Definition: A list of integer tuples which each define the mem-acc-supply
corner for each voltage corner in order from lowest to highest.
The list must contain qcom,cpr-fuse-combos number of tuples
in which case the tuples are matched to fuse combinations
1-to-1 or qcom,cpr-speed-bins number of tuples in which case
the tuples are matched to speed bins 1-to-1 or exactly 1
tuple which is used regardless of the fuse combination and
speed bin found on a given chip.
Each tuple must be of the length defined in the
corresponding element of the qcom,cpr-corners property or
the qcom,cpr-speed-bins property. A single tuple may only
be specified if all of the corner counts in qcom,cpr-corners
are the same.
- qcom,cpr-target-quotients
Usage: required
Value type: <prop-encoded-array>
Definition: A grouping of integer tuple lists. Each tuple defines the
CPR target quotient for each ring oscillator (RO) for a
given corner. Since CPR3 supports exactly 16 ROs, each
tuple must contain 16 elements corresponding to RO0 through
RO15 in order. If a given RO is unused for a corner, then
its target quotient should be specified as 0.
Each tuple list in the grouping must meet the same size
requirements as those specified for qcom,mem-acc-voltage
above. The tuples in a given list are ordered from the
lowest corner to the highest corner.
- qcom,cpr-ro-scaling-factor
Usage: required if qcom,cpr-closed-loop-voltage-adjustment is
specified
Value type: <prop-encoded-array>
Definition: The common definition of this property in cpr3-regulator.txt
is accurate for MMSS CPR3 controllers except for this
modification:
Each tuple list must contain the number of tuples defined in
the corresponding element of the qcom,cpr-corners property
or the qcom,cpr-speed-bins property as opposed to the value
of the qcom,cpr-fuse-corners property.
- qcom,cpr-fused-closed-loop-voltage-adjustment-map
Usage: optional
Value type: <prop-encoded-array>
Definition: A list of integer tuples which each define the CPR fused
corner closed-loop offset adjustment fuse to utilize for
each voltage corner in order from lowest to highest.
The list must contain qcom,cpr-fuse-combos number of tuples
in which case the tuples are matched to fuse combinations
1-to-1 or qcom,cpr-speed-bins number of tuples in which case
the tuples are matched to speed bins 1-to-1 or exactly 1
tuple which is used regardless of the fuse combination and
speed bin found on a given chip.
Each tuple must be of the length defined in the
corresponding element of the qcom,cpr-corners property or
the qcom,cpr-speed-bins property. A single tuple may only
be specified if all of the corner counts in qcom,cpr-corners
are the same.
Each tuple element must be either 0 or in the range 1 to
qcom,cpr-fuse-corners. A value of 0 signifies that no fuse
based adjustment should be applied to the fuse corner.
Values 1 to qcom,cpr-fuse-corners denote the specific fuse
corner that should be used by a given voltage corner.
- qcom,cpr-corner-allow-ldo-mode
Usage: optional
Value type: <prop-encoded-array>
Definition: A list of integer tuples which each define the LDO mode
allowed state for each voltage corner in order from lowest
to highest. Each element in the tuple should be either
0 (LDO mode not allowed) or 1 (LDO mode allowed).
The list must contain qcom,cpr-fuse-combos number of tuples
in which case the tuples are matched to fuse combinations
1-to-1 or qcom,cpr-speed-bins number of tuples in which case
the tuples are matched to speed bins 1-to-1 or exactly 1
tuple which is used regardless of the fuse combination and
speed bin found on a given chip.
Each tuple must be of the length defined in the
corresponding element of the qcom,cpr-corners property or
the qcom,cpr-speed-bin-corners property. A single tuple may
only be specified if all of the corner counts in
qcom,cpr-corners are the same.
- qcom,cpr-corner-allow-closed-loop
Usage: optional
Value type: <prop-encoded-array>
Definition: A list of integer tuples which each define the CPR
closed-loop operation allowed state for each voltage corner
in order from lowest to highest. Each element in the tuple
should be either 0 (CPR closed-loop operation not allowed)
or 1 (CPR closed-loop operation allowed).
The list must contain qcom,cpr-fuse-combos number of tuples
in which case the tuples are matched to fuse combinations
1-to-1 or qcom,cpr-speed-bins number of tuples in which case
the tuples are matched to speed bins 1-to-1 or exactly 1
tuple which is used regardless of the fuse combination and
speed bin found on a given chip.
Each tuple must be of the length defined in the
corresponding element of the qcom,cpr-corners property or
the qcom,cpr-speed-bin-corners property. A single tuple may
only be specified if all of the corner counts in
qcom,cpr-corners are the same.
Note that the qcom,cpr-closed-loop-voltage-fuse-adjustment property is not
meaningful for MMSS LDO CPR3 regulator nodes since target quotients are not
defined in fuses.
=======
Example
=======
gfx_cpr: cpr4-ctrl@05061000 {
compatible = "qcom,cpr4-msmfalcon-mmss-ldo-regulator";
reg = <0x05061000 0x4000>, <0x00784000 0x1000>;
reg-names = "cpr_ctrl", "fuse_base";
interrupts = <GIC_SPI 285 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "cpr";
qcom,cpr-ctrl-name = "gfx";
qcom,cpr-sensor-time = <1000>;
qcom,cpr-loop-time = <5000000>;
qcom,cpr-idle-cycles = <15>;
qcom,cpr-step-quot-init-min = <8>;
qcom,cpr-step-quot-init-max = <12>;
qcom,cpr-count-mode = <0>; /* All at once */
vdd-supply = <&gfx_stub_vreg>;
mem-acc-supply = <&gfx_mem_acc_vreg>;
system-supply = <&pm2falcon_s3_level>; /* vdd_cx */
qcom,voltage-step = <5000>;
vdd-thread0-ldo-supply = <&gfx_ldo_vreg>;
qcom,cpr-enable;
thread@0 {
qcom,cpr-thread-id = <0>;
qcom,cpr-consecutive-up = <0>;
qcom,cpr-consecutive-down = <2>;
qcom,cpr-up-threshold = <0>;
qcom,cpr-down-threshold = <2>;
gfx_vreg_corner: regulator {
regulator-name = "gfx_corner";
regulator-min-microvolt = <1>;
regulator-max-microvolt = <7>;
qcom,cpr-fuse-corners = <6>;
qcom,cpr-fuse-combos = <8>;
qcom,cpr-corners = <7>;
qcom,cpr-corner-fmax-map = <1 2 3 4 5 6>;
qcom,cpr-voltage-ceiling =
<584000 644000 724000 788000
868000 924000 1068000>;
qcom,cpr-voltage-floor =
<504000 504000 596000 652000
712000 744000 1068000>;
qcom,mem-acc-voltage = <1 1 1 2 2 2 2>;
qcom,system-voltage =
<RPM_SMD_REGULATOR_LEVEL_MIN_SVS>,
<RPM_SMD_REGULATOR_LEVEL_LOW_SVS>,
<RPM_SMD_REGULATOR_LEVEL_SVS>,
<RPM_SMD_REGULATOR_LEVEL_SVS_PLUS>,
<RPM_SMD_REGULATOR_LEVEL_NOM>,
<RPM_SMD_REGULATOR_LEVEL_NOM_PLUS>,
<RPM_SMD_REGULATOR_LEVEL_TURBO>;
qcom,corner-frequencies =
<160000000 266000000 370000000
465000000 588000000 647000000
800000000>;
qcom,cpr-target-quotients =
<0 0 0 0 0 0 185 179
291 299 304 319 0 0 0 0>,
<0 0 0 0 0 0 287 273
425 426 443 453 0 0 0 0>,
<0 0 0 0 0 0 414 392
584 576 608 612 0 0 0 0>,
<0 0 0 0 0 0 459 431
684 644 692 679 0 0 0 0>,
<0 0 0 0 0 0 577 543
798 768 823 810 0 0 0 0>,
<0 0 0 0 0 0 669 629
886 864 924 911 0 0 0 0>,
<0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0>;
qcom,cpr-ro-scaling-factor =
< 0 0 0 0 0 0 2035 1917
1959 2131 2246 2253 0 0 0 0>,
< 0 0 0 0 0 0 2035 1917
1959 2131 2246 2253 0 0 0 0>,
< 0 0 0 0 0 0 2035 1917
1959 2131 2246 2253 0 0 0 0>,
< 0 0 0 0 0 0 2035 1917
1959 2131 2246 2253 0 0 0 0>,
< 0 0 0 0 0 0 2035 1917
1959 2131 2246 2253 0 0 0 0>,
< 0 0 0 0 0 0 2035 1917
1959 2131 2246 2253 0 0 0 0>,
< 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0>;
qcom,cpr-scaled-open-loop-voltage-as-ceiling;
qcom,cpr-corner-ldo-mode-allowed =
<1 1 1 1 1 1 0>;
qcom,cpr-corner-use-closed-loop =
<1 1 1 1 1 1 0>;
};
};
};

24
arch/arm/boot/dts/qcom/Makefile
View file

@ -116,6 +116,8 @@ dtb-$(CONFIG_ARCH_MSM8998) += msm8998-sim.dtb \
msm8998-v2-qrd-skuk.dtb \
msm8998-qrd-vr1.dtb \
msm8998-v2-qrd-vr1.dtb \
msm8998-v2-qrd-skuk-evt3.dtb \
msm8998-v2-qrd-skuk-hdk.dtb \
apq8998-mtp.dtb \
apq8998-cdp.dtb \
apq8998-v2-mtp.dtb \
@ -135,17 +137,29 @@ dtb-$(CONFIG_ARCH_MSM8998) += msm8998-sim.dtb \
dtb-$(CONFIG_ARCH_MSMHAMSTER) += msmhamster-rumi.dtb
dtb-$(CONFIG_ARCH_MSMFALCON) += msmfalcon-sim.dtb \
msmfalcon-rumi.dtb \
msmfalcon-cdp.dtb \
msmfalcon-internal-codec-cdp.dtb \
msmfalcon-mtp.dtb \
msmfalcon-internal-codec-mtp.dtb \
msmfalcon-rcm.dtb \
msmfalcon-internal-codec-rcm.dtb \
msmfalcon-cdp.dtb \
msmfalcon-mtp.dtb \
msmfalcon-qrd.dtb \
msmfalcon-rcm.dtb \
msmfalcon-rumi.dtb \
msmfalcon-pm3falcon-cdp.dtb \
msmfalcon-pm3falcon-mtp.dtb \
msmfalcon-pm3falcon-qrd.dtb \
msmfalcon-pm3falcon-rcm.dtb \
msmfalcon-pm3falcon-rumi.dtb \
msmfalcon-internal-codec-pm3falcon-cdp.dtb \
msmfalcon-internal-codec-pm3falcon-mtp.dtb \
msmfalcon-internal-codec-pm3falcon-rcm.dtb \
msmfalcon-pm3falcon-sim.dtb \
apqfalcon-cdp.dtb \
apqfalcon-mtp.dtb \
apqfalcon-rcm.dtb
apqfalcon-rcm.dtb \
apqfalcon-pm3falcon-cdp.dtb \
apqfalcon-pm3falcon-mtp.dtb \
apqfalcon-pm3falcon-rcm.dtb
dtb-$(CONFIG_ARCH_MSMTRITON) += msmtriton-rumi.dtb

4
arch/arm/boot/dts/qcom/apqfalcon-cdp.dts
View file

@ -17,7 +17,9 @@
#include "msmfalcon-cdp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. APQ FALCON CDP";
model = "Qualcomm Technologies, Inc. APQ FALCON PMFALCON + PM2FALCON CDP";
compatible = "qcom,apqfalcon-cdp", "qcom,apqfalcon", "qcom,cdp";
qcom,board-id = <1 0>;
qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>,
<0x0001001b 0x0201011a 0x0 0x0>;
};

4
arch/arm/boot/dts/qcom/apqfalcon-mtp.dts
View file

@ -17,7 +17,9 @@
#include "msmfalcon-mtp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. APQ FALCON MTP";
model = "Qualcomm Technologies, Inc. APQ FALCON PMFALCON + PM2FALCON MTP";
compatible = "qcom,apqfalcon-mtp", "qcom,apqfalcon", "qcom,mtp";
qcom,board-id = <8 0>;
qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>,
<0x0001001b 0x0201011a 0x0 0x0>;
};

25
arch/arm/boot/dts/qcom/apqfalcon-pm3falcon-cdp.dts Normal file
View file

@ -0,0 +1,25 @@
/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/dts-v1/;
#include "apqfalcon.dtsi"
#include "msmfalcon-cdp.dtsi"
#include "msm-pm3falcon.dtsi"
/ {
model = "Qualcomm Technologies, Inc. APQ FALCON PMFALCON + PM3FALCON CDP";
compatible = "qcom,apqfalcon-cdp", "qcom,apqfalcon", "qcom,cdp";
qcom,board-id = <1 0>;
qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>;
};

25
arch/arm/boot/dts/qcom/apqfalcon-pm3falcon-mtp.dts Normal file
View file

@ -0,0 +1,25 @@
/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/dts-v1/;
#include "apqfalcon.dtsi"
#include "msmfalcon-mtp.dtsi"
#include "msm-pm3falcon.dtsi"
/ {
model = "Qualcomm Technologies, Inc. APQ FALCON PMFALCON + PM3FALCON MTP";
compatible = "qcom,apqfalcon-mtp", "qcom,apqfalcon", "qcom,mtp";
qcom,board-id = <8 0>;
qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>;
};

25
arch/arm/boot/dts/qcom/apqfalcon-pm3falcon-rcm.dts Normal file
View file

@ -0,0 +1,25 @@
/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/dts-v1/;
#include "apqfalcon.dtsi"
#include "msmfalcon-cdp.dtsi"
#include "msm-pm3falcon.dtsi"
/ {
model = "Qualcomm Technologies, Inc. APQ FALCON PMFALCON + PM3FALCON RCM";
compatible = "qcom,apqfalcon-cdp", "qcom,apqfalcon", "qcom,cdp";
qcom,board-id = <21 0>;
qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>;
};

4
arch/arm/boot/dts/qcom/apqfalcon-rcm.dts
View file

@ -17,7 +17,9 @@
#include "msmfalcon-cdp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. APQ FALCON RCM";
model = "Qualcomm Technologies, Inc. APQ FALCON PMFALCON + PM2FALCON RCM";
compatible = "qcom,apqfalcon-cdp", "qcom,apqfalcon", "qcom,cdp";
qcom,board-id = <21 0>;
qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>,
<0x0001001b 0x0201011a 0x0 0x0>;
};

2
arch/arm/boot/dts/qcom/msm8998-camera-sensor-skuk.dtsi
View file

@ -16,6 +16,7 @@
cell-index = <0>;
compatible = "qcom,camera-flash";
qcom,flash-source = <&pmi8998_flash0 &pmi8998_flash1>;
qcom,torch-source = <&pmi8998_torch0 &pmi8998_torch1>;
qcom,switch-source = <&pmi8998_switch0>;
status = "ok";
};
@ -24,6 +25,7 @@
cell-index = <1>;
compatible = "qcom,camera-flash";
qcom,flash-source = <&pmi8998_flash2>;
qcom,torch-source = <&pmi8998_torch2>;
qcom,switch-source = <&pmi8998_switch1>;
status = "ok";
};

5
arch/arm/boot/dts/qcom/msm8998-interposer-msmfalcon.dtsi
View file

@ -2886,7 +2886,6 @@
};
qcom,icnss@18800000 {
status = "disabled";
compatible = "qcom,icnss";
reg = <0x18800000 0x800000>,
<0x10AC000 0x20>,
@ -2894,6 +2893,8 @@
<0xb0000000 0x10000>;
reg-names = "membase", "mpm_config",
"smmu_iova_base", "smmu_iova_ipa";
iommus = <&anoc2_smmu 0x1900>,
<&anoc2_smmu 0x1901>;
interrupts = <0 413 0 /* CE0 */ >,
<0 414 0 /* CE1 */ >,
<0 415 0 /* CE2 */ >,
@ -2907,6 +2908,8 @@
<0 424 0 /* CE10 */ >,
<0 425 0 /* CE11 */ >;
qcom,wlan-msa-memory = <0x100000>;
qcom,icnss-vadc = <&pmfalcon_vadc>;
qcom,icnss-adc_tm = <&pmfalcon_adc_tm>;
};
tspp: msm_tspp@0c1e7000 {

76
arch/arm/boot/dts/qcom/msm8998-pinctrl.dtsi
View file

@ -1637,6 +1637,82 @@
};
};
/* add pingrp for touchscreen */
pmx_ts_int_active {
ts_int_active: ts_int_active {
mux {
pins = "gpio125";
function = "gpio";
};
config {
pins = "gpio125";
drive-strength = <8>;
bias-pull-up;
};
};
};
pmx_ts_int_suspend {
ts_int_suspend1: ts_int_suspend1 {
mux {
pins = "gpio125";
function = "gpio";
};
config {
pins = "gpio125";
drive-strength = <2>;
bias-pull-down;
};
};
};
pmx_ts_reset_active {
ts_reset_active: ts_reset_active {
mux {
pins = "gpio89";
function = "gpio";
};
config {
pins = "gpio89";
drive-strength = <8>;
bias-pull-up;
};
};
};
pmx_ts_reset_suspend {
ts_reset_suspend1: ts_reset_suspend1 {
mux {
pins = "gpio89";
function = "gpio";
};
config {
pins = "gpio89";
drive-strength = <2>;
bias-pull-down;
};
};
};
pmx_ts_release {
ts_release: ts_release {
mux {
pins = "gpio125", "gpio89";
function = "gpio";
};
config {
pins = "gpio125", "gpio89";
drive-strength = <2>;
bias-pull-down;
};
};
};
ts_mux {
ts_active: ts_active {
mux {

15
arch/arm/boot/dts/qcom/msm8998-qrd-skuk.dtsi
View file

@ -160,6 +160,15 @@
input-name = "gpio-keys";
status = "okay";
home {
label = "home";
gpios = <&pm8998_gpios 5 0x1>;
linux,input-type = <1>;
linux,code = <102>;
gpio-key,wakeup;
debounce-interval = <15>;
};
vol_up {
label = "volume_up";
gpios = <&pm8998_gpios 6 0x1>;
@ -290,12 +299,18 @@
&pmi8998_fg {
qcom,battery-data = <&qrd_batterydata>;
qcom,fg-jeita-thresholds = <0 5 55 55>;
};
&pmi8998_haptics {
status = "okay";
};
&pmi8998_wled {
qcom,led-strings-list = [00 01];
qcom,fs-curr-ua = <20000>;
};
&tlmm {
/* add pingrp for touchscreen */
pmx_ts_rst_active {

1
arch/arm/boot/dts/qcom/msm8998-qrd-vr1.dtsi
View file

@ -196,6 +196,7 @@
&pmi8998_fg {
qcom,battery-data = <&qrd_batterydata>;
qcom,fg-jeita-thresholds = <0 5 55 55>;
};
&pmi8998_haptics {

23
arch/arm/boot/dts/qcom/msm8998-v2-qrd-skuk-evt3.dts Normal file
View file

@ -0,0 +1,23 @@
/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/dts-v1/;
#include "msm8998-v2.dtsi"
#include "msm8998-qrd-skuk.dtsi"
/ {
model = "Qualcomm Technologies, Inc. MSM 8998 V2 SKUK EVT3";
compatible = "qcom,msm8998-qrd", "qcom,msm8998", "qcom,qrd";
qcom,board-id = <0x02000b 0x10>;
};

23
arch/arm/boot/dts/qcom/msm8998-v2-qrd-skuk-hdk.dts Normal file
View file

@ -0,0 +1,23 @@
/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/dts-v1/;
#include "msm8998-v2.dtsi"
#include "msm8998-qrd-skuk.dtsi"
/ {
model = "Qualcomm Technologies, Inc. MSM 8998 SKUK HDK";
compatible = "qcom,msm8998-qrd", "qcom,msm8998", "qcom,qrd";
qcom,board-id = <0x06000b 0x10>;
};

5
arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-qrd.dts
View file

@ -118,6 +118,11 @@
core-supply = <&pmfalcon_l1>;
};
&sdhc_2 {
vdd-supply = <&pm2falcon_l5>;
vdd-io-supply = <&pm2falcon_l2>;
};
&pm2falcon_gpios {
/* GPIO 7 for VOL_UP */
gpio@c600 {

56
arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-qrd.dtsi
View file

@ -72,30 +72,6 @@
status = "ok";
};
&sdc2_cd_on {
mux {
pins = "gpio54";
};
config {
pins = "gpio54";
/delete-property/ bias-pull-up;
bias-disable;
};
};
&sdc2_cd_off {
mux {
pins = "gpio54";
};
config {
pins = "gpio54";
/delete-property/ bias-pull-up;
bias-disable;
};
};
&sdhc_2 {
vdd-supply = <&pm2falcon_l5>;
qcom,vdd-voltage-level = <2950000 2950000>;
@ -113,7 +89,37 @@
50000000 100000000 200000000>;
qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104";
cd-gpios = <&tlmm 54 0x0>;
cd-gpios = <&tlmm 95 0x0>;
status = "ok";
};
&i2c_5 {
status = "okay";
synaptics@20 {
compatible = "synaptics,dsx";
reg = <0x20>;
interrupt-parent = <&tlmm>;
interrupts = <125 0x2008>;
avdd-supply = <&pm2falcon_l3>;
vdd-supply = <&pmfalcon_l11>;
synaptics,vdd-voltage = <1880000 1880000>;
synaptics,avdd-voltage = <3000000 3008000>;
synaptics,vdd-current = <40000>;
synaptics,avdd-current = <20000>;
/* pins used by touchscreen */
pinctrl-names = "pmx_ts_active", "pmx_ts_suspend",
"pmx_ts_release";
pinctrl-0 = <&ts_int_active &ts_reset_active>;
pinctrl-1 = <&ts_int_suspend1 &ts_reset_suspend1>;
pinctrl-2 = <&ts_release>;
synaptics,display-coords = <0 0 1439 2559>;
synaptics,panel-coords = <0 0 1439 2779>;
synaptics,irq-gpio = <&tlmm 125 0x2008>;
synaptics,reset-gpio = <&tlmm 89 0x0>;
synaptics,i2c-pull-up;
synaptics,disable-gpios;
synaptics,button-map = <139 172 158>;
};
};

5
arch/arm/boot/dts/qcom/msm8998.dtsi
View file

@ -2825,6 +2825,11 @@
reg = <0x6b0 32>;
};
kaslr_offset@6d0 {
compatible = "qcom,msm-imem-kaslr_offset";
reg = <0x6d0 12>;
};
pil@94c {
compatible = "qcom,msm-imem-pil";
reg = <0x94c 200>;

5
arch/arm/boot/dts/qcom/msmfalcon-audio.dtsi
View file

@ -15,12 +15,13 @@
#include "msmfalcon-lpi.dtsi"
&slim_aud {
msm_dai_slim {
status = "okay";
dai_slim: msm_dai_slim {
compatible = "qcom,msm-dai-slim";
elemental-addr = [ff ff ff fe 17 02];
};
tasha_codec {
wcd9335: tasha_codec {
compatible = "qcom,tasha-slim-pgd";
elemental-addr = [00 01 a0 01 17 02];

4
arch/arm/boot/dts/qcom/msmfalcon-cdp.dts
View file

@ -17,7 +17,9 @@
#include "msmfalcon-cdp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. MSM FALCON CDP";
model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM2FALCON CDP";
compatible = "qcom,msmfalcon-cdp", "qcom,msmfalcon", "qcom,cdp";
qcom,board-id = <1 0>;
qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>,
<0x0001001b 0x0201011a 0x0 0x0>;
};

46
arch/arm/boot/dts/qcom/msmfalcon-cdp.dtsi
View file

@ -42,6 +42,52 @@
status = "ok";
};
&mdss_mdp {
qcom,mdss-pref-prim-intf = "dsi";
};
&mdss_dsi {
hw-config = "split_dsi";
};
&mdss_dsi0 {
qcom,dsi-pref-prim-pan = <&dsi_dual_nt35597_truly_video>;
pinctrl-names = "mdss_default", "mdss_sleep";
pinctrl-0 = <&mdss_dsi_active &mdss_te_active>;
pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>;
qcom,platform-reset-gpio = <&tlmm 53 0>;
qcom,platform-te-gpio = <&tlmm 59 0>;
};
&mdss_dsi1 {
qcom,dsi-pref-prim-pan = <&dsi_dual_nt35597_truly_video>;
pinctrl-names = "mdss_default", "mdss_sleep";
pinctrl-0 = <&mdss_dsi_active &mdss_te_active>;
pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>;
qcom,platform-reset-gpio = <&tlmm 53 0>;
qcom,platform-te-gpio = <&tlmm 59 0>;
};
&pm2falcon_wled {
qcom,led-strings-list = [01 02];
};
&dsi_dual_nt35597_truly_video {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
qcom,mdss-dsi-bl-min-level = <1>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-dsi-mode-sel-gpio-state = "dual_port";
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
};
&dsi_dual_nt35597_truly_cmd {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
qcom,mdss-dsi-bl-min-level = <1>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-dsi-mode-sel-gpio-state = "dual_port";
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
};
&soc {
qcom,msm-ssc-sensors {
compatible = "qcom,msm-ssc-sensors";

52
arch/arm/boot/dts/qcom/msmfalcon-internal-codec-cdp.dts
View file

@ -17,7 +17,57 @@
#include "msmfalcon-cdp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. MSM FALCON Int. Audio Codec CDP";
model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM2FALCON Int. Audio Codec CDP";
compatible = "qcom,msmfalcon-cdp", "qcom,msmfalcon", "qcom,cdp";
qcom,board-id = <1 1>;
qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>,
<0x0001001b 0x0201011a 0x0 0x0>;
};
&slim_aud {
status = "disabled";
};
&dai_slim {
status = "disabled";
};
&wcd9335 {
status = "disabled";
};
&wcd934x_cdc {
status = "disabled";
};
&clock_audio {
status = "disabled";
};
&wcd_rst_gpio {
status = "disabled";
};
&wcd9xxx_intc {
status = "disabled";
};
&tasha_snd {
status = "disabled";
};
&tavil_snd {
status = "disabled";
};
&int_codec {
status = "okay";
};
&pmic_analog_codec {
status = "okay";
};
&msm_sdw_codec {
status = "okay";
};

53
arch/arm/boot/dts/qcom/msmfalcon-internal-codec-mtp.dts
View file

@ -17,7 +17,58 @@
#include "msmfalcon-mtp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. MSM FALCON Int. Audio Codec MTP";
model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM2FALCON Int. Audio Codec MTP";
compatible = "qcom,msmfalcon-mtp", "qcom,msmfalcon", "qcom,mtp";
qcom,board-id = <8 1>;
qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>,
<0x0001001b 0x0201011a 0x0 0x0>;
};
&slim_aud {
status = "disabled";
};
&dai_slim {
status = "disabled";
};
&wcd9335 {
status = "disabled";
};
&wcd934x_cdc {
status = "disabled";
};
&clock_audio {
status = "disabled";
};
&wcd_rst_gpio {
status = "disabled";
};
&wcd9xxx_intc {
status = "disabled";
};
&tasha_snd {
status = "disabled";
};
&tavil_snd {
status = "disabled";
};
&int_codec {
qcom,model = "msmfalcon-snd-card-mtp";
status = "okay";
};
&pmic_analog_codec {
status = "okay";
};
&msm_sdw_codec {
status = "okay";
};

25
arch/arm/boot/dts/qcom/msmfalcon-internal-codec-pm3falcon-cdp.dts Normal file
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@ -0,0 +1,25 @@
/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/dts-v1/;
#include "msmfalcon.dtsi"
#include "msmfalcon-cdp.dtsi"
#include "msm-pm3falcon.dtsi"
/ {
model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM3FALCON Int. Audio Codec CDP";
compatible = "qcom,msmfalcon-cdp", "qcom,msmfalcon", "qcom,cdp";
qcom,board-id = <1 1>;
qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>;
};

25
arch/arm/boot/dts/qcom/msmfalcon-internal-codec-pm3falcon-mtp.dts Normal file
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/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/dts-v1/;
#include "msmfalcon.dtsi"
#include "msmfalcon-mtp.dtsi"
#include "msm-pm3falcon.dtsi"
/ {
model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM3FALCON Int. Audio Codec MTP";
compatible = "qcom,msmfalcon-mtp", "qcom,msmfalcon", "qcom,mtp";
qcom,board-id = <8 1>;
qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>;
};

25
arch/arm/boot/dts/qcom/msmfalcon-internal-codec-pm3falcon-rcm.dts Normal file
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/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/dts-v1/;
#include "msmfalcon.dtsi"
#include "msmfalcon-cdp.dtsi"
#include "msm-pm3falcon.dtsi"
/ {
model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM3FALCON Int. Audio Codec RCM";
compatible = "qcom,msmfalcon-cdp", "qcom,msmfalcon", "qcom,cdp";
qcom,board-id = <21 1>;
qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>;
};

52
arch/arm/boot/dts/qcom/msmfalcon-internal-codec-rcm.dts
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@ -17,7 +17,57 @@
#include "msmfalcon-cdp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. MSM FALCON Int. Audio Codec RCM";
model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM2FALCON Int. Audio Codec RCM";
compatible = "qcom,msmfalcon-cdp", "qcom,msmfalcon", "qcom,cdp";
qcom,board-id = <21 1>;
qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>,
<0x0001001b 0x0201011a 0x0 0x0>;
};
&slim_aud {
status = "disabled";
};
&dai_slim {
status = "disabled";
};
&wcd9335 {
status = "disabled";
};
&wcd934x_cdc {
status = "disabled";
};
&clock_audio {
status = "disabled";
};
&wcd_rst_gpio {
status = "disabled";
};
&wcd9xxx_intc {
status = "disabled";
};
&tasha_snd {
status = "disabled";
};
&tavil_snd {
status = "disabled";
};
&int_codec {
status = "okay";
};
&pmic_analog_codec {
status = "okay";
};
&msm_sdw_codec {
status = "okay";
};

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arch/arm/boot/dts/qcom/msmfalcon-mdss-panels.dtsi Normal file
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/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "dsi-panel-sim-video.dtsi"
#include "dsi-panel-sim-dualmipi-video.dtsi"
#include "dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi"
#include "dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi"
&soc {
dsi_panel_pwr_supply: dsi_panel_pwr_supply {
#address-cells = <1>;
#size-cells = <0>;
qcom,panel-supply-entry@0 {
reg = <0>;
qcom,supply-name = "wqhd-vddio";
qcom,supply-min-voltage = <1880000>;
qcom,supply-max-voltage = <1950000>;
qcom,supply-enable-load = <32000>;
qcom,supply-disable-load = <80>;
};
qcom,panel-supply-entry@1 {
reg = <1>;
qcom,supply-name = "lab";
qcom,supply-min-voltage = <4600000>;
qcom,supply-max-voltage = <6000000>;
qcom,supply-enable-load = <100000>;
qcom,supply-disable-load = <100>;
};
qcom,panel-supply-entry@2 {
reg = <2>;
qcom,supply-name = "ibb";
qcom,supply-min-voltage = <4600000>;
qcom,supply-max-voltage = <6000000>;
qcom,supply-enable-load = <100000>;
qcom,supply-disable-load = <100>;
qcom,supply-post-on-sleep = <10>;
};
};
};
&soc {
dsi_panel_pwr_supply_no_labibb: dsi_panel_pwr_supply_no_labibb {
#address-cells = <1>;
#size-cells = <0>;
qcom,panel-supply-entry@0 {
reg = <0>;
qcom,supply-name = "wqhd-vddio";
qcom,supply-min-voltage = <1880000>;
qcom,supply-max-voltage = <1950000>;
qcom,supply-enable-load = <32000>;
qcom,supply-disable-load = <80>;
};
};
};
&dsi_dual_nt35597_truly_video {
qcom,mdss-dsi-panel-timings-8996 = [23 1e 07 08 05 03 04 a0
23 1e 07 08 05 03 04 a0
23 1e 07 08 05 03 04 a0
23 1e 07 08 05 03 04 a0
23 18 07 08 04 03 04 a0];
};
&dsi_dual_nt35597_truly_cmd {
qcom,mdss-dsi-panel-timings-8996 = [23 1e 07 08 05 03 04 a0
23 1e 07 08 05 03 04 a0
23 1e 07 08 05 03 04 a0
23 1e 07 08 05 03 04 a0
23 18 07 08 04 03 04 a0];
};

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arch/arm/boot/dts/qcom/msmfalcon-mdss-pll.dtsi Normal file
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/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
&soc {
mdss_dsi0_pll: qcom,mdss_dsi_pll@c994400 {
compatible = "qcom,mdss_dsi_pll_msmfalcon";
status = "ok";
label = "MDSS DSI 0 PLL";
cell-index = <0>;
#clock-cells = <1>;
reg = <0xc994400 0x588>,
<0xc8c2300 0x8>;
reg-names = "pll_base", "gdsc_base";
gdsc-supply = <&gdsc_mdss>;
clocks = <&clock_mmss MMSS_MDSS_AHB_CLK>;
clock-names = "iface_clk";
clock-rate = <0>;
qcom,dsi-pll-ssc-en;
qcom,dsi-pll-ssc-mode = "down-spread";
qcom,platform-supply-entries {
#address-cells = <1>;
#size-cells = <0>;
qcom,platform-supply-entry@0 {
reg = <0>;
qcom,supply-name = "gdsc";
qcom,supply-min-voltage = <0>;
qcom,supply-max-voltage = <0>;
qcom,supply-enable-load = <0>;
qcom,supply-disable-load = <0>;
};
};
};
mdss_dsi1_pll: qcom,mdss_dsi_pll@c996400 {
compatible = "qcom,mdss_dsi_pll_msmfalcon";
status = "ok";
label = "MDSS DSI 1 PLL";
cell-index = <1>;
#clock-cells = <1>;
reg = <0xc996400 0x588>,
<0xc8c2300 0x8>;
reg-names = "pll_base", "gdsc_base";
gdsc-supply = <&gdsc_mdss>;
clocks = <&clock_mmss MMSS_MDSS_AHB_CLK>;
clock-names = "iface_clk";
clock-rate = <0>;
qcom,dsi-pll-ssc-en;
qcom,dsi-pll-ssc-mode = "down-spread";
qcom,platform-supply-entries {
#address-cells = <1>;
#size-cells = <0>;
qcom,platform-supply-entry@0 {
reg = <0>;
qcom,supply-name = "gdsc";
qcom,supply-min-voltage = <0>;
qcom,supply-max-voltage = <0>;
qcom,supply-enable-load = <0>;
qcom,supply-disable-load = <0>;
};
};
};
};

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arch/arm/boot/dts/qcom/msmfalcon-mdss.dtsi Normal file
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/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <dt-bindings/clock/mdss-pll-clk.h>
&soc {
mdss_mdp: qcom,mdss_mdp@c900000 {
compatible = "qcom,mdss_mdp";
status = "ok";
reg = <0x0c900000 0x90000>,
<0x0c9b0000 0x1040>;
reg-names = "mdp_phys", "vbif_phys";
interrupts = <0 83 0>;
interrupt-controller;
#interrupt-cells = <1>;
vdd-supply = <&gdsc_mdss>;
/* Bus Scale Settings */
qcom,msm-bus,name = "mdss_mdp";
qcom,msm-bus,num-cases = <3>;
qcom,msm-bus,num-paths = <2>;
qcom,msm-bus,vectors-KBps =
<22 512 0 0>, <23 512 0 0>,
<22 512 0 6400000>, <23 512 0 6400000>,
<22 512 0 6400000>, <23 512 0 6400000>;
/* Fudge factors */
qcom,mdss-ab-factor = <1 1>; /* 1 time */
qcom,mdss-ib-factor = <1 1>; /* 1 time */
qcom,mdss-clk-factor = <105 100>; /* 1.05 times */
qcom,max-mixer-width = <2560>;
qcom,max-pipe-width = <2560>;
qcom,max-dest-scaler-input-width = <2048>;
qcom,max-dest-scaler-output-width = <2560>;
/* VBIF QoS remapper settings*/
qcom,mdss-vbif-qos-rt-setting = <1 2 2 2>;
qcom,vbif-settings = <0x00ac 0x00000040>,
<0x00d0 0x00001010>; /* v1 only */
qcom,mdss-has-panic-ctrl;
qcom,mdss-per-pipe-panic-luts = <0x000f>,
<0xffff>,
<0xfffc>,
<0xff00>;
qcom,mdss-mdp-reg-offset = <0x00001000>;
qcom,max-bandwidth-low-kbps = <6600000>;
qcom,max-bandwidth-high-kbps = <6600000>;
qcom,max-bandwidth-per-pipe-kbps = <3100000>;
qcom,max-clk-rate = <412500000>;
qcom,mdss-default-ot-rd-limit = <32>;
qcom,mdss-default-ot-wr-limit = <40>;
qcom,mdss-dram-channels = <2>;
/* Bandwidth limit settings */
qcom,max-bw-settings = <1 6600000>, /* Default */
<2 4500000>; /* Camera */
qcom,mdss-pipe-vig-off = <0x00005000 0x00007000>;
qcom,mdss-pipe-dma-off = <0x00025000 0x00027000
0x00029000>;
qcom,mdss-pipe-cursor-off = <0x00035000>;
qcom,mdss-pipe-vig-xin-id = <0 4>;
qcom,mdss-pipe-dma-xin-id = <1 5 9>;
qcom,mdss-pipe-cursor-xin-id = <2>;
/* These Offsets are relative to
* "mdp_phys + mdp-reg-offset" address
*/
qcom,mdss-pipe-vig-clk-ctrl-offsets = <0x2ac 0 0>,
<0x2b4 0 0>;
qcom,mdss-pipe-dma-clk-ctrl-offsets = <0x2ac 8 12>,
<0x2b4 8 12>,
<0x2c4 8 12>;
qcom,mdss-pipe-cursor-clk-ctrl-offsets = <0x3a8 16 15>;
qcom,mdss-ctl-off = <0x00002000 0x00002200 0x00002400
0x00002600 0x00002800>;
qcom,mdss-mixer-intf-off = <0x00045000 0x00046000
0x00047000 0x0004a000>;
qcom,mdss-dspp-off = <0x00055000 0x00057000>;
qcom,mdss-wb-off = <0x00066000>;
qcom,mdss-intf-off = <0x0006b000 0x0006b800
0x0006c000 0x0006c800>;
qcom,mdss-pingpong-off = <0x00071000 0x00071800
0x00072000 0x00072800>;
qcom,mdss-slave-pingpong-off = <0x00073000>;
qcom,mdss-ppb-ctl-off = <0x00000330 0x00000338 0x00000370
0x00000374> ;
qcom,mdss-ppb-cfg-off = <0x00000334 0x0000033C>;
qcom,mdss-has-pingpong-split;
qcom,mdss-has-separate-rotator;
qcom,mdss-ad-off = <0x0079000 0x00079800>;
qcom,mdss-cdm-off = <0x0007a200>;
qcom,mdss-dsc-off = <0x00081000 0x00081400>;
qcom,mdss-wfd-mode = "intf";
qcom,mdss-has-source-split;
qcom,mdss-highest-bank-bit = <0x1>;
qcom,mdss-has-decimation;
qcom,mdss-idle-power-collapse-enabled;
clocks = <&clock_mmss MMSS_MNOC_AHB_CLK>,
<&clock_mmss MMSS_MDSS_AHB_CLK>,
<&clock_mmss MMSS_MDSS_AXI_CLK>,
<&clock_mmss MDP_CLK_SRC>,
<&clock_mmss MMSS_MDSS_MDP_CLK>,
<&clock_mmss MMSS_MDSS_VSYNC_CLK>,
<&clock_mmss MDP_CLK_SRC>;
clock-names = "mnoc_clk", "iface_clk", "bus_clk",
"core_clk_src", "core_clk", "vsync_clk",
"lut_clk";
qcom,mdp-settings = <0x01190 0x00000000>,
<0x012ac 0xc0000ccc>,
<0x012b4 0xc0000ccc>,
<0x012bc 0x00cccccc>,
<0x012c4 0x000000cc>,
<0x013a8 0x0cccc0c0>,
<0x013b0 0xccccc0c0>,
<0x013b8 0xcccc0000>,
<0x013d0 0x00cc0000>,
<0x0506c 0x00000000>,
<0x0706c 0x00000000>,
<0x0906c 0x00000000>,
<0x0b06c 0x00000000>,
<0x1506c 0x00000000>,
<0x1706c 0x00000000>,
<0x1906c 0x00000000>,
<0x1b06c 0x00000000>,
<0x2506c 0x00000000>,
<0x2706c 0x00000000>;
qcom,regs-dump-mdp = <0x01000 0x01458>,
<0x02000 0x02094>,
<0x02200 0x02294>,
<0x02400 0x02494>,
<0x02600 0x02694>,
<0x02800 0x02894>,
<0x05000 0x05154>,
<0x05a00 0x05b00>,
<0x07000 0x07154>,
<0x07a00 0x07b00>,
<0x25000 0x25184>,
<0x27000 0x27184>,
<0x29000 0x29184>,
<0x35000 0x35150>,
<0x45000 0x452bc>,
<0x46000 0x462bc>,
<0x47000 0x472bc>,
<0x4a000 0x4a2bc>,
<0x55000 0x5522c>,
<0x57000 0x5722c>,
<0x66000 0x662c0>,
<0x6b000 0x6b268>,
<0x6b800 0x6ba68>,
<0x6c000 0x6c268>,
<0x71000 0x710d4>,
<0x71800 0x718d4>,
<0x73000 0x730d4>,
<0x81000 0x81140>,
<0x81400 0x81540>;
qcom,regs-dump-names-mdp = "MDP",
"CTL_0", "CTL_1", "CTL_2", "CTL_3", "CTL_4",
"VIG0_SSPP", "VIG0", "VIG1_SSPP", "VIG1",
"DMA0_SSPP", "DMA1_SSPP","DMA2_SSPP",
"CURSOR0_SSPP",
"LAYER_0", "LAYER_1", "LAYER_2",
"LAYER_5",
"DSPP_0", "DSPP_1",
"WB_2",
"INTF_0", "INTF_1", "INTF_2",
"PP_0", "PP_1", "PP_4",
"DSC_0", "DSC_1";
/* buffer parameters to calculate prefill bandwidth */
qcom,mdss-prefill-outstanding-buffer-bytes = <0>;
qcom,mdss-prefill-y-buffer-bytes = <0>;
qcom,mdss-prefill-scaler-buffer-lines-bilinear = <2>;
qcom,mdss-prefill-scaler-buffer-lines-caf = <4>;
qcom,mdss-prefill-post-scaler-buffer-pixels = <2560>;
qcom,mdss-prefill-pingpong-buffer-pixels = <5120>;
qcom,mdss-pp-offsets {
qcom,mdss-sspp-mdss-igc-lut-off = <0x2000>;
qcom,mdss-sspp-vig-pcc-off = <0x1b00>;
qcom,mdss-sspp-rgb-pcc-off = <0x380>;
qcom,mdss-sspp-dma-pcc-off = <0x380>;
qcom,mdss-lm-pgc-off = <0x3c0>;
qcom,mdss-dspp-gamut-off = <0x1600>;
qcom,mdss-dspp-pcc-off = <0x1700>;
qcom,mdss-dspp-pgc-off = <0x17c0>;
};
qcom,mdss-scaler-offsets {
qcom,mdss-vig-scaler-off = <0xa00>;
qcom,mdss-vig-scaler-lut-off = <0xb00>;
qcom,mdss-has-dest-scaler;
qcom,mdss-dest-block-off = <0x00061000>;
qcom,mdss-dest-scaler-off = <0x800 0x1000>;
qcom,mdss-dest-scaler-lut-off = <0x900 0x1100>;
};
smmu_mdp_unsec: qcom,smmu_mdp_unsec_cb {
compatible = "qcom,smmu_mdp_unsec";
iommus = <&mmss_bimc_smmu 0>;
gdsc-mmagic-mdss-supply = <&gdsc_bimc_smmu>;
clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>,
<&clock_mmss MMSS_MNOC_AHB_CLK>,
<&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>,
<&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>;
clock-names = "mmss_noc_axi_clk",
"mmss_noc_ahb_clk",
"mmss_smmu_ahb_clk",
"mmss_smmu_axi_clk";
};
smmu_mdp_sec: qcom,smmu_mdp_sec_cb {
compatible = "qcom,smmu_mdp_sec";
iommus = <&mmss_bimc_smmu 1>;
gdsc-mmagic-mdss-supply = <&gdsc_bimc_smmu>;
clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>,
<&clock_mmss MMSS_MNOC_AHB_CLK>,
<&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>,
<&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>;
clock-names = "mmss_noc_axi_clk",
"mmss_noc_ahb_clk",
"mmss_smmu_ahb_clk",
"mmss_smmu_axi_clk";
};
mdss_fb0: qcom,mdss_fb_primary {
cell-index = <0>;
compatible = "qcom,mdss-fb";
};
mdss_fb1: qcom,mdss_fb_wfd {
cell-index = <1>;
compatible = "qcom,mdss-fb";
};
mdss_fb2: qcom,mdss_fb_dp {
cell-index = <2>;
compatible = "qcom,mdss-fb";
qcom,mdss-intf = <&mdss_dp_ctrl>;
};
};
mdss_dsi: qcom,mdss_dsi@0 {
compatible = "qcom,mdss-dsi";
#address-cells = <1>;
#size-cells = <1>;
gdsc-supply = <&gdsc_mdss>;
vdda-1p2-supply = <&pmfalcon_l1>;
vdda-0p9-supply = <&pm2falcon_l1>;
ranges = <0xc994000 0xc994000 0x400
0xc994400 0xc994400 0x588
0xc828000 0xc828000 0xac
0xc996000 0xc996000 0x400
0xc996400 0xc996400 0x588
0xc828000 0xc828000 0xac>;
/* Bus Scale Settings */
qcom,msm-bus,name = "mdss_dsi";
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<22 512 0 0>,
<22 512 0 1000>;
qcom,mmss-ulp-clamp-ctrl-offset = <0x14>;
clocks = <&clock_mmss MMSS_MDSS_MDP_CLK>,
<&clock_mmss MMSS_MNOC_AHB_CLK>,
<&clock_mmss MMSS_MDSS_AHB_CLK>,
<&clock_mmss MMSS_MDSS_AXI_CLK>,
<&clock_mmss MMSS_MISC_AHB_CLK>,
<&mdss_dsi0_pll BYTE0_MUX_CLK>,
<&mdss_dsi1_pll BYTE1_MUX_CLK>,
<&mdss_dsi0_pll PIX0_MUX_CLK>,
<&mdss_dsi1_pll PIX1_MUX_CLK>;
clock-names = "mdp_core_clk",
"mnoc_clk", "iface_clk",
"bus_clk", "core_mmss_clk",
"ext_byte0_clk", "ext_byte1_clk",
"ext_pixel0_clk", "ext_pixel1_clk";
qcom,core-supply-entries {
#address-cells = <1>;
#size-cells = <0>;
qcom,core-supply-entry@0 {
reg = <0>;
qcom,supply-name = "gdsc";
qcom,supply-min-voltage = <0>;
qcom,supply-max-voltage = <0>;
qcom,supply-enable-load = <0>;
qcom,supply-disable-load = <0>;
};
};
qcom,ctrl-supply-entries {
#address-cells = <1>;
#size-cells = <0>;
qcom,ctrl-supply-entry@0 {
reg = <0>;
qcom,supply-name = "vdda-1p2";
qcom,supply-min-voltage = <1200000>;
qcom,supply-max-voltage = <1250000>;
qcom,supply-enable-load = <12560>;
qcom,supply-disable-load = <4>;
};
};
qcom,phy-supply-entries {
#address-cells = <1>;
#size-cells = <0>;
qcom,phy-supply-entry@0 {
reg = <0>;
qcom,supply-name = "vdda-0p9";
qcom,supply-min-voltage = <880000>;
qcom,supply-max-voltage = <925000>;
qcom,supply-enable-load = <73400>;
qcom,supply-disable-load = <32>;
};
};
mdss_dsi0: qcom,mdss_dsi_ctrl0@c994000 {
compatible = "qcom,mdss-dsi-ctrl";
label = "MDSS DSI CTRL->0";
cell-index = <0>;
reg = <0xc994000 0x400>,
<0xc994400 0x588>,
<0xc828000 0xac>;
reg-names = "dsi_ctrl", "dsi_phy", "mmss_misc_phys";
qcom,timing-db-mode;
wqhd-vddio-supply = <&pmfalcon_l11>;
lab-supply = <&lcdb_ldo_vreg>;
ibb-supply = <&lcdb_ncp_vreg>;
qcom,mdss-mdp = <&mdss_mdp>;
qcom,mdss-fb-map = <&mdss_fb0>;
clocks = <&clock_mmss MMSS_MDSS_BYTE0_CLK>,
<&clock_mmss MMSS_MDSS_PCLK0_CLK>,
<&clock_mmss MMSS_MDSS_ESC0_CLK>,
<&clock_mmss BYTE0_CLK_SRC>,
<&clock_mmss PCLK0_CLK_SRC>,
<&clock_mmss MMSS_MDSS_BYTE0_INTF_CLK>;
clock-names = "byte_clk", "pixel_clk", "core_clk",
"byte_clk_rcg", "pixel_clk_rcg",
"byte_intf_clk";
qcom,platform-strength-ctrl = [ff 06
ff 06
ff 06
ff 06
ff 00];
qcom,platform-regulator-settings = [1d
1d 1d 1d 1d];
qcom,platform-lane-config = [00 00 10 0f
00 00 10 0f
00 00 10 0f
00 00 10 0f
00 00 10 8f];
};
mdss_dsi1: qcom,mdss_dsi_ctrl1@c996000 {
compatible = "qcom,mdss-dsi-ctrl";
label = "MDSS DSI CTRL->1";
cell-index = <1>;
reg = <0xc996000 0x400>,
<0xc996400 0x588>,
<0xc828000 0xac>;
reg-names = "dsi_ctrl", "dsi_phy", "mmss_misc_phys";
qcom,timing-db-mode;
wqhd-vddio-supply = <&pmfalcon_l11>;
lab-supply = <&lcdb_ldo_vreg>;
ibb-supply = <&lcdb_ncp_vreg>;
qcom,mdss-mdp = <&mdss_mdp>;
qcom,mdss-fb-map = <&mdss_fb0>;
clocks = <&clock_mmss MMSS_MDSS_BYTE1_CLK>,
<&clock_mmss MMSS_MDSS_PCLK1_CLK>,
<&clock_mmss MMSS_MDSS_ESC1_CLK>,
<&clock_mmss BYTE1_CLK_SRC>,
<&clock_mmss PCLK1_CLK_SRC>,
<&clock_mmss MMSS_MDSS_BYTE1_INTF_CLK>;
clock-names = "byte_clk", "pixel_clk", "core_clk",
"byte_clk_rcg", "pixel_clk_rcg",
"byte_intf_clk";
qcom,platform-strength-ctrl = [ff 06
ff 06
ff 06
ff 06
ff 00];
qcom,platform-regulator-settings = [1d
1d 1d 1d 1d];
qcom,platform-lane-config = [00 00 10 0f
00 00 10 0f
00 00 10 0f
00 00 10 0f
00 00 10 8f];
};
};
qcom,mdss_wb_panel {
compatible = "qcom,mdss_wb";
qcom,mdss_pan_res = <640 480>;
qcom,mdss_pan_bpp = <24>;
qcom,mdss-fb-map = <&mdss_fb1>;
};
msm_ext_disp: qcom,msm_ext_disp {
status = "disabled";
compatible = "qcom,msm-ext-disp";
ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx {
compatible = "qcom,msm-ext-disp-audio-codec-rx";
qcom,msm_ext_disp = <&msm_ext_disp>;
};
};
mdss_dp_ctrl: qcom,dp_ctrl@c990000 {
status = "disabled";
cell-index = <0>;
compatible = "qcom,mdss-dp";
qcom,mdss-fb-map = <&mdss_fb2>;
gdsc-supply = <&gdsc_mdss>;
vdda-1p2-supply = <&pmfalcon_l1>;
vdda-0p9-supply = <&pm2falcon_l1>;
reg = <0xc990000 0xa84>,
<0xc011000 0x910>,
<0x1fcb200 0x050>,
<0xc8c2200 0x1a0>,
<0x780000 0x621c>,
<0xc9e1000 0x02c>;
reg-names = "dp_ctrl", "dp_phy", "tcsr_regs", "dp_mmss_cc",
"qfprom_physical","hdcp_physical";
qcom,msm_ext_disp = <&msm_ext_disp>;
qcom,core-supply-entries {
#address-cells = <1>;
#size-cells = <0>;
qcom,core-supply-entry@0 {
reg = <0>;
qcom,supply-name = "gdsc";
qcom,supply-min-voltage = <0>;
qcom,supply-max-voltage = <0>;
qcom,supply-enable-load = <0>;
qcom,supply-disable-load = <0>;
};
};
qcom,ctrl-supply-entries {
#address-cells = <1>;
#size-cells = <0>;
qcom,ctrl-supply-entry@0 {
reg = <0>;
qcom,supply-name = "vdda-1p2";
qcom,supply-min-voltage = <1200000>;
qcom,supply-max-voltage = <1250000>;
qcom,supply-enable-load = <12560>;
qcom,supply-disable-load = <4>;
};
};
qcom,phy-supply-entries {
#address-cells = <1>;
#size-cells = <0>;
qcom,phy-supply-entry@0 {
reg = <0>;
qcom,supply-name = "vdda-0p9";
qcom,supply-min-voltage = <880000>;
qcom,supply-max-voltage = <925000>;
qcom,supply-enable-load = <73400>;
qcom,supply-disable-load = <32>;
};
};
};
mdss_rotator: qcom,mdss_rotator {
compatible = "qcom,sde_rotator";
reg = <0x0c900000 0xab100>,
<0x0c9b0000 0x1040>;
reg-names = "mdp_phys",
"rot_vbif_phys";
qcom,mdss-rot-mode = <1>;
qcom,mdss-highest-bank-bit = <0x2>;
/* Bus Scale Settings */
qcom,msm-bus,name = "mdss_rotator";
qcom,msm-bus,num-cases = <3>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<22 512 0 0>,
<22 512 0 6400000>,
<22 512 0 6400000>;
rot-vdd-supply = <&gdsc_mdss>;
qcom,supply-names = "rot-vdd";
clocks = <&clock_mmss MMSS_MNOC_AHB_CLK>,
<&clock_mmss MMSS_MDSS_AHB_CLK>,
<&clock_mmss ROT_CLK_SRC>,
<&clock_mmss MMSS_MDSS_ROT_CLK>,
<&clock_mmss MMSS_MDSS_AXI_CLK>;
clock-names = "mnoc_clk",
"iface_clk", "rot_core_clk",
"rot_clk", "axi_clk";
interrupt-parent = <&mdss_mdp>;
interrupts = <2 0>;
/* VBIF QoS remapper settings*/
qcom,mdss-rot-vbif-qos-setting = <1 1 1 1>;
qcom,mdss-default-ot-rd-limit = <32>;
qcom,mdss-default-ot-wr-limit = <40>;
smmu_rot_unsec: qcom,smmu_rot_unsec_cb {
compatible = "qcom,smmu_sde_rot_unsec";
iommus = <&mmss_bimc_smmu 0xe00>;
gdsc-mdss-supply = <&gdsc_bimc_smmu>;
clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>,
<&clock_mmss MMSS_MNOC_AHB_CLK>,
<&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>,
<&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>;
clock-names = "mmss_noc_axi_clk",
"mmss_noc_ahb_clk",
"mmss_smmu_ahb_clk",
"mmss_smmu_axi_clk";
};
smmu_rot_sec: qcom,smmu_rot_sec_cb {
compatible = "qcom,smmu_sde_rot_sec";
iommus = <&mmss_bimc_smmu 0xe01>;
gdsc-mdss-supply = <&gdsc_bimc_smmu>;
clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>,
<&clock_mmss MMSS_MNOC_AHB_CLK>,
<&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>,
<&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>;
clock-names = "mmss_noc_axi_clk",
"mmss_noc_ahb_clk",
"mmss_smmu_ahb_clk",
"mmss_smmu_axi_clk";
};
};
};
#include "msmfalcon-mdss-panels.dtsi"

4
arch/arm/boot/dts/qcom/msmfalcon-mtp.dts
View file

@ -17,7 +17,9 @@
#include "msmfalcon-mtp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. MSM FALCON MTP";
model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM2FALCON MTP";
compatible = "qcom,msmfalcon-mtp", "qcom,msmfalcon", "qcom,mtp";
qcom,board-id = <8 0>;
qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>,
<0x0001001b 0x0201011a 0x0 0x0>;
};

50
arch/arm/boot/dts/qcom/msmfalcon-mtp.dtsi
View file

@ -42,8 +42,58 @@
status = "ok";
};
&mdss_mdp {
qcom,mdss-pref-prim-intf = "dsi";
};
&mdss_dsi {
hw-config = "split_dsi";
};
&mdss_dsi0 {
qcom,dsi-pref-prim-pan = <&dsi_dual_nt35597_truly_video>;
pinctrl-names = "mdss_default", "mdss_sleep";
pinctrl-0 = <&mdss_dsi_active &mdss_te_active>;
pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>;
qcom,platform-reset-gpio = <&tlmm 53 0>;
qcom,platform-te-gpio = <&tlmm 59 0>;
};
&mdss_dsi1 {
qcom,dsi-pref-prim-pan = <&dsi_dual_nt35597_truly_video>;
pinctrl-names = "mdss_default", "mdss_sleep";
pinctrl-0 = <&mdss_dsi_active &mdss_te_active>;
pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>;
qcom,platform-reset-gpio = <&tlmm 53 0>;
qcom,platform-te-gpio = <&tlmm 59 0>;
};
&pm2falcon_wled {
qcom,led-strings-list = [01 02];
};
&dsi_dual_nt35597_truly_video {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
qcom,mdss-dsi-bl-min-level = <1>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-dsi-mode-sel-gpio-state = "dual_port";
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
};
&dsi_dual_nt35597_truly_cmd {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
qcom,mdss-dsi-bl-min-level = <1>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-dsi-mode-sel-gpio-state = "dual_port";
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
};
&soc {
qcom,msm-ssc-sensors {
compatible = "qcom,msm-ssc-sensors";
};
};
&mem_client_3_size {
qcom,peripheral-size = <0x500000>;
};

53
arch/arm/boot/dts/qcom/msmfalcon-pinctrl.dtsi
View file

@ -1196,6 +1196,59 @@
};
};
pmx_mdss: pmx_mdss {
mdss_dsi_active: mdss_dsi_active {
mux {
pins = "gpio53";
function = "gpio";
};
config {
pins = "gpio53";
drive-strength = <8>; /* 8 mA */
bias-disable = <0>; /* no pull */
};
};
mdss_dsi_suspend: mdss_dsi_suspend {
mux {
pins = "gpio53";
function = "gpio";
};
config {
pins = "gpio53";
drive-strength = <2>; /* 2 mA */
bias-pull-down; /* pull down */
};
};
};
pmx_mdss_te {
mdss_te_active: mdss_te_active {
mux {
pins = "gpio59";
function = "mdp_vsync_p";
};
config {
pins = "gpio59";
drive-strength = <2>; /* 8 mA */
bias-pull-down; /* pull down*/
};
};
mdss_te_suspend: mdss_te_suspend {
mux {
pins = "gpio59";
function = "mdp_vsync_p";
};
config {
pins = "gpio59";
drive-strength = <2>; /* 2 mA */
bias-pull-down; /* pull down */
};
};
};
ts_mux {
ts_active: ts_active {
mux {

25
arch/arm/boot/dts/qcom/msmfalcon-pm3falcon-cdp.dts Normal file
View file

@ -0,0 +1,25 @@
/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/dts-v1/;
#include "msmfalcon.dtsi"
#include "msmfalcon-cdp.dtsi"
#include "msm-pm3falcon.dtsi"
/ {
model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM3FALCON CDP";
compatible = "qcom,msmfalcon-cdp", "qcom,msmfalcon", "qcom,cdp";
qcom,board-id = <1 0>;
qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>;
};

25
arch/arm/boot/dts/qcom/msmfalcon-pm3falcon-mtp.dts Normal file
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@ -0,0 +1,25 @@
/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/dts-v1/;
#include "msmfalcon.dtsi"
#include "msmfalcon-mtp.dtsi"
#include "msm-pm3falcon.dtsi"
/ {
model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM3FALCON MTP";
compatible = "qcom,msmfalcon-mtp", "qcom,msmfalcon", "qcom,mtp";
qcom,board-id = <8 0>;
qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>;
};

25
arch/arm/boot/dts/qcom/msmfalcon-pm3falcon-qrd.dts Normal file
View file

@ -0,0 +1,25 @@
/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/dts-v1/;
#include "msmfalcon.dtsi"
#include "msmfalcon-qrd.dtsi"
#include "msm-pm3falcon.dtsi"
/ {
model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM3FALCON QRD";
compatible = "qcom,msmfalcon-qrd", "qcom,msmfalcon", "qcom,qrd";
qcom,board-id = <0x1000b 0>;
qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>;
};

25
arch/arm/boot/dts/qcom/msmfalcon-pm3falcon-rcm.dts Normal file
View file

@ -0,0 +1,25 @@
/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/dts-v1/;
#include "msmfalcon.dtsi"
#include "msmfalcon-cdp.dtsi"
#include "msm-pm3falcon.dtsi"
/ {
model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM3FALCON RCM";
compatible = "qcom,msmfalcon-cdp", "qcom,msmfalcon", "qcom,cdp";
qcom,board-id = <21 0>;
qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>;
};

146
arch/arm/boot/dts/qcom/msmfalcon-pm3falcon-rumi.dts Normal file
View file

@ -0,0 +1,146 @@
/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/dts-v1/;
#include "msmfalcon.dtsi"
#include "msmfalcon-pinctrl.dtsi"
#include "msm-pm3falcon.dtsi"
/ {
model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM3FALCON RUMI";
compatible = "qcom,msmfalcon-rumi", "qcom,msmfalcon", "qcom,rumi";
qcom,board-id = <15 0>;
qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>;
chosen {
bootargs = "lpm_levels.sleep_disabled=1";
};
};
&usb3 {
/delete-property/ USB3_GDSC-supply;
/delete-property/ extcon;
dwc3@a800000 {
maximum-speed = "high-speed";
};
};
&ssphy {
compatible = "usb-nop-xceiv";
};
&qusb_phy0 {
reg = <0x0a928000 0x8000>,
<0x0a8f8800 0x400>,
<0x0a920000 0x100>;
reg-names = "qusb_phy_base",
"qscratch_base",
"emu_phy_base";
qcom,emulation;
qcom,qusb-phy-init-seq = <0x19 0x1404
0x20 0x1414
0x79 0x1410
0x00 0x1418
0x99 0x1404
0x04 0x1408
0xd9 0x1404>;
qcom,emu-dcm-reset-seq = <0x100000 0x20
0x0 0x20
0x1a0 0x20
0x5 0x14>;
};
&uartblsp1dm1 {
status = "ok";
pinctrl-names = "default";
pinctrl-0 = <&uart_console_active>;
};
&sdhc_1 {
/* device core power supply */
vdd-supply = <&pm2falcon_l4>;
qcom,vdd-voltage-level = <2950000 2950000>;
qcom,vdd-current-level = <200 570000>;
/* device communication power supply */
vdd-io-supply = <&pmfalcon_l8>;
qcom,vdd-io-always-on;
qcom,vdd-io-lpm-sup;
qcom,vdd-io-voltage-level = <1800000 1800000>;
qcom,vdd-io-current-level = <200 325000>;
pinctrl-names = "active", "sleep";
pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
qcom,clk-rates = <400000 20000000 25000000 50000000 192000000
384000000>;
qcom,nonremovable;
qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v";
status = "ok";
};
&clock_gcc {
compatible = "qcom,dummycc";
clock-output-names = "gcc_clocks";
};
&pmfalcon_charger {
status = "disabled";
};
&pmfalcon_fg {
status = "disabled";
};
&clock_gfx {
compatible = "qcom,dummycc";
clock-output-names = "gfx_clocks";
};
&pmfalcon_pdphy {
status = "disabled";
};
&clock_mmss {
compatible = "qcom,dummycc";
clock-output-names = "mmss_clocks";
};
&ufsphy1 {
vdda-phy-supply = <&pm2falcon_l1>;
vdda-pll-supply = <&pmfalcon_l10>;
vddp-ref-clk-supply = <&pmfalcon_l1>;
vdda-phy-max-microamp = <51400>;
vdda-pll-max-microamp = <14200>;
vddp-ref-clk-max-microamp = <100>;
vddp-ref-clk-always-on;
};
&ufs1 {
vdd-hba-supply = <&gdsc_ufs>;
vdd-hba-fixed-regulator;
vcc-supply = <&pm2falcon_l4>;
vccq2-supply = <&pmfalcon_l8>;
vcc-max-microamp = <500000>;
vccq2-max-microamp = <600000>;
qcom,disable-lpm;
};
&clock_debug {
compatible = "qcom,dummycc";
clock-output-names = "debug_clocks";
};

111
arch/arm/boot/dts/qcom/msmfalcon-pm3falcon-sim.dts Normal file
View file

@ -0,0 +1,111 @@
/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/dts-v1/;
#include "msmfalcon.dtsi"
#include "msmfalcon-pinctrl.dtsi"
#include "msm-pm3falcon.dtsi"
/ {
model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM3FALCON SIM";
compatible = "qcom,msmfalcon-sim", "qcom,msmfalcon", "qcom,sim";
qcom,board-id = <16 0>;
qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>;
chosen {
bootargs = "lpm_levels.sleep_disabled=1";
};
};
&usb3 {
reg = <0xa800000 0xfc000>;
reg-names = "core_base";
/delete-property/ extcon;
dwc3@a800000 {
maximum-speed = "high-speed";
};
};
&ssphy {
compatible = "usb-nop-xceiv";
};
&qusb_phy0 {
compatible = "usb-nop-xceiv";
};
&uartblsp1dm1 {
status = "ok";
pinctrl-names = "default";
pinctrl-0 = <&uart_console_active>;
};
&sdhc_1 {
/* device core power supply */
vdd-supply = <&pm2falcon_l4>;
qcom,vdd-voltage-level = <2950000 2950000>;
qcom,vdd-current-level = <200 570000>;
/* device communication power supply */
vdd-io-supply = <&pmfalcon_l8>;
qcom,vdd-io-always-on;
qcom,vdd-io-lpm-sup;
qcom,vdd-io-voltage-level = <1800000 1800000>;
qcom,vdd-io-current-level = <200 325000>;
pinctrl-names = "active", "sleep";
pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
qcom,clk-rates = <400000 20000000 25000000 50000000 192000000
384000000>;
qcom,nonremovable;
qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v";
status = "ok";
};
&pmfalcon_charger {
status = "disabled";
};
&pmfalcon_fg {
status = "disabled";
};
&pmfalcon_pdphy {
status = "disabled";
};
&ufsphy1 {
vdda-phy-supply = <&pm2falcon_l1>;
vdda-pll-supply = <&pmfalcon_l10>;
vddp-ref-clk-supply = <&pmfalcon_l1>;
vdda-phy-max-microamp = <51400>;
vdda-pll-max-microamp = <14200>;
vddp-ref-clk-max-microamp = <100>;
vddp-ref-clk-always-on;
status = "ok";
};
&ufs1 {
vdd-hba-supply = <&gdsc_ufs>;
vdd-hba-fixed-regulator;
vcc-supply = <&pm2falcon_l4>;
vccq2-supply = <&pmfalcon_l8>;
vcc-max-microamp = <500000>;
vccq2-max-microamp = <600000>;
status = "ok";
};

4
arch/arm/boot/dts/qcom/msmfalcon-qrd.dts
View file

@ -17,7 +17,9 @@
#include "msmfalcon-qrd.dtsi"
/ {
model = "Qualcomm Technologies, Inc. MSM FALCON QRD";
model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM2FALCON QRD";
compatible = "qcom,msmfalcon-qrd", "qcom,msmfalcon", "qcom,qrd";
qcom,board-id = <0x1000b 0>;
qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>,
<0x0001001b 0x0201011a 0x0 0x0>;
};

4
arch/arm/boot/dts/qcom/msmfalcon-rcm.dts
View file

@ -17,7 +17,9 @@
#include "msmfalcon-cdp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. MSM FALCON RCM";
model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM2FALCON RCM";
compatible = "qcom,msmfalcon-cdp", "qcom,msmfalcon", "qcom,cdp";
qcom,board-id = <21 0>;
qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>,
<0x0001001b 0x0201011a 0x0 0x0>;
};

4
arch/arm/boot/dts/qcom/msmfalcon-rumi.dts
View file

@ -17,9 +17,11 @@
#include "msmfalcon-pinctrl.dtsi"
/ {
model = "Qualcomm Technologies, Inc. MSM FALCON RUMI";
model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM2FALCON RUMI";
compatible = "qcom,msmfalcon-rumi", "qcom,msmfalcon", "qcom,rumi";
qcom,board-id = <15 0>;
qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>,
<0x0001001b 0x0201011a 0x0 0x0>;
chosen {
bootargs = "lpm_levels.sleep_disabled=1";

4
arch/arm/boot/dts/qcom/msmfalcon-sim.dts
View file

@ -17,9 +17,11 @@
#include "msmfalcon-pinctrl.dtsi"
/ {
model = "Qualcomm Technologies, Inc. MSM FALCON SIM";
model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM2FALCON SIM";
compatible = "qcom,msmfalcon-sim", "qcom,msmfalcon", "qcom,sim";
qcom,board-id = <16 0>;
qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>,
<0x0001001b 0x0201011a 0x0 0x0>;
chosen {
bootargs = "lpm_levels.sleep_disabled=1";

18
arch/arm/boot/dts/qcom/msmfalcon-vidc.dtsi
View file

@ -14,6 +14,8 @@
#include <dt-bindings/msm/msm-bus-ids.h>
#include <dt-bindings/clock/qcom,gcc-msmfalcon.h>
#include <dt-bindings/clock/qcom,mmcc-msmfalcon.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
&soc {
msm_vidc: qcom,vidc@cc00000 {
@ -25,16 +27,10 @@
qcom,hfi-version = "3xx";
qcom,firmware-name = "venus";
qcom,sw-power-collapse;
qcom,debug-timeout;
qcom,reg-presets =
<0x80124 0x00000003>,
<0x80550 0x01111111>,
<0x80560 0x01111111>,
<0x80568 0x01111111>,
<0x80570 0x01111111>,
<0x80580 0x01111111>,
<0x80588 0x01111111>,
<0xe2010 0x00000000>;
<0x80010 0x00000003>,
<0x80018 0x05555556>,
<0x8001c 0x05555556>;
qcom,max-hw-load = <1036800>; /* Full 4k @ 30 */
qcom,allowed-clock-rates =
@ -70,7 +66,7 @@
"mmss_video_axi_clk",
"mmss_video_core0_clk";
clocks = <&clock_gcc GCC_MMSS_SYS_NOC_AXI_CLK>,
<&clock_gcc MMSSNOC_AXI_CLK>,
<&clock_rpmcc MMSSNOC_AXI_CLK>,
<&clock_mmss MMSS_MNOC_AHB_CLK>,
<&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>,
<&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>,
@ -210,7 +206,7 @@
<&mmss_bimc_smmu 0x411>,
<&mmss_bimc_smmu 0x431>;
buffer-types = <0xfff>;
virtual-addr-pool = <0x70800000 0x8f800000>;
virtual-addr-pool = <0x70800000 0x6f800000>;
};
firmware_cb {

229
arch/arm/boot/dts/qcom/msmfalcon.dtsi
View file

@ -32,6 +32,7 @@
chosen {
stdout-path = "serial0";
bootargs = "rcupdate.rcu_expedited=1";
};
psci {
@ -952,6 +953,231 @@
#clock-cells = <1>;
};
cpubw: qcom,cpubw {
compatible = "qcom,devbw";
governor = "performance";
qcom,src-dst-ports = <1 512>;
qcom,active-only;
qcom,bw-tbl =
< 762 /* 100 MHz */ >,
< 1144 /* 150 MHz */ >,
< 1525 /* 200 MHz */ >,
< 2288 /* 300 MHz */ >,
< 3143 /* 412 MHz */ >,
< 4173 /* 547 MHz */ >,
< 5195 /* 681 MHz */ >,
< 5859 /* 768 MHz */ >,
< 7759 /* 1017 MHz */ >,
< 9887 /* 1296 MHz */ >,
< 10327 /* 1353 MHz */ >,
< 11863 /* 1555 MHz */ >,
< 13763 /* 1804 MHz */ >;
};
bwmon: qcom,cpu-bwmon {
compatible = "qcom,bimc-bwmon3";
reg = <0x01008000 0x300>, <0x01001000 0x200>;
reg-names = "base", "global_base";
interrupts = <0 183 4>;
qcom,mport = <0>;
qcom,target-dev = <&cpubw>;
};
mincpubw: qcom,mincpubw {
compatible = "qcom,devbw";
governor = "powersave";
qcom,src-dst-ports = <1 512>;
qcom,active-only;
qcom,bw-tbl =
< 762 /* 100 MHz */ >,
< 1144 /* 150 MHz */ >,
< 1525 /* 200 MHz */ >,
< 2288 /* 300 MHz */ >,
< 3143 /* 412 MHz */ >,
< 4173 /* 547 MHz */ >,
< 5195 /* 681 MHz */ >,
< 5859 /* 768 MHz */ >,
< 7759 /* 1017 MHz */ >,
< 9887 /* 1296 MHz */ >,
< 10327 /* 1353 MHz */ >,
< 11863 /* 1555 MHz */ >,
< 13763 /* 1804 MHz */ >;
};
memlat_cpu0: qcom,memlat-cpu0 {
compatible = "qcom,devbw";
governor = "powersave";
qcom,src-dst-ports = <1 512>;
qcom,active-only;
qcom,bw-tbl =
< 762 /* 100 MHz */ >,
< 1144 /* 150 MHz */ >,
< 1525 /* 200 MHz */ >,
< 2288 /* 300 MHz */ >,
< 3143 /* 412 MHz */ >,
< 4173 /* 547 MHz */ >,
< 5195 /* 681 MHz */ >,
< 5859 /* 768 MHz */ >,
< 7759 /* 1017 MHz */ >,
< 9887 /* 1296 MHz */ >,
< 10327 /* 1353 MHz */ >,
< 11863 /* 1555 MHz */ >,
< 13763 /* 1804 MHz */ >;
};
memlat_cpu4: qcom,memlat-cpu4 {
compatible = "qcom,devbw";
governor = "powersave";
qcom,src-dst-ports = <1 512>;
qcom,active-only;
qcom,bw-tbl =
< 762 /* 100 MHz */ >,
< 1144 /* 150 MHz */ >,
< 1525 /* 200 MHz */ >,
< 2288 /* 300 MHz */ >,
< 3143 /* 412 MHz */ >,
< 4173 /* 547 MHz */ >,
< 5195 /* 681 MHz */ >,
< 5859 /* 768 MHz */ >,
< 7759 /* 1017 MHz */ >,
< 9887 /* 1296 MHz */ >,
< 10327 /* 1353 MHz */ >,
< 11863 /* 1555 MHz */ >,
< 13763 /* 1804 MHz */ >;
};
devfreq_memlat_0: qcom,arm-memlat-mon-0 {
compatible = "qcom,arm-memlat-mon";
qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
qcom,target-dev = <&memlat_cpu0>;
qcom,core-dev-table =
< 633600 1525 >,
< 1401600 4173 >,
< 1881600 7759 >;
};
devfreq_memlat_4: qcom,arm-memlat-mon-4 {
compatible = "qcom,arm-memlat-mon";
qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
qcom,target-dev = <&memlat_cpu4>;
qcom,core-dev-table =
< 1113600 1525 >,
< 1401600 7759 >,
< 2150400 11863 >,
< 2457600 13763 >;
};
devfreq_cpufreq: devfreq-cpufreq {
mincpubw-cpufreq {
target-dev = <&mincpubw>;
cpu-to-dev-map-0 =
< 633600 1525 >,
< 1401600 3143 >,
< 1881600 5859 >;
cpu-to-dev-map-4 =
< 1113600 1525 >,
< 1401600 4173 >,
< 1747200 5859 >,
< 2150400 7759 >,
< 2457600 13763 >;
};
};
clock_cpu: qcom,clk-cpu-falcon@179c0000 {
compatible = "qcom,clk-cpu-osm";
status = "disabled";
reg = <0x179c0000 0x4000>, <0x17916000 0x1000>,
<0x17816000 0x1000>, <0x179d1000 0x1000>,
<0x00784130 0x8>;
reg-names = "osm", "pwrcl_pll", "perfcl_pll",
"apcs_common", "perfcl_efuse";
/* ToDo: Add power and perf supply rails */
interrupts = <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 36 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "pwrcl-irq", "perfcl-irq";
qcom,pwrcl-speedbin0-v0 =
< 300000000 0x0004000f 0x01200020 0x1 1 >,
< 633600000 0x05040021 0x03200020 0x1 1 >,
< 902400000 0x0404002f 0x04260026 0x1 2 >,
< 1113600000 0x0404003a 0x052e002e 0x2 3 >,
< 1401600000 0x04040049 0x073a003a 0x2 4 >,
< 1536000000 0x04040050 0x08400040 0x3 5 >,
< 1747200000 0x0404005b 0x09480048 0x3 6 >,
< 1843200000 0x04040060 0x094c004c 0x3 7 >;
qcom,perfcl-speedbin0-v0 =
< 300000000 0x0004000f 0x01200020 0x1 1 >,
< 1113600000 0x0404003a 0x052e002e 0x1 1 >,
< 1401600000 0x04040049 0x073a003a 0x2 2 >,
< 1747200000 0x0404005b 0x09480048 0x2 3 >,
< 1958400000 0x04040066 0x0a510051 0x3 4 >,
< 2150400000 0x04040070 0x0b590059 0x3 5 >,
< 2457600000 0x04040080 0x0c660066 0x3 6 >;
qcom,perfcl-speedbin1-v0 =
< 300000000 0x0004000f 0x01200020 0x1 1 >,
< 1113600000 0x0404003a 0x052e002e 0x1 1 >,
< 1401600000 0x04040049 0x073a003a 0x2 2 >,
< 1747200000 0x0404005b 0x09480048 0x2 3 >,
< 1958400000 0x04040066 0x0a510051 0x3 4 >,
< 2150400000 0x04040070 0x0b590059 0x3 5 >,
< 2208000000 0x04040073 0x0b5c005c 0x3 6 >;
qcom,up-timer = <1000 1000>;
qcom,down-timer = <1000 1000>;
qcom,pc-override-index = <0 0>;
qcom,set-ret-inactive;
qcom,enable-llm-freq-vote;
qcom,llm-freq-up-timer = <327675 327675>;
qcom,llm-freq-down-timer = <327675 327675>;
qcom,enable-llm-volt-vote;
qcom,llm-volt-up-timer = <327675 327675>;
qcom,llm-volt-down-timer = <327675 327675>;
qcom,cc-reads = <10>;
qcom,cc-delay = <5>;
qcom,cc-factor = <100>;
qcom,osm-clk-rate = <200000000>;
qcom,xo-clk-rate = <19200000>;
qcom,l-val-base = <0x17916004 0x17816004>;
qcom,apcs-itm-present = <0x179d143c 0x179d143c>;
qcom,apcs-pll-user-ctl = <0x1791600c 0x1781600c>;
qcom,apcs-cfg-rcgr = <0x17911054 0x17811054>;
qcom,apcs-cmd-rcgr = <0x17911050 0x17811050>;
qcom,apm-mode-ctl = <0x179d0004 0x179d0010>;
qcom,apm-ctrl-status = <0x179d000c 0x179d0018>;
qcom,apm-threshold-voltage = <832000>;
qcom,boost-fsm-en;
qcom,safe-fsm-en;
qcom,ps-fsm-en;
qcom,droop-fsm-en;
qcom,wfx-fsm-en;
qcom,pc-fsm-en;
qcom,pwrcl-apcs-mem-acc-cfg =
<0x179d1360 0x179d1364 0x179d1364>;
qcom,perfcl-apcs-mem-acc-cfg =
<0x179d1368 0x179d136C 0x179d1370>;
qcom,pwrcl-apcs-mem-acc-val =
<0x00000000 0x80000000 0x80000000>,
<0x00000000 0x00000000 0x00000000>,
<0x00000000 0x00000001 0x00000001>;
qcom,perfcl-apcs-mem-acc-val =
<0x00000000 0x00000000 0x80000000>,
<0x00000000 0x00000000 0x00000000>,
<0x00000000 0x00000000 0x00000001>;
clock-names = "aux_clk", "xo_a";
clocks = <&clock_gcc HMSS_GPLL0_CLK_SRC>,
<&clock_rpmcc RPM_XO_A_CLK_SRC>;
#clock-cells = <1>;
};
sdhc_1: sdhci@c0c4000 {
compatible = "qcom,sdhci-msm-v5";
reg = <0xc0c4000 0x1000>, <0xc0c5000 0x1000>;
@ -2047,3 +2273,6 @@
};
};
};
#include "msmfalcon-mdss.dtsi"
#include "msmfalcon-mdss-pll.dtsi"

178
arch/arm/boot/dts/qcom/msmtriton.dtsi
View file

@ -30,6 +30,7 @@
chosen {
stdout-path = "serial0";
bootargs = "rcupdate.rcu_expedited=1";
};
psci {
@ -46,6 +47,7 @@
compatible = "arm,armv8";
reg = <0x0 0x100>;
enable-method = "psci";
qcom,limits-info = <&mitigation_profile0>;
efficiency = <1024>;
next-level-cache = <&L2_1>;
L2_1: l2-cache {
@ -69,6 +71,7 @@
compatible = "arm,armv8";
reg = <0x0 0x101>;
enable-method = "psci";
qcom,limits-info = <&mitigation_profile1>;
efficiency = <1024>;
next-level-cache = <&L2_1>;
L1_I_101: l1-icache {
@ -86,6 +89,7 @@
compatible = "arm,armv8";
reg = <0x0 0x102>;
enable-method = "psci";
qcom,limits-info = <&mitigation_profile2>;
efficiency = <1024>;
next-level-cache = <&L2_1>;
L1_I_102: l1-icache {
@ -103,6 +107,7 @@
compatible = "arm,armv8";
reg = <0x0 0x103>;
enable-method = "psci";
qcom,limits-info = <&mitigation_profile3>;
efficiency = <1024>;
next-level-cache = <&L2_1>;
L1_I_103: l1-icache {
@ -120,6 +125,7 @@
compatible = "arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
qcom,limits-info = <&mitigation_profile4>;
efficiency = <1024>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
@ -143,6 +149,7 @@
compatible = "arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
qcom,limits-info = <&mitigation_profile4>;
efficiency = <1024>;
next-level-cache = <&L2_0>;
L1_I_1: l1-icache {
@ -160,6 +167,7 @@
compatible = "arm,armv8";
reg = <0x0 0x2>;
enable-method = "psci";
qcom,limits-info = <&mitigation_profile4>;
efficiency = <1024>;
next-level-cache = <&L2_0>;
L1_I_2: l1-icache {
@ -177,6 +185,7 @@
compatible = "arm,armv8";
reg = <0x0 0x3>;
enable-method = "psci";
qcom,limits-info = <&mitigation_profile4>;
efficiency = <1024>;
next-level-cache = <&L2_0>;
L1_I_3: l1-icache {
@ -449,6 +458,175 @@
qcom,sensors = <12>;
};
qcom,sensor-information {
compatible = "qcom,sensor-information";
sensor_information0: qcom,sensor-information-0 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor0";
qcom,scaling-factor = <10>;
};
sensor_information1: qcom,sensor-information-1 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor1";
qcom,scaling-factor = <10>;
};
sensor_information2: qcom,sensor-information-2 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor2";
qcom,scaling-factor = <10>;
};
sensor_information3: qcom,sensor-information-3 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor3";
qcom,scaling-factor = <10>;
};
sensor_information4: qcom,sensor-information-4 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor4";
qcom,scaling-factor = <10>;
};
sensor_information5: qcom,sensor-information-5 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor5";
qcom,scaling-factor = <10>;
};
sensor_information6: qcom,sensor-information-6 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor6";
qcom,scaling-factor = <10>;
};
sensor_information7: qcom,sensor-information-7 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor7";
qcom,scaling-factor = <10>;
};
sensor_information8: qcom,sensor-information-8 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor8";
qcom,scaling-factor = <10>;
qcom,alias-name = "gpu";
};
sensor_information9: qcom,sensor-information-9 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor9";
qcom,scaling-factor = <10>;
};
sensor_information10: qcom,sensor-information-10 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor10";
qcom,scaling-factor = <10>;
};
sensor_information11: qcom,sensor-information-11 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor11";
qcom,scaling-factor = <10>;
};
sensor_information12: qcom,sensor-information-12 {
qcom,sensor-type = "alarm";
qcom,sensor-name = "pmfalcon_tz";
qcom,scaling-factor = <1000>;
};
sensor_information13: qcom,sensor-information-13 {
qcom,sensor-type = "adc";
qcom,sensor-name = "msm_therm";
};
sensor_information14: qcom,sensor-information-14 {
qcom,sensor-type = "adc";
qcom,sensor-name = "xo_therm";
};
sensor_information15: qcom,sensor-information-15 {
qcom,sensor-type = "adc";
qcom,sensor-name = "pa_therm0";
};
sensor_information16: qcom,sensor-information-16 {
qcom,sensor-type = "adc";
qcom,sensor-name = "pa_therm1";
};
sensor_information17: qcom,sensor-information-17 {
qcom,sensor-type = "adc";
qcom,sensor-name = "quiet_therm";
};
sensor_information18: qcom,sensor-information-18 {
qcom,sensor-type = "llm";
qcom,sensor-name = "limits_sensor-00";
};
sensor_information19: qcom,sensor-information-19 {
qcom,sensor-type = "llm";
qcom,sensor-name = "limits_sensor-01";
};
};
mitigation_profile0: qcom,limit_info-0 {
qcom,temperature-sensor = <&sensor_information3>;
qcom,hotplug-mitigation-enable;
};
mitigation_profile1: qcom,limit_info-1 {
qcom,temperature-sensor = <&sensor_information4>;
qcom,hotplug-mitigation-enable;
};
mitigation_profile2: qcom,limit_info-2 {
qcom,temperature-sensor = <&sensor_information5>;
qcom,hotplug-mitigation-enable;
};
mitigation_profile3: qcom,limit_info-3 {
qcom,temperature-sensor = <&sensor_information6>;
qcom,hotplug-mitigation-enable;
};
mitigation_profile4: qcom,limit_info-4 {
qcom,temperature-sensor = <&sensor_information1>;
qcom,hotplug-mitigation-enable;
};
qcom,msm-thermal {
compatible = "qcom,msm-thermal";
qcom,sensor-id = <3>;
qcom,poll-ms = <100>;
qcom,therm-reset-temp = <115>;
qcom,core-limit-temp = <70>;
qcom,core-temp-hysteresis = <10>;
qcom,hotplug-temp = <105>;
qcom,hotplug-temp-hysteresis = <20>;
qcom,online-hotplug-core;
qcom,synchronous-cluster-id = <0 1>;
qcom,synchronous-cluster-map = <0 4 &CPU4 &CPU5 &CPU6 &CPU7>,
<1 4 &CPU0 &CPU1 &CPU2 &CPU3>;
qcom,vdd-restriction-temp = <5>;
qcom,vdd-restriction-temp-hysteresis = <10>;
vdd-dig-supply = <&pm2falcon_s3_floor_level>;
vdd-gfx-supply = <&gfx_vreg_corner>;
qcom,vdd-dig-rstr{
qcom,vdd-rstr-reg = "vdd-dig";
qcom,levels = <RPM_SMD_REGULATOR_LEVEL_NOM
RPM_SMD_REGULATOR_LEVEL_TURBO
RPM_SMD_REGULATOR_LEVEL_TURBO>;
qcom,min-level = <RPM_SMD_REGULATOR_LEVEL_NONE>;
};
qcom,vdd-gfx-rstr{
qcom,vdd-rstr-reg = "vdd-gfx";
qcom,levels = <5 6 6>; /* Nominal, Turbo, Turbo */
qcom,min-level = <1>; /* No Request */
};
msm_thermal_freq: qcom,vdd-apps-rstr{
qcom,vdd-rstr-reg = "vdd-apps";
qcom,levels = <1248000>;
qcom,freq-req;
};
};
qcom,lmh {
compatible = "qcom,lmh_v1";
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
};
wdog: qcom,wdt@17817000 {
status = "disabled";
compatible = "qcom,msm-watchdog";

1
arch/arm/configs/msmcortex_defconfig
View file

@ -353,6 +353,7 @@ CONFIG_USB_STORAGE=y
CONFIG_USB_DWC3=y
CONFIG_USB_ISP1760=y
CONFIG_USB_ISP1760_HOST_ROLE=y
CONFIG_USB_EHSET_TEST_FIXTURE=y
CONFIG_USB_OTG_WAKELOCK=y
CONFIG_NOP_USB_XCEIV=y
CONFIG_USB_MSM_SSPHY_QMP=y

2
arch/arm/configs/msmfalcon-perf_defconfig
View file

@ -348,6 +348,7 @@ CONFIG_WCD9335_CODEC=y
CONFIG_WCD934X_CODEC=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_MSM_GFX_LDO=y
CONFIG_REGULATOR_RPM_SMD=y
CONFIG_REGULATOR_QPNP=y
CONFIG_REGULATOR_QPNP_LABIBB=y
@ -355,6 +356,7 @@ CONFIG_REGULATOR_SPM=y
CONFIG_REGULATOR_CPR3_HMSS=y
CONFIG_REGULATOR_CPR3_MMSS=y
CONFIG_REGULATOR_CPRH_KBSS=y
CONFIG_REGULATOR_CPR4_MMSS_LDO=y
CONFIG_REGULATOR_MEM_ACC=y
CONFIG_REGULATOR_PROXY_CONSUMER=y
CONFIG_REGULATOR_STUB=y

3
arch/arm/configs/msmfalcon_defconfig
View file

@ -346,6 +346,7 @@ CONFIG_WCD9335_CODEC=y
CONFIG_WCD934X_CODEC=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_MSM_GFX_LDO=y
CONFIG_REGULATOR_RPM_SMD=y
CONFIG_REGULATOR_QPNP=y
CONFIG_REGULATOR_QPNP_LABIBB=y
@ -354,6 +355,7 @@ CONFIG_REGULATOR_SPM=y
CONFIG_REGULATOR_CPR3_HMSS=y
CONFIG_REGULATOR_CPR3_MMSS=y
CONFIG_REGULATOR_CPRH_KBSS=y
CONFIG_REGULATOR_CPR4_MMSS_LDO=y
CONFIG_REGULATOR_MEM_ACC=y
CONFIG_REGULATOR_PROXY_CONSUMER=y
CONFIG_REGULATOR_STUB=y
@ -482,6 +484,7 @@ CONFIG_USB_BAM=y
CONFIG_QCOM_CLK_SMD_RPM=y
CONFIG_MSM_GPUCC_FALCON=y
CONFIG_MSM_MMCC_FALCON=y
CONFIG_CLOCK_CPU_OSM=y
CONFIG_QCOM_MDSS_PLL=y
CONFIG_REMOTE_SPINLOCK_MSM=y
CONFIG_ARM_SMMU=y

2
arch/arm64/configs/msmcortex-perf_defconfig
View file

@ -430,6 +430,7 @@ CONFIG_USB_ISP1760=y
CONFIG_USB_ISP1760_HOST_ROLE=y
CONFIG_USB_PD_POLICY=y
CONFIG_QPNP_USB_PDPHY=y
CONFIG_USB_EHSET_TEST_FIXTURE=y
CONFIG_USB_OTG_WAKELOCK=y
CONFIG_NOP_USB_XCEIV=y
CONFIG_USB_MSM_SSPHY_QMP=y
@ -614,7 +615,6 @@ CONFIG_CRYPTO_DEV_QCRYPTO=y
CONFIG_CRYPTO_DEV_QCOM_MSM_QCE=y
CONFIG_CRYPTO_DEV_QCEDEV=y
CONFIG_CRYPTO_DEV_OTA_CRYPTO=y
CONFIG_CRYPTO_DEV_QCE=y
CONFIG_CRYPTO_DEV_QCOM_ICE=y
CONFIG_ARM64_CRYPTO=y
CONFIG_CRYPTO_SHA1_ARM64_CE=y

2
arch/arm64/configs/msmcortex_defconfig
View file

@ -432,6 +432,7 @@ CONFIG_USB_ISP1760=y
CONFIG_USB_ISP1760_HOST_ROLE=y
CONFIG_USB_PD_POLICY=y
CONFIG_QPNP_USB_PDPHY=y
CONFIG_USB_EHSET_TEST_FIXTURE=y
CONFIG_USB_OTG_WAKELOCK=y
CONFIG_NOP_USB_XCEIV=y
CONFIG_USB_MSM_SSPHY_QMP=y
@ -681,7 +682,6 @@ CONFIG_CRYPTO_DEV_QCRYPTO=y
CONFIG_CRYPTO_DEV_QCOM_MSM_QCE=y
CONFIG_CRYPTO_DEV_QCEDEV=y
CONFIG_CRYPTO_DEV_OTA_CRYPTO=y
CONFIG_CRYPTO_DEV_QCE=y
CONFIG_CRYPTO_DEV_QCOM_ICE=y
CONFIG_ARM64_CRYPTO=y
CONFIG_CRYPTO_SHA1_ARM64_CE=y

3
arch/arm64/configs/msmfalcon-perf_defconfig
View file

@ -346,6 +346,7 @@ CONFIG_WCD9335_CODEC=y
CONFIG_WCD934X_CODEC=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_MSM_GFX_LDO=y
CONFIG_REGULATOR_RPM_SMD=y
CONFIG_REGULATOR_QPNP=y
CONFIG_REGULATOR_QPNP_LABIBB=y
@ -354,6 +355,7 @@ CONFIG_REGULATOR_SPM=y
CONFIG_REGULATOR_CPR3_HMSS=y
CONFIG_REGULATOR_CPR3_MMSS=y
CONFIG_REGULATOR_CPRH_KBSS=y
CONFIG_REGULATOR_CPR4_MMSS_LDO=y
CONFIG_REGULATOR_MEM_ACC=y
CONFIG_REGULATOR_PROXY_CONSUMER=y
CONFIG_REGULATOR_STUB=y
@ -504,6 +506,7 @@ CONFIG_USB_BAM=y
CONFIG_QCOM_CLK_SMD_RPM=y
CONFIG_MSM_GPUCC_FALCON=y
CONFIG_MSM_MMCC_FALCON=y
CONFIG_CLOCK_CPU_OSM=y
CONFIG_QCOM_MDSS_PLL=y
CONFIG_REMOTE_SPINLOCK_MSM=y
CONFIG_IOMMU_IO_PGTABLE_FAST=y

3
arch/arm64/configs/msmfalcon_defconfig
View file

@ -348,6 +348,7 @@ CONFIG_WCD9335_CODEC=y
CONFIG_WCD934X_CODEC=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_MSM_GFX_LDO=y
CONFIG_REGULATOR_RPM_SMD=y
CONFIG_REGULATOR_QPNP=y
CONFIG_REGULATOR_QPNP_LABIBB=y
@ -356,6 +357,7 @@ CONFIG_REGULATOR_SPM=y
CONFIG_REGULATOR_CPR3_HMSS=y
CONFIG_REGULATOR_CPR3_MMSS=y
CONFIG_REGULATOR_CPRH_KBSS=y
CONFIG_REGULATOR_CPR4_MMSS_LDO=y
CONFIG_REGULATOR_MEM_ACC=y
CONFIG_REGULATOR_PROXY_CONSUMER=y
CONFIG_REGULATOR_STUB=y
@ -513,6 +515,7 @@ CONFIG_USB_BAM=y
CONFIG_QCOM_CLK_SMD_RPM=y
CONFIG_MSM_GPUCC_FALCON=y
CONFIG_MSM_MMCC_FALCON=y
CONFIG_CLOCK_CPU_OSM=y
CONFIG_QCOM_MDSS_PLL=y
CONFIG_REMOTE_SPINLOCK_MSM=y
CONFIG_IOMMU_IO_PGTABLE_FAST=y

26
drivers/char/diag/diag_dci.c
View file

@ -771,6 +771,7 @@ static int diag_dci_remove_req_entry(unsigned char *buf, int len,
if (*buf != 0x80) {
list_del(&entry->track);
kfree(entry);
entry = NULL;
return 1;
}
@ -788,6 +789,7 @@ static int diag_dci_remove_req_entry(unsigned char *buf, int len,
if (delayed_rsp_id == 0) {
list_del(&entry->track);
kfree(entry);
entry = NULL;
return 1;
}
@ -801,6 +803,7 @@ static int diag_dci_remove_req_entry(unsigned char *buf, int len,
if (rsp_count > 0 && rsp_count < 0x1000) {
list_del(&entry->track);
kfree(entry);
entry = NULL;
return 1;
}
@ -2682,10 +2685,12 @@ int diag_dci_init(void)
err:
pr_err("diag: Could not initialize diag DCI buffers");
kfree(driver->apps_dci_buf);
driver->apps_dci_buf = NULL;
if (driver->diag_dci_wq)
destroy_workqueue(driver->diag_dci_wq);
kfree(partial_pkt.data);
partial_pkt.data = NULL;
mutex_destroy(&driver->dci_mutex);
mutex_destroy(&dci_log_mask_mutex);
mutex_destroy(&dci_event_mask_mutex);
@ -2705,7 +2710,9 @@ void diag_dci_channel_init(void)
void diag_dci_exit(void)
{
kfree(partial_pkt.data);
partial_pkt.data = NULL;
kfree(driver->apps_dci_buf);
driver->apps_dci_buf = NULL;
mutex_destroy(&driver->dci_mutex);
mutex_destroy(&dci_log_mask_mutex);
mutex_destroy(&dci_event_mask_mutex);
@ -2917,22 +2924,30 @@ fail_alloc:
mutex_destroy(&proc_buf->health_mutex);
if (proc_buf->buf_primary) {
kfree(proc_buf->buf_primary->data);
proc_buf->buf_primary->data = NULL;
mutex_destroy(
&proc_buf->buf_primary->data_mutex);
}
kfree(proc_buf->buf_primary);
proc_buf->buf_primary = NULL;
if (proc_buf->buf_cmd) {
kfree(proc_buf->buf_cmd->data);
proc_buf->buf_cmd->data = NULL;
mutex_destroy(
&proc_buf->buf_cmd->data_mutex);
}
kfree(proc_buf->buf_cmd);
proc_buf->buf_cmd = NULL;
}
}
kfree(new_entry->dci_event_mask);
new_entry->dci_event_mask = NULL;
kfree(new_entry->dci_log_mask);
new_entry->dci_log_mask = NULL;
kfree(new_entry->buffers);
new_entry->buffers = NULL;
kfree(new_entry);
new_entry = NULL;
}
mutex_unlock(&driver->dci_mutex);
return DIAG_DCI_NO_REG;
@ -2963,6 +2978,7 @@ int diag_dci_deinit_client(struct diag_dci_client_tbl *entry)
* masks and send the masks to peripherals
*/
kfree(entry->dci_log_mask);
entry->dci_log_mask = NULL;
diag_dci_invalidate_cumulative_log_mask(token);
if (token == DCI_LOCAL_PROC)
diag_update_userspace_clients(DCI_LOG_MASKS_TYPE);
@ -2971,6 +2987,7 @@ int diag_dci_deinit_client(struct diag_dci_client_tbl *entry)
return ret;
}
kfree(entry->dci_event_mask);
entry->dci_event_mask = NULL;
diag_dci_invalidate_cumulative_event_mask(token);
if (token == DCI_LOCAL_PROC)
diag_update_userspace_clients(DCI_EVENT_MASKS_TYPE);
@ -2986,6 +3003,7 @@ int diag_dci_deinit_client(struct diag_dci_client_tbl *entry)
if (!list_empty(&req_entry->track))
list_del(&req_entry->track);
kfree(req_entry);
req_entry = NULL;
}
}
@ -3001,6 +3019,7 @@ int diag_dci_deinit_client(struct diag_dci_client_tbl *entry)
buf_entry->data = NULL;
mutex_unlock(&buf_entry->data_mutex);
kfree(buf_entry);
buf_entry = NULL;
} else if (buf_entry->buf_type == DCI_BUF_CMD) {
peripheral = buf_entry->data_source;
if (peripheral == APPS_DATA)
@ -3027,14 +3046,17 @@ int diag_dci_deinit_client(struct diag_dci_client_tbl *entry)
mutex_unlock(&buf_entry->data_mutex);
mutex_destroy(&buf_entry->data_mutex);
kfree(buf_entry);
buf_entry = NULL;
}
mutex_lock(&proc_buf->buf_primary->data_mutex);
kfree(proc_buf->buf_primary->data);
proc_buf->buf_primary->data = NULL;
mutex_unlock(&proc_buf->buf_primary->data_mutex);
mutex_lock(&proc_buf->buf_cmd->data_mutex);
kfree(proc_buf->buf_cmd->data);
proc_buf->buf_cmd->data = NULL;
mutex_unlock(&proc_buf->buf_cmd->data_mutex);
mutex_destroy(&proc_buf->health_mutex);
@ -3042,13 +3064,17 @@ int diag_dci_deinit_client(struct diag_dci_client_tbl *entry)
mutex_destroy(&proc_buf->buf_cmd->data_mutex);
kfree(proc_buf->buf_primary);
proc_buf->buf_primary = NULL;
kfree(proc_buf->buf_cmd);
proc_buf->buf_cmd = NULL;
mutex_unlock(&proc_buf->buf_mutex);
}
mutex_destroy(&entry->write_buf_mutex);
kfree(entry->buffers);
entry->buffers = NULL;
kfree(entry);
entry = NULL;
if (driver->num_dci_client == 0) {
diag_update_proc_vote(DIAG_PROC_DCI, VOTE_DOWN, token);

63
drivers/clk/clk.c
View file

@ -71,6 +71,8 @@ struct clk_core {
bool orphan;
unsigned int enable_count;
unsigned int prepare_count;
bool need_handoff_enable;
bool need_handoff_prepare;
unsigned long min_rate;
unsigned long max_rate;
unsigned long accuracy;
@ -195,6 +197,19 @@ static void clk_unprepare_unused_subtree(struct clk_core *core)
hlist_for_each_entry(child, &core->children, child_node)
clk_unprepare_unused_subtree(child);
/*
* setting CLK_ENABLE_HAND_OFF flag triggers this conditional
*
* need_handoff_prepare implies this clk was already prepared by
* __clk_init. now we have a proper user, so unset the flag in our
* internal bookkeeping. See CLK_ENABLE_HAND_OFF flag in clk-provider.h
* for details.
*/
if (core->need_handoff_prepare) {
core->need_handoff_prepare = false;
core->prepare_count--;
}
if (core->prepare_count)
return;
@ -221,6 +236,19 @@ static void clk_disable_unused_subtree(struct clk_core *core)
hlist_for_each_entry(child, &core->children, child_node)
clk_disable_unused_subtree(child);
/*
* setting CLK_ENABLE_HAND_OFF flag triggers this conditional
*
* need_handoff_enable implies this clk was already enabled by
* __clk_init. now we have a proper user, so unset the flag in our
* internal bookkeeping. See CLK_ENABLE_HAND_OFF flag in clk-provider.h
* for details.
*/
if (core->need_handoff_enable) {
core->need_handoff_enable = false;
core->enable_count--;
}
flags = clk_enable_lock();
if (core->enable_count)
@ -925,7 +953,7 @@ static int clk_core_prepare(struct clk_core *core)
*/
int clk_prepare(struct clk *clk)
{
int ret;
int ret = 0;
if (!clk)
return 0;
@ -1040,7 +1068,7 @@ static int clk_core_enable(struct clk_core *core)
int clk_enable(struct clk *clk)
{
unsigned long flags;
int ret;
int ret = 0;
if (!clk)
return 0;
@ -3146,6 +3174,37 @@ static int __clk_init(struct device *dev, struct clk *clk_user)
clk_enable_unlock(flags);
}
/*
* enable clocks with the CLK_ENABLE_HAND_OFF flag set
*
* This flag causes the framework to enable the clock at registration
* time, which is sometimes necessary for clocks that would cause a
* system crash when gated (e.g. cpu, memory, etc). The prepare_count
* is migrated over to the first clk consumer to call clk_prepare().
* Similarly the clk's enable_count is migrated to the first consumer
* to call clk_enable().
*/
if (core->flags & CLK_ENABLE_HAND_OFF) {
unsigned long flags;
/*
* Few clocks might have hardware gating which would be required
* to be ON before prepare/enabling the clocks. So check if the
* clock has been turned ON earlier and we should
* prepare/enable those clocks.
*/
if (clk_core_is_enabled(core)) {
core->need_handoff_prepare = true;
core->need_handoff_enable = true;
ret = clk_core_prepare(core);
if (ret)
goto out;
flags = clk_enable_lock();
clk_core_enable(core);
clk_enable_unlock(flags);
}
}
kref_init(&core->ref);
out:
clk_prepare_unlock();

12
drivers/clk/qcom/Kconfig
View file

@ -219,4 +219,16 @@ config QCOM_A53
Say Y if you want to support CPU frequency scaling on devices
such as MSM8916.
config CLOCK_CPU_OSM
tristate "OSM CPU Clock Controller"
depends on COMMON_CLK_QCOM
help
Support for the osm clock controller.
Operating State Manager (OSM) is a hardware engine used by some
Qualcomm Technologies, Inc. (QTI) SoCs to manage frequency and
voltage scaling in hardware. OSM is capable of controlling
frequency and voltage requests for multiple clusters via the
existence of multiple OSM domains.
Say Y if you want to support osm clocks.
source "drivers/clk/qcom/mdss/Kconfig"

1
drivers/clk/qcom/Makefile
View file

@ -37,5 +37,6 @@ obj-$(CONFIG_KRAITCC) += krait-cc.o
obj-$(CONFIG_QCOM_A53) += clk-a53.o
obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o
obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
obj-$(CONFIG_CLOCK_CPU_OSM) += clk-cpu-osm.o
obj-y += mdss/

1105
drivers/clk/qcom/clk-cpu-osm.c
View file

File diff suppressed because it is too large Load diff

93
drivers/clk/qcom/clk-smd-rpm.c
View file

@ -551,6 +551,39 @@ DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8996, bb_clk2_pin, bb_clk2_a_pin, 2);
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8996, rf_clk1_pin, rf_clk1_a_pin, 4);
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8996, rf_clk2_pin, rf_clk2_a_pin, 5);
/* Voter clocks */
static DEFINE_CLK_VOTER(mmssnoc_axi_clk, mmssnoc_axi_rpm_clk, 0);
static DEFINE_CLK_VOTER(mmssnoc_axi_a_clk, mmssnoc_axi_rpm_a_clk, 0);
static DEFINE_CLK_VOTER(mmssnoc_gds_clk, mmssnoc_axi_rpm_clk, 40000000);
static DEFINE_CLK_VOTER(bimc_msmbus_clk, bimc_clk, LONG_MAX);
static DEFINE_CLK_VOTER(bimc_msmbus_a_clk, bimc_a_clk, LONG_MAX);
static DEFINE_CLK_VOTER(cnoc_msmbus_clk, cnoc_clk, LONG_MAX);
static DEFINE_CLK_VOTER(cnoc_msmbus_a_clk, cnoc_a_clk, LONG_MAX);
static DEFINE_CLK_VOTER(snoc_msmbus_clk, snoc_clk, LONG_MAX);
static DEFINE_CLK_VOTER(snoc_msmbus_a_clk, snoc_a_clk, LONG_MAX);
static DEFINE_CLK_VOTER(cnoc_periph_keepalive_a_clk, cnoc_periph_a_clk,
LONG_MAX);
static DEFINE_CLK_VOTER(mcd_ce1_clk, ce1_clk, 85710000);
static DEFINE_CLK_VOTER(qcedev_ce1_clk, ce1_clk, 85710000);
static DEFINE_CLK_VOTER(qcrypto_ce1_clk, ce1_clk, 85710000);
static DEFINE_CLK_VOTER(qseecom_ce1_clk, ce1_clk, 85710000);
static DEFINE_CLK_VOTER(scm_ce1_clk, ce1_clk, 85710000);
static DEFINE_CLK_VOTER(pnoc_keepalive_a_clk, pnoc_a_clk, LONG_MAX);
static DEFINE_CLK_VOTER(pnoc_msmbus_clk, pnoc_clk, LONG_MAX);
static DEFINE_CLK_VOTER(pnoc_msmbus_a_clk, pnoc_a_clk, LONG_MAX);
static DEFINE_CLK_VOTER(pnoc_pm_clk, pnoc_clk, LONG_MAX);
static DEFINE_CLK_VOTER(pnoc_sps_clk, pnoc_clk, 0);
static DEFINE_CLK_VOTER(mmssnoc_a_clk_cpu_vote, mmssnoc_axi_rpm_a_clk,
19200000);
/* Voter Branch clocks */
static DEFINE_CLK_BRANCH_VOTER(cxo_dwc3_clk, cxo);
static DEFINE_CLK_BRANCH_VOTER(cxo_lpm_clk, cxo);
static DEFINE_CLK_BRANCH_VOTER(cxo_otg_clk, cxo);
static DEFINE_CLK_BRANCH_VOTER(cxo_pil_lpass_clk, cxo);
static DEFINE_CLK_BRANCH_VOTER(cxo_pil_ssc_clk, cxo);
static DEFINE_CLK_BRANCH_VOTER(cxo_pil_cdsp_clk, cxo);
static struct clk_hw *msm8996_clks[] = {
[RPM_XO_CLK_SRC] = &msm8996_cxo.hw,
[RPM_XO_A_CLK_SRC] = &msm8996_cxo_a.hw,
@ -590,6 +623,31 @@ static struct clk_hw *msm8996_clks[] = {
[RPM_DIV_CLK3_AO] = &msm8996_div_clk3_ao.hw,
[RPM_LN_BB_CLK] = &msm8996_ln_bb_clk.hw,
[RPM_LN_BB_A_CLK] = &msm8996_ln_bb_a_clk.hw,
[MMSSNOC_AXI_CLK] = &mmssnoc_axi_clk.hw,
[MMSSNOC_AXI_A_CLK] = &mmssnoc_axi_a_clk.hw,
[MMSSNOC_GDS_CLK] = &mmssnoc_gds_clk.hw,
[BIMC_MSMBUS_CLK] = &bimc_msmbus_clk.hw,
[BIMC_MSMBUS_A_CLK] = &bimc_msmbus_a_clk.hw,
[CNOC_MSMBUS_CLK] = &cnoc_msmbus_clk.hw,
[CNOC_MSMBUS_A_CLK] = &cnoc_msmbus_a_clk.hw,
[PNOC_KEEPALIVE_A_CLK] = &pnoc_keepalive_a_clk.hw,
[PNOC_MSMBUS_CLK] = &pnoc_msmbus_clk.hw,
[PNOC_MSMBUS_A_CLK] = &pnoc_msmbus_a_clk.hw,
[PNOC_PM_CLK] = &pnoc_pm_clk.hw,
[PNOC_SPS_CLK] = &pnoc_sps_clk.hw,
[MCD_CE1_CLK] = &mcd_ce1_clk.hw,
[QCEDEV_CE1_CLK] = &qcedev_ce1_clk.hw,
[QCRYPTO_CE1_CLK] = &qcrypto_ce1_clk.hw,
[QSEECOM_CE1_CLK] = &qseecom_ce1_clk.hw,
[SCM_CE1_CLK] = &scm_ce1_clk.hw,
[SNOC_MSMBUS_CLK] = &snoc_msmbus_clk.hw,
[SNOC_MSMBUS_A_CLK] = &snoc_msmbus_a_clk.hw,
[CXO_DWC3_CLK] = &cxo_dwc3_clk.hw,
[CXO_LPM_CLK] = &cxo_lpm_clk.hw,
[CXO_OTG_CLK] = &cxo_otg_clk.hw,
[CXO_PIL_LPASS_CLK] = &cxo_pil_lpass_clk.hw,
[CXO_PIL_SSC_CLK] = &cxo_pil_ssc_clk.hw,
[MMSSNOC_A_CLK_CPU_VOTE] = &mmssnoc_a_clk_cpu_vote.hw
};
static const struct rpm_smd_clk_desc rpm_clk_msm8996 = {
@ -627,26 +685,6 @@ DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msmfalcon, ln_bb_clk2_pin,
ln_bb_clk2_pin_ao, 0x2);
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msmfalcon, ln_bb_clk3_pin,
ln_bb_clk3_pin_ao, 0x3);
/* Voter clocks */
static DEFINE_CLK_VOTER(bimc_msmbus_clk, bimc_clk, LONG_MAX);
static DEFINE_CLK_VOTER(bimc_msmbus_a_clk, bimc_a_clk, LONG_MAX);
static DEFINE_CLK_VOTER(cnoc_msmbus_clk, cnoc_clk, LONG_MAX);
static DEFINE_CLK_VOTER(cnoc_msmbus_a_clk, cnoc_a_clk, LONG_MAX);
static DEFINE_CLK_VOTER(snoc_msmbus_clk, snoc_clk, LONG_MAX);
static DEFINE_CLK_VOTER(snoc_msmbus_a_clk, snoc_a_clk, LONG_MAX);
static DEFINE_CLK_VOTER(cnoc_periph_keepalive_a_clk, cnoc_periph_a_clk,
LONG_MAX);
static DEFINE_CLK_VOTER(mcd_ce1_clk, ce1_clk, 85710000);
static DEFINE_CLK_VOTER(qcedev_ce1_clk, ce1_clk, 85710000);
static DEFINE_CLK_VOTER(qcrypto_ce1_clk, ce1_clk, 85710000);
static DEFINE_CLK_VOTER(qseecom_ce1_clk, ce1_clk, 85710000);
static DEFINE_CLK_VOTER(scm_ce1_clk, ce1_clk, 85710000);
static DEFINE_CLK_BRANCH_VOTER(cxo_dwc3_clk, cxo);
static DEFINE_CLK_BRANCH_VOTER(cxo_lpm_clk, cxo);
static DEFINE_CLK_BRANCH_VOTER(cxo_otg_clk, cxo);
static DEFINE_CLK_BRANCH_VOTER(cxo_pil_lpass_clk, cxo);
static DEFINE_CLK_BRANCH_VOTER(cxo_pil_cdsp_clk, cxo);
static struct clk_hw *msmfalcon_clks[] = {
[RPM_XO_CLK_SRC] = &msmfalcon_cxo.hw,
@ -799,10 +837,19 @@ static int rpm_smd_clk_probe(struct platform_device *pdev)
if (ret)
goto err;
/* Keep an active vote on CXO in case no other driver votes for it */
if (is_8996)
if (is_8996) {
/*
* Keep an active vote on CXO in case no other driver
* votes for it.
*/
clk_prepare_enable(msm8996_cxo_a.hw.clk);
else if (is_falcon) {
/* Hold an active set vote for the pnoc_keepalive_a_clk */
clk_set_rate(pnoc_keepalive_a_clk.hw.clk, 19200000);
clk_prepare_enable(pnoc_keepalive_a_clk.hw.clk);
clk_prepare_enable(mmssnoc_a_clk_cpu_vote.hw.clk);
} else if (is_falcon) {
clk_prepare_enable(msmfalcon_cxo_a.hw.clk);
/* Hold an active set vote for the cnoc_periph resource */

1
drivers/clk/qcom/common.h
View file

@ -137,6 +137,7 @@ struct clk_debug_mux {
};
#define BM(msb, lsb) (((((uint32_t)-1) << (31-msb)) >> (31-msb+lsb)) << lsb)
#define BVAL(msb, lsb, val) (((val) << lsb) & BM(msb, lsb))
#define to_clk_measure(_hw) container_of((_hw), struct clk_debug_mux, hw)

195
drivers/clk/qcom/gcc-msm8996.c
View file

@ -31,9 +31,12 @@
#include "clk-rcg.h"
#include "clk-branch.h"
#include "reset.h"
#include "vdd-level-8996.h"
#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
static DEFINE_VDD_REGULATORS(vdd_dig, VDD_DIG_NUM, 1, vdd_corner);
enum {
P_XO,
P_GPLL0,
@ -89,7 +92,7 @@ static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
static const char * const gcc_xo_gpll0_gpll4[] = {
"xo",
"gpll0",
"gpll4"
"gpll4_early"
};
static const struct parent_map gcc_xo_gpll0_aud_ref_clk_map[] = {
@ -128,7 +131,7 @@ static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_early_div_map[] = {
static const char * const gcc_xo_gpll0_gpll4_gpll0_early_div[] = {
"xo",
"gpll0",
"gpll4",
"gpll4_early",
"gpll0_early_div"
};
@ -162,7 +165,7 @@ static const char * const gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_d
"gpll0",
"gpll1_early_div",
"gpll1",
"gpll4",
"gpll4_early",
"gpll0_early_div"
};
@ -202,10 +205,24 @@ static const char * const gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll4_gpll0_early_div[]
"gpll2",
"gpll3",
"gpll1",
"gpll4",
"gpll4_early",
"gpll0_early_div"
};
static struct clk_fixed_factor gcc_ce1_ahb_m_clk = {
.hw.init = &(struct clk_init_data){
.name = "gcc_ce1_ahb_m_clk",
.ops = &clk_dummy_ops,
},
};
static struct clk_fixed_factor gcc_ce1_axi_m_clk = {
.hw.init = &(struct clk_init_data){
.name = "gcc_ce1_axi_m_clk",
.ops = &clk_dummy_ops,
},
};
static struct clk_fixed_factor xo = {
.mult = 1,
.div = 1,
@ -294,6 +311,8 @@ static struct clk_rcg2 usb30_master_clk_src = {
.parent_names = gcc_xo_gpll0_gpll0_early_div,
.num_parents = 3,
.ops = &clk_rcg2_ops,
VDD_DIG_FMAX_MAP3(LOWER, 60000000, LOW, 120000000,
NOMINAL, 150000000),
},
};
@ -312,6 +331,7 @@ static struct clk_rcg2 usb30_mock_utmi_clk_src = {
.parent_names = gcc_xo_gpll0_gpll0_early_div,
.num_parents = 3,
.ops = &clk_rcg2_ops,
VDD_DIG_FMAX_MAP2(LOWER, 40000000, LOW, 60000000),
},
};
@ -330,6 +350,7 @@ static struct clk_rcg2 usb3_phy_aux_clk_src = {
.parent_names = gcc_xo_sleep_clk,
.num_parents = 2,
.ops = &clk_rcg2_ops,
VDD_DIG_FMAX_MAP1(LOWER, 1200000),
},
};
@ -349,6 +370,8 @@ static struct clk_rcg2 usb20_master_clk_src = {
.parent_names = gcc_xo_gpll0_gpll0_early_div,
.num_parents = 3,
.ops = &clk_rcg2_ops,
VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 60000000,
NOMINAL, 120000000),
},
};
@ -362,6 +385,7 @@ static struct clk_rcg2 usb20_mock_utmi_clk_src = {
.parent_names = gcc_xo_gpll0_gpll0_early_div,
.num_parents = 3,
.ops = &clk_rcg2_ops,
VDD_DIG_FMAX_MAP2(LOWER, 19200000, LOW, 60000000),
},
};
@ -388,6 +412,8 @@ static struct clk_rcg2 sdcc1_apps_clk_src = {
.parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
.num_parents = 4,
.ops = &clk_rcg2_ops,
VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 200000000,
NOMINAL, 400000000),
},
};
@ -408,6 +434,8 @@ static struct clk_rcg2 sdcc1_ice_core_clk_src = {
.parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
.num_parents = 4,
.ops = &clk_rcg2_ops,
VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 150000000,
NOMINAL, 300000000),
},
};
@ -433,6 +461,8 @@ static struct clk_rcg2 sdcc2_apps_clk_src = {
.parent_names = gcc_xo_gpll0_gpll4,
.num_parents = 3,
.ops = &clk_rcg2_ops,
VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 100000000,
NOMINAL, 200000000),
},
};
@ -447,6 +477,8 @@ static struct clk_rcg2 sdcc3_apps_clk_src = {
.parent_names = gcc_xo_gpll0_gpll4,
.num_parents = 3,
.ops = &clk_rcg2_ops,
VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 100000000,
NOMINAL, 200000000),
},
};
@ -471,6 +503,8 @@ static struct clk_rcg2 sdcc4_apps_clk_src = {
.parent_names = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 50000000,
NOMINAL, 100000000),
},
};
@ -496,6 +530,8 @@ static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
.parent_names = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 25000000,
NOMINAL, 50000000),
},
};
@ -515,6 +551,7 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
.parent_names = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
VDD_DIG_FMAX_MAP2(LOWER, 19200000, LOW, 50000000),
},
};
@ -548,6 +585,8 @@ static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
.parent_names = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 31580000,
NOMINAL, 63160000),
},
};
@ -562,6 +601,8 @@ static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
.parent_names = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 25000000,
NOMINAL, 50000000),
},
};
@ -575,6 +616,7 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
.parent_names = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
VDD_DIG_FMAX_MAP2(LOWER, 19200000, LOW, 50000000),
},
};
@ -589,6 +631,8 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
.parent_names = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 31580000,
NOMINAL, 63160000),
},
};
@ -603,6 +647,8 @@ static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
.parent_names = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 25000000,
NOMINAL, 50000000),
},
};
@ -616,6 +662,7 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
.parent_names = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
VDD_DIG_FMAX_MAP2(LOWER, 19200000, LOW, 50000000),
},
};
@ -630,6 +677,8 @@ static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
.parent_names = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 31580000,
NOMINAL, 63160000),
},
};
@ -644,6 +693,8 @@ static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
.parent_names = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 25000000,
NOMINAL, 50000000),
},
};
@ -657,6 +708,7 @@ static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
.parent_names = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
VDD_DIG_FMAX_MAP2(LOWER, 19200000, LOW, 50000000),
},
};
@ -671,6 +723,8 @@ static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
.parent_names = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 31580000,
NOMINAL, 63160000),
},
};
@ -685,6 +739,8 @@ static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
.parent_names = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 25000000,
NOMINAL, 50000000),
},
};
@ -698,6 +754,7 @@ static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
.parent_names = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
VDD_DIG_FMAX_MAP2(LOWER, 19200000, LOW, 50000000),
},
};
@ -712,6 +769,8 @@ static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
.parent_names = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 31580000,
NOMINAL, 63160000),
},
};
@ -726,6 +785,8 @@ static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
.parent_names = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 25000000,
NOMINAL, 50000000),
},
};
@ -739,6 +800,7 @@ static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
.parent_names = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
VDD_DIG_FMAX_MAP2(LOWER, 19200000, LOW, 50000000),
},
};
@ -753,6 +815,8 @@ static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
.parent_names = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 31580000,
NOMINAL, 63160000),
},
};
@ -767,6 +831,8 @@ static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
.parent_names = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 25000000,
NOMINAL, 50000000),
},
};
@ -780,6 +846,7 @@ static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
.parent_names = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
VDD_DIG_FMAX_MAP2(LOWER, 19200000, LOW, 50000000),
},
};
@ -794,6 +861,8 @@ static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
.parent_names = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 31580000,
NOMINAL, 63160000),
},
};
@ -808,6 +877,8 @@ static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
.parent_names = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 25000000,
NOMINAL, 50000000),
},
};
@ -821,6 +892,7 @@ static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
.parent_names = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
VDD_DIG_FMAX_MAP2(LOWER, 19200000, LOW, 50000000),
},
};
@ -835,6 +907,8 @@ static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
.parent_names = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 31580000,
NOMINAL, 63160000),
},
};
@ -849,6 +923,8 @@ static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
.parent_names = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 25000000,
NOMINAL, 50000000),
},
};
@ -862,6 +938,7 @@ static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
.parent_names = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
VDD_DIG_FMAX_MAP2(LOWER, 19200000, LOW, 50000000),
},
};
@ -876,6 +953,8 @@ static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
.parent_names = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 31580000,
NOMINAL, 63160000),
},
};
@ -890,6 +969,8 @@ static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
.parent_names = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 25000000,
NOMINAL, 50000000),
},
};
@ -903,6 +984,7 @@ static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
.parent_names = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
VDD_DIG_FMAX_MAP2(LOWER, 19200000, LOW, 50000000),
},
};
@ -917,6 +999,8 @@ static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
.parent_names = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 31580000,
NOMINAL, 63160000),
},
};
@ -931,6 +1015,8 @@ static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
.parent_names = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 25000000,
NOMINAL, 50000000),
},
};
@ -944,6 +1030,7 @@ static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
.parent_names = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
VDD_DIG_FMAX_MAP2(LOWER, 19200000, LOW, 50000000),
},
};
@ -958,6 +1045,8 @@ static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
.parent_names = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 31580000,
NOMINAL, 63160000),
},
};
@ -972,6 +1061,8 @@ static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
.parent_names = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 25000000,
NOMINAL, 50000000),
},
};
@ -985,6 +1076,7 @@ static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
.parent_names = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
VDD_DIG_FMAX_MAP2(LOWER, 19200000, LOW, 50000000),
},
};
@ -999,6 +1091,8 @@ static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
.parent_names = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 31580000,
NOMINAL, 63160000),
},
};
@ -1017,6 +1111,7 @@ static struct clk_rcg2 pdm2_clk_src = {
.parent_names = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
VDD_DIG_FMAX_MAP2(LOWER, 19200000, LOW, 60000000),
},
};
@ -1036,6 +1131,7 @@ static struct clk_rcg2 tsif_ref_clk_src = {
.parent_names = gcc_xo_gpll0_aud_ref_clk,
.num_parents = 3,
.ops = &clk_rcg2_ops,
VDD_DIG_FMAX_MAP1(LOWER, 19200000),
},
};
@ -1082,6 +1178,8 @@ static struct clk_rcg2 gp1_clk_src = {
.parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
.num_parents = 4,
.ops = &clk_rcg2_ops,
VDD_DIG_FMAX_MAP3(LOWER, 50000000, LOW, 100000000,
NOMINAL, 200000000),
},
};
@ -1096,6 +1194,8 @@ static struct clk_rcg2 gp2_clk_src = {
.parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
.num_parents = 4,
.ops = &clk_rcg2_ops,
VDD_DIG_FMAX_MAP3(LOWER, 50000000, LOW, 100000000,
NOMINAL, 200000000),
},
};
@ -1110,6 +1210,8 @@ static struct clk_rcg2 gp3_clk_src = {
.parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
.num_parents = 4,
.ops = &clk_rcg2_ops,
VDD_DIG_FMAX_MAP3(LOWER, 50000000, LOW, 100000000,
NOMINAL, 200000000),
},
};
@ -1129,6 +1231,7 @@ static struct clk_rcg2 pcie_aux_clk_src = {
.parent_names = gcc_xo_sleep_clk,
.num_parents = 2,
.ops = &clk_rcg2_ops,
VDD_DIG_FMAX_MAP1(LOWER, 1011000),
},
};
@ -1150,6 +1253,8 @@ static struct clk_rcg2 ufs_axi_clk_src = {
.parent_names = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
VDD_DIG_FMAX_MAP4(LOWER, 19200000, LOW, 100000000,
NOMINAL, 200000000, HIGH, 240000000),
},
};
@ -1170,6 +1275,8 @@ static struct clk_rcg2 ufs_ice_core_clk_src = {
.parent_names = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 150000000,
NOMINAL, 300000000),
},
};
@ -1191,6 +1298,8 @@ static struct clk_rcg2 qspi_ser_clk_src = {
.parent_names = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div,
.num_parents = 6,
.ops = &clk_rcg2_ops,
VDD_DIG_FMAX_MAP3(LOWER, 80200000, LOW, 160400000,
NOMINAL, 320000000),
},
};
@ -1321,6 +1430,18 @@ static struct clk_branch gcc_usb3_phy_aux_clk = {
},
};
static struct clk_gate2 gpll0_out_msscc_clk = {
.udelay = 1,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gpll0_out_msscc_clk",
.ops = &clk_gate2_ops,
},
},
};
static struct clk_gate2 gcc_usb3_phy_pipe_clk = {
.udelay = 50,
.clkr = {
@ -1333,18 +1454,6 @@ static struct clk_gate2 gcc_usb3_phy_pipe_clk = {
},
};
static struct clk_gate2 gpll0_out_msscc = {
.udelay = 1,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gpll0_out_msscc",
.ops = &clk_gate2_ops,
},
},
};
static struct clk_branch gcc_usb20_master_clk = {
.halt_reg = 0x12004,
.clkr = {
@ -1826,6 +1935,7 @@ static struct clk_branch gcc_blsp2_ahb_clk = {
.enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_ahb_clk",
.flags = CLK_ENABLE_HAND_OFF,
.ops = &clk_branch2_ops,
},
},
@ -2728,18 +2838,6 @@ static struct clk_branch gcc_smmu_aggre0_ahb_clk = {
},
};
static struct clk_branch gcc_aggre1_pnoc_ahb_clk = {
.halt_reg = 0x82014,
.clkr = {
.enable_reg = 0x82014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre1_pnoc_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre2_ufs_axi_clk = {
.halt_reg = 0x83014,
.clkr = {
@ -2995,11 +3093,13 @@ static struct clk_branch gcc_mmss_gpll0_div_clk = {
};
static struct clk_hw *gcc_msm8996_hws[] = {
&xo.hw,
&gpll0_early_div.hw,
&ufs_tx_cfg_clk_src.hw,
&ufs_rx_cfg_clk_src.hw,
&ufs_ice_core_postdiv_clk_src.hw,
[GCC_XO] = &xo.hw,
[GCC_CE1_AHB_M_CLK] = &gcc_ce1_ahb_m_clk.hw,
[GCC_CE1_AXI_M_CLK] = &gcc_ce1_axi_m_clk.hw,
[GCC_GPLL0_EARLY_DIV] = &gpll0_early_div.hw,
[GCC_UFS_TX_CFG_CLK_SRC] = &ufs_tx_cfg_clk_src.hw,
[GCC_UFS_RX_CFG_CLK_SRC] = &ufs_rx_cfg_clk_src.hw,
[GCC_UFS_ICE_CORE_PDIV_CLK_SRC] = &ufs_ice_core_postdiv_clk_src.hw,
};
static struct clk_regmap *gcc_msm8996_clocks[] = {
@ -3170,7 +3270,6 @@ static struct clk_regmap *gcc_msm8996_clocks[] = {
[GCC_AGGRE0_CNOC_AHB_CLK] = &gcc_aggre0_cnoc_ahb_clk.clkr,
[GCC_SMMU_AGGRE0_AXI_CLK] = &gcc_smmu_aggre0_axi_clk.clkr,
[GCC_SMMU_AGGRE0_AHB_CLK] = &gcc_smmu_aggre0_ahb_clk.clkr,
[GCC_AGGRE1_PNOC_AHB_CLK] = &gcc_aggre1_pnoc_ahb_clk.clkr,
[GCC_AGGRE2_UFS_AXI_CLK] = &gcc_aggre2_ufs_axi_clk.clkr,
[GCC_AGGRE2_USB3_AXI_CLK] = &gcc_aggre2_usb3_axi_clk.clkr,
[GCC_QSPI_AHB_CLK] = &gcc_qspi_ahb_clk.clkr,
@ -3192,10 +3291,10 @@ static struct clk_regmap *gcc_msm8996_clocks[] = {
[GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
[GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
[GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr,
[GCC_DCC_AHB_ALK] = &gcc_dcc_ahb_clk.clkr,
[GCC_DCC_AHB_CLK] = &gcc_dcc_ahb_clk.clkr,
[GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK] = &gcc_aggre0_noc_mpu_cfg_ahb_clk.clkr,
[GCC_MMSS_GPLL0_DIV_CLK] = &gcc_mmss_gpll0_div_clk.clkr,
[GPLL0_OUT_MSSCC] = &gpll0_out_msscc.clkr,
[GPLL0_OUT_MSSCC_CLK] = &gpll0_out_msscc_clk.clkr,
};
static const struct qcom_reset_map gcc_msm8996_resets[] = {
@ -3317,6 +3416,8 @@ static const struct regmap_config gcc_msm8996_regmap_config = {
static const struct qcom_cc_desc gcc_msm8996_desc = {
.config = &gcc_msm8996_regmap_config,
.clks = gcc_msm8996_clocks,
.hwclks = gcc_msm8996_hws,
.num_hwclks = ARRAY_SIZE(gcc_msm8996_hws),
.num_clks = ARRAY_SIZE(gcc_msm8996_clocks),
.resets = gcc_msm8996_resets,
.num_resets = ARRAY_SIZE(gcc_msm8996_resets),
@ -3330,9 +3431,7 @@ MODULE_DEVICE_TABLE(of, gcc_msm8996_match_table);
static int gcc_msm8996_probe(struct platform_device *pdev)
{
struct clk *clk;
struct device *dev = &pdev->dev;
int i, ret = 0;
int ret = 0;
struct regmap *regmap;
regmap = qcom_cc_map(pdev, &gcc_msm8996_desc);
@ -3342,10 +3441,14 @@ static int gcc_msm8996_probe(struct platform_device *pdev)
/* Set the HMSS_AHB_CLK_ENA bit to enable the hmss_ahb_clk */
regmap_update_bits(regmap, 0x52004, BIT(21), BIT(21));
for (i = 0; i < ARRAY_SIZE(gcc_msm8996_hws); i++) {
clk = devm_clk_register(dev, gcc_msm8996_hws[i]);
if (IS_ERR(clk))
return PTR_ERR(clk);
vdd_dig.vdd_uv[1] = RPM_REGULATOR_CORNER_SVS_KRAIT;
vdd_dig.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_dig");
if (IS_ERR(vdd_dig.regulator[0])) {
if (!(PTR_ERR(vdd_dig.regulator[0]) == -EPROBE_DEFER))
dev_err(&pdev->dev,
"Unable to get vdd_dig regulator!");
return PTR_ERR(vdd_dig.regulator[0]);
}
ret = qcom_cc_really_probe(pdev, &gcc_msm8996_desc, regmap);
@ -3358,6 +3461,12 @@ static int gcc_msm8996_probe(struct platform_device *pdev)
/* This clock is used for all MMSS register access */
clk_prepare_enable(gcc_mmss_noc_cfg_ahb_clk.clkr.hw.clk);
/*
* Keep the core memory settings enabled at all times for
* gcc_mmss_bimc_gfx_clk.
*/
clk_set_flags(gcc_mmss_bimc_gfx_clk.clkr.hw.clk, CLKFLAG_RETAIN_MEM);
dev_info(&pdev->dev, "Registered GCC clocks\n");
return ret;

6
drivers/clk/qcom/gcc-msmfalcon.c
View file

@ -1229,6 +1229,7 @@ static struct clk_branch gcc_blsp1_ahb_clk = {
.enable_mask = BIT(17),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_ahb_clk",
.flags = CLK_ENABLE_HAND_OFF,
.ops = &clk_branch2_ops,
},
},
@ -1422,6 +1423,7 @@ static struct clk_branch gcc_blsp2_ahb_clk = {
.enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_ahb_clk",
.flags = CLK_ENABLE_HAND_OFF,
.ops = &clk_branch2_ops,
},
},
@ -2844,7 +2846,7 @@ static struct measure_clk_data debug_mux_priv = {
static const char *const debug_mux_parent_names[] = {
"snoc_clk",
"cnoc_clk",
"cnoc_periph",
"cnoc_periph_clk",
"bimc_clk",
"ce1_clk",
"ipa_clk",
@ -2924,6 +2926,7 @@ static const char *const debug_mux_parent_names[] = {
"gcc_ufs_rx_symbol_1_clk",
"gcc_ufs_tx_symbol_0_clk",
"gcc_usb3_phy_pipe_clk",
"mmssnoc_axi_clk",
"mmss_bimc_smmu_ahb_clk",
"mmss_bimc_smmu_axi_clk",
"mmss_camss_ahb_clk",
@ -3104,6 +3107,7 @@ static struct clk_debug_mux gcc_debug_mux = {
{ "gcc_ufs_rx_symbol_1_clk", 0x162 },
{ "gcc_ufs_tx_symbol_0_clk", 0x0EC },
{ "gcc_usb3_phy_pipe_clk", 0x040 },
{ "mmssnoc_axi_clk", 0x22, MMCC, 0x004 },
{ "mmss_bimc_smmu_ahb_clk", 0x22, MMCC, 0x00C },
{ "mmss_bimc_smmu_axi_clk", 0x22, MMCC, 0x00D },
{ "mmss_camss_ahb_clk", 0x22, MMCC, 0x037 },

5
drivers/clk/qcom/mdss/mdss-pll.c
View file

@ -133,6 +133,10 @@ static int mdss_pll_resource_parse(struct platform_device *pdev,
pll_res->pll_interface_type = MDSS_DSI_PLL_8996;
pll_res->target_id = MDSS_PLL_TARGET_8996;
pll_res->revision = 2;
} else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_msmfalcon")) {
pll_res->pll_interface_type = MDSS_DSI_PLL_8996;
pll_res->target_id = MDSS_PLL_TARGET_MSMFALCON;
pll_res->revision = 2;
} else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_8998")) {
pll_res->pll_interface_type = MDSS_DSI_PLL_8998;
} else if (!strcmp(compatible_stream, "qcom,mdss_dp_pll_8998")) {
@ -378,6 +382,7 @@ static const struct of_device_id mdss_pll_dt_match[] = {
{.compatible = "qcom,mdss_hdmi_pll_8996_v3_1p8"},
{.compatible = "qcom,mdss_dp_pll_8998"},
{.compatible = "qcom,mdss_hdmi_pll_8998"},
{.compatible = "qcom,mdss_dsi_pll_msmfalcon"},
{}
};

1
drivers/clk/qcom/mdss/mdss-pll.h
View file

@ -51,6 +51,7 @@ enum {
enum {
MDSS_PLL_TARGET_8996,
MDSS_PLL_TARGET_MSMFALCON,
};
#define DFPS_MAX_NUM_OF_FRAME_RATES 20

11
drivers/clk/qcom/mmcc-msmfalcon.c
View file

@ -529,6 +529,7 @@ static struct clk_rcg2 ahb_clk_src = {
.hid_width = 5,
.parent_map = mmcc_parent_map_10,
.freq_tbl = ftbl_ahb_clk_src,
.flags = FORCE_ENABLE_RCGR,
.clkr.hw.init = &(struct clk_init_data){
.name = "ahb_clk_src",
.parent_names = mmcc_parent_names_10,
@ -1281,6 +1282,7 @@ static struct clk_rcg2 video_core_clk_src = {
.hid_width = 5,
.parent_map = mmcc_parent_map_12,
.freq_tbl = ftbl_video_core_clk_src,
.flags = FORCE_ENABLE_RCGR,
.clkr.hw.init = &(struct clk_init_data){
.name = "video_core_clk_src",
.parent_names = mmcc_parent_names_12,
@ -1323,6 +1325,7 @@ static struct clk_branch mmss_bimc_smmu_ahb_clk = {
.parent_names = (const char *[]){
"ahb_clk_src",
},
.flags = CLK_ENABLE_HAND_OFF,
.num_parents = 1,
.ops = &clk_branch2_ops,
},
@ -1337,6 +1340,7 @@ static struct clk_branch mmss_bimc_smmu_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mmss_bimc_smmu_axi_clk",
.flags = CLK_ENABLE_HAND_OFF,
.ops = &clk_branch2_ops,
},
},
@ -2016,9 +2020,9 @@ static struct clk_branch mmss_camss_jpeg0_clk = {
},
};
static DEFINE_CLK_VOTER(mmss_camss_jpeg0_vote_clk, &mmss_camss_jpeg0_clk.c, 0);
static DEFINE_CLK_VOTER(mmss_camss_jpeg0_vote_clk, mmss_camss_jpeg0_clk, 0);
static DEFINE_CLK_VOTER(mmss_camss_jpeg0_dma_vote_clk,
&mmss_camss_jpeg0_clk.c, 0);
mmss_camss_jpeg0_clk, 0);
static struct clk_branch mmss_camss_jpeg_ahb_clk = {
.halt_reg = 0x35b4,
@ -2318,6 +2322,7 @@ static struct clk_branch mmss_mdss_ahb_clk = {
.parent_names = (const char *[]){
"ahb_clk_src",
},
.flags = CLK_ENABLE_HAND_OFF,
.num_parents = 1,
.ops = &clk_branch2_ops,
},
@ -2602,7 +2607,7 @@ static struct clk_branch mmss_mdss_mdp_clk = {
"mdp_clk_src",
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.flags = CLK_SET_RATE_PARENT | CLK_ENABLE_HAND_OFF,
.ops = &clk_branch2_ops,
},
},

95
drivers/clk/qcom/vdd-level-8996.h Normal file
View file

@ -0,0 +1,95 @@
/*
* Copyright (c) 2016, The Linux Foundation. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __QCOM_VDD_LEVEL_8996_H__
#define __QCOM_VDD_LEVEL_8996_H__
#include <linux/regulator/rpm-smd-regulator.h>
#include <linux/regulator/consumer.h>
#define VDD_DIG_FMAX_MAP1(l1, f1) \
.vdd_class = &vdd_dig, \
.rate_max = (unsigned long[VDD_DIG_NUM]) { \
[VDD_DIG_##l1] = (f1), \
}, \
.num_rate_max = VDD_DIG_NUM
#define VDD_DIG_FMAX_MAP2(l1, f1, l2, f2) \
.vdd_class = &vdd_dig, \
.rate_max = (unsigned long[VDD_DIG_NUM]) { \
[VDD_DIG_##l1] = (f1), \
[VDD_DIG_##l2] = (f2), \
}, \
.num_rate_max = VDD_DIG_NUM
#define VDD_DIG_FMAX_MAP3(l1, f1, l2, f2, l3, f3) \
.vdd_class = &vdd_dig, \
.rate_max = (unsigned long[VDD_DIG_NUM]) { \
[VDD_DIG_##l1] = (f1), \
[VDD_DIG_##l2] = (f2), \
[VDD_DIG_##l3] = (f3), \
}, \
.num_rate_max = VDD_DIG_NUM
#define VDD_DIG_FMAX_MAP4(l1, f1, l2, f2, l3, f3, l4, f4) \
.vdd_class = &vdd_dig, \
.rate_max = (unsigned long[VDD_DIG_NUM]) { \
[VDD_DIG_##l1] = (f1), \
[VDD_DIG_##l2] = (f2), \
[VDD_DIG_##l3] = (f3), \
[VDD_DIG_##l4] = (f4), \
}, \
.num_rate_max = VDD_DIG_NUM
#define VDD_MMPLL4_FMAX_MAP1(l1, f1) \
.vdd_class = &vdd_mmpll4, \
.rate_max = (unsigned long[VDD_DIG_NUM]) { \
[VDD_DIG_##l1] = (f1), \
}, \
.num_rate_max = VDD_DIG_NUM
#define VDD_MMPLL4_FMAX_MAP2(l1, f1, l2, f2) \
.vdd_class = &vdd_mmpll4, \
.rate_max = (unsigned long[VDD_DIG_NUM]) { \
[VDD_DIG_##l1] = (f1), \
[VDD_DIG_##l2] = (f2), \
}, \
.num_rate_max = VDD_DIG_NUM
#define VDD_MMPLL4_FMAX_MAP3(l1, f1, l2, f2, l3, f3) \
.vdd_class = &vdd_mmpll4, \
.rate_max = (unsigned long[VDD_DIG_NUM]) { \
[VDD_DIG_##l1] = (f1), \
[VDD_DIG_##l2] = (f2), \
[VDD_DIG_##l3] = (f3), \
}, \
.num_rate_max = VDD_DIG_NUM
enum vdd_dig_levels {
VDD_DIG_NONE,
VDD_DIG_LOWER, /* SVS2 */
VDD_DIG_LOW, /* SVS */
VDD_DIG_NOMINAL, /* NOMINAL */
VDD_DIG_HIGH, /* Turbo */
VDD_DIG_NUM
};
static int vdd_corner[] = {
RPM_REGULATOR_CORNER_NONE, /* VDD_DIG_NONE */
RPM_REGULATOR_CORNER_SVS_SOC, /* SVS2 is remapped to SVS */
RPM_REGULATOR_CORNER_SVS_SOC, /* VDD_DIG_SVS */
RPM_REGULATOR_CORNER_NORMAL, /* VDD_DIG_NOMINAL */
RPM_REGULATOR_CORNER_SUPER_TURBO, /* VDD_DIG_TURBO */
};
#endif

20
drivers/crypto/msm/qce50.c
View file

@ -2485,8 +2485,11 @@ static int _qce_sps_add_sg_data_off(struct qce_device *pce_dev,
res_within_sg = sg_dma_len(sg_src);
while (off > 0) {
if (!sg_src)
if (!sg_src) {
pr_err("broken sg list off %d nbytes %d\n",
off, nbytes);
return -ENOENT;
}
len = sg_dma_len(sg_src);
if (off < len) {
res_within_sg = len - off;
@ -2494,7 +2497,8 @@ static int _qce_sps_add_sg_data_off(struct qce_device *pce_dev,
}
off -= len;
sg_src = sg_next(sg_src);
res_within_sg = sg_dma_len(sg_src);
if (sg_src)
res_within_sg = sg_dma_len(sg_src);
}
while (nbytes > 0 && sg_src) {
len = min(nbytes, res_within_sg);
@ -2525,9 +2529,15 @@ static int _qce_sps_add_sg_data_off(struct qce_device *pce_dev,
addr += data_cnt;
len -= data_cnt;
}
sg_src = sg_next(sg_src);
off = 0;
res_within_sg = sg_dma_len(sg_src);
if (nbytes) {
sg_src = sg_next(sg_src);
if (!sg_src) {
pr_err("more data bytes %d\n", nbytes);
return -ENOMEM;
}
res_within_sg = sg_dma_len(sg_src);
off = 0;
}
}
return 0;
}

53
drivers/crypto/msm/qcrypto.c
View file

@ -821,19 +821,16 @@ static struct qcrypto_alg *_qcrypto_aead_alg_alloc(struct crypto_priv *cp,
return q_alg;
};
static int _qcrypto_cipher_cra_init(struct crypto_tfm *tfm)
static int _qcrypto_cipher_ctx_init(struct qcrypto_cipher_ctx *ctx,
struct qcrypto_alg *q_alg)
{
struct crypto_alg *alg = tfm->__crt_alg;
struct qcrypto_alg *q_alg;
struct qcrypto_cipher_ctx *ctx = crypto_tfm_ctx(tfm);
q_alg = container_of(alg, struct qcrypto_alg, cipher_alg);
if (!ctx || !q_alg) {
pr_err("ctx or q_alg is NULL\n");
return -EINVAL;
}
ctx->flags = 0;
/* update context with ptr to cp */
ctx->cp = q_alg->cp;
/* random first IV */
get_random_bytes(ctx->iv, QCRYPTO_MAX_IV_LENGTH);
if (_qcrypto_init_assign) {
@ -845,6 +842,16 @@ static int _qcrypto_cipher_cra_init(struct crypto_tfm *tfm)
INIT_LIST_HEAD(&ctx->rsp_queue);
ctx->auth_alg = QCE_HASH_LAST;
return 0;
}
static int _qcrypto_cipher_cra_init(struct crypto_tfm *tfm)
{
struct crypto_alg *alg = tfm->__crt_alg;
struct qcrypto_alg *q_alg;
struct qcrypto_cipher_ctx *ctx = crypto_tfm_ctx(tfm);
q_alg = container_of(alg, struct qcrypto_alg, cipher_alg);
return _qcrypto_cipher_ctx_init(ctx, q_alg);
};
static int _qcrypto_ahash_cra_init(struct crypto_tfm *tfm)
@ -941,13 +948,22 @@ static int _qcrypto_cra_aes_ablkcipher_init(struct crypto_tfm *tfm)
return _qcrypto_cra_ablkcipher_init(tfm);
};
static int _qcrypto_aead_cra_init(struct crypto_aead *tfm)
{
struct qcrypto_cipher_ctx *ctx = crypto_aead_ctx(tfm);
struct aead_alg *aeadalg = crypto_aead_alg(tfm);
struct qcrypto_alg *q_alg = container_of(aeadalg, struct qcrypto_alg,
aead_alg);
return _qcrypto_cipher_ctx_init(ctx, q_alg);
};
static int _qcrypto_cra_aead_sha1_init(struct crypto_aead *tfm)
{
int rc;
struct qcrypto_cipher_ctx *ctx = crypto_aead_ctx(tfm);
crypto_aead_set_reqsize(tfm, sizeof(struct qcrypto_cipher_req_ctx));
rc = _qcrypto_cipher_cra_init(&tfm->base);
rc = _qcrypto_aead_cra_init(tfm);
ctx->auth_alg = QCE_HASH_SHA1_HMAC;
return rc;
}
@ -958,7 +974,7 @@ static int _qcrypto_cra_aead_sha256_init(struct crypto_aead *tfm)
struct qcrypto_cipher_ctx *ctx = crypto_aead_ctx(tfm);
crypto_aead_set_reqsize(tfm, sizeof(struct qcrypto_cipher_req_ctx));
rc = _qcrypto_cipher_cra_init(&tfm->base);
rc = _qcrypto_aead_cra_init(tfm);
ctx->auth_alg = QCE_HASH_SHA256_HMAC;
return rc;
}
@ -969,7 +985,7 @@ static int _qcrypto_cra_aead_ccm_init(struct crypto_aead *tfm)
struct qcrypto_cipher_ctx *ctx = crypto_aead_ctx(tfm);
crypto_aead_set_reqsize(tfm, sizeof(struct qcrypto_cipher_req_ctx));
rc = _qcrypto_cipher_cra_init(&tfm->base);
rc = _qcrypto_aead_cra_init(tfm);
ctx->auth_alg = QCE_HASH_AES_CMAC;
return rc;
}
@ -980,7 +996,7 @@ static int _qcrypto_cra_aead_rfc4309_ccm_init(struct crypto_aead *tfm)
struct qcrypto_cipher_ctx *ctx = crypto_aead_ctx(tfm);
crypto_aead_set_reqsize(tfm, sizeof(struct qcrypto_cipher_req_ctx));
rc = _qcrypto_cipher_cra_init(&tfm->base);
rc = _qcrypto_aead_cra_init(tfm);
ctx->auth_alg = QCE_HASH_AES_CMAC;
return rc;
}
@ -992,7 +1008,7 @@ static int _qcrypto_cra_aead_aes_sha1_init(struct crypto_aead *tfm)
struct crypto_priv *cp = &qcrypto_dev;
crypto_aead_set_reqsize(tfm, sizeof(struct qcrypto_cipher_req_ctx));
rc = _qcrypto_cipher_cra_init(&tfm->base);
rc = _qcrypto_aead_cra_init(tfm);
if (rc)
return rc;
ctx->cipher_aes192_fb = NULL;
@ -1023,7 +1039,7 @@ static int _qcrypto_cra_aead_aes_sha256_init(struct crypto_aead *tfm)
struct crypto_priv *cp = &qcrypto_dev;
crypto_aead_set_reqsize(tfm, sizeof(struct qcrypto_cipher_req_ctx));
rc = _qcrypto_cipher_cra_init(&tfm->base);
rc = _qcrypto_aead_cra_init(tfm);
if (rc)
return rc;
ctx->cipher_aes192_fb = NULL;
@ -1828,7 +1844,7 @@ static void _qce_aead_complete(void *cookie, unsigned char *icv,
if (rctx->dir == QCE_ENCRYPT) {
/* copy the icv to dst */
scatterwalk_map_and_copy(icv, areq->dst,
areq->cryptlen,
areq->cryptlen + areq->assoclen,
ctx->authsize, 1);
} else {
@ -1836,8 +1852,9 @@ static void _qce_aead_complete(void *cookie, unsigned char *icv,
/* compare icv from src */
scatterwalk_map_and_copy(tmp,
areq->src, areq->cryptlen -
ctx->authsize, ctx->authsize, 0);
areq->src, areq->assoclen +
areq->cryptlen - ctx->authsize,
ctx->authsize, 0);
ret = memcmp(icv, tmp, ctx->authsize);
if (ret != 0)
ret = -EBADMSG;

10
drivers/gpu/msm/adreno_dispatch.c
View file

@ -604,6 +604,16 @@ static int sendcmd(struct adreno_device *adreno_dev,
if (!test_and_set_bit(ADRENO_DISPATCHER_ACTIVE,
&dispatcher->priv))
reinit_completion(&dispatcher->idle_gate);
/*
* We update power stats generally at the expire of
* cmdbatch. In cases where the cmdbatch takes a long
* time to finish, it will delay power stats update,
* in effect it will delay DCVS decision. Start a
* timer to update power state on expire of this timer.
*/
kgsl_pwrscale_midframe_timer_restart(device);
} else {
kgsl_active_count_put(device);
clear_bit(ADRENO_DISPATCHER_POWER, &dispatcher->priv);

5
drivers/gpu/msm/kgsl_pwrctrl.c
View file

@ -2355,6 +2355,7 @@ static int _init(struct kgsl_device *device)
case KGSL_STATE_ACTIVE:
kgsl_pwrctrl_irq(device, KGSL_PWRFLAGS_OFF);
del_timer_sync(&device->idle_timer);
kgsl_pwrscale_midframe_timer_cancel(device);
device->ftbl->stop(device);
/* fall through */
case KGSL_STATE_AWARE:
@ -2462,6 +2463,7 @@ _aware(struct kgsl_device *device)
case KGSL_STATE_ACTIVE:
kgsl_pwrctrl_irq(device, KGSL_PWRFLAGS_OFF);
del_timer_sync(&device->idle_timer);
kgsl_pwrscale_midframe_timer_cancel(device);
break;
case KGSL_STATE_SLUMBER:
status = kgsl_pwrctrl_enable(device);
@ -2486,6 +2488,8 @@ _nap(struct kgsl_device *device)
return -EBUSY;
}
kgsl_pwrscale_midframe_timer_cancel(device);
/*
* Read HW busy counters before going to NAP state.
* The data might be used by power scale governors
@ -2522,6 +2526,7 @@ _slumber(struct kgsl_device *device)
/* fall through */
case KGSL_STATE_NAP:
del_timer_sync(&device->idle_timer);
kgsl_pwrscale_midframe_timer_cancel(device);
if (device->pwrctrl.thermal_cycle == CYCLE_ACTIVE) {
device->pwrctrl.thermal_cycle = CYCLE_ENABLE;
del_timer_sync(&device->pwrctrl.thermal_timer);

79
drivers/gpu/msm/kgsl_pwrscale.c
View file

@ -13,6 +13,7 @@
#include <linux/export.h>
#include <linux/kernel.h>
#include <linux/hrtimer.h>
#include "kgsl.h"
#include "kgsl_pwrscale.h"
@ -37,6 +38,18 @@ static struct kgsl_popp popp_param[POPP_MAX] = {
{0, 0},
};
/**
* struct kgsl_midframe_info - midframe power stats sampling info
* @timer - midframe sampling timer
* @timer_check_ws - Updates powerstats on midframe expiry
* @device - pointer to kgsl_device
*/
static struct kgsl_midframe_info {
struct hrtimer timer;
struct work_struct timer_check_ws;
struct kgsl_device *device;
} *kgsl_midframe = NULL;
static void do_devfreq_suspend(struct work_struct *work);
static void do_devfreq_resume(struct work_struct *work);
static void do_devfreq_notify(struct work_struct *work);
@ -183,9 +196,57 @@ void kgsl_pwrscale_update(struct kgsl_device *device)
if (device->state != KGSL_STATE_SLUMBER)
queue_work(device->pwrscale.devfreq_wq,
&device->pwrscale.devfreq_notify_ws);
kgsl_pwrscale_midframe_timer_restart(device);
}
EXPORT_SYMBOL(kgsl_pwrscale_update);
void kgsl_pwrscale_midframe_timer_restart(struct kgsl_device *device)
{
if (kgsl_midframe) {
WARN_ON(!mutex_is_locked(&device->mutex));
/* If the timer is already running, stop it */
if (hrtimer_active(&kgsl_midframe->timer))
hrtimer_cancel(
&kgsl_midframe->timer);
hrtimer_start(&kgsl_midframe->timer,
ns_to_ktime(KGSL_GOVERNOR_CALL_INTERVAL
* NSEC_PER_USEC), HRTIMER_MODE_REL);
}
}
EXPORT_SYMBOL(kgsl_pwrscale_midframe_timer_restart);
void kgsl_pwrscale_midframe_timer_cancel(struct kgsl_device *device)
{
if (kgsl_midframe) {
WARN_ON(!mutex_is_locked(&device->mutex));
hrtimer_cancel(&kgsl_midframe->timer);
}
}
EXPORT_SYMBOL(kgsl_pwrscale_midframe_timer_cancel);
static void kgsl_pwrscale_midframe_timer_check(struct work_struct *work)
{
struct kgsl_device *device = kgsl_midframe->device;
mutex_lock(&device->mutex);
if (device->state == KGSL_STATE_ACTIVE)
kgsl_pwrscale_update(device);
mutex_unlock(&device->mutex);
}
static enum hrtimer_restart kgsl_pwrscale_midframe_timer(struct hrtimer *timer)
{
struct kgsl_device *device = kgsl_midframe->device;
queue_work(device->pwrscale.devfreq_wq,
&kgsl_midframe->timer_check_ws);
return HRTIMER_NORESTART;
}
/*
* kgsl_pwrscale_disable - temporarily disable the governor
* @device: The device
@ -852,6 +913,17 @@ int kgsl_pwrscale_init(struct device *dev, const char *governor)
data->bin.ctxt_aware_busy_penalty = 12000;
}
if (of_property_read_bool(device->pdev->dev.of_node,
"qcom,enable-midframe-timer")) {
kgsl_midframe = kzalloc(
sizeof(struct kgsl_midframe_info), GFP_KERNEL);
hrtimer_init(&kgsl_midframe->timer,
CLOCK_MONOTONIC, HRTIMER_MODE_REL);
kgsl_midframe->timer.function =
kgsl_pwrscale_midframe_timer;
kgsl_midframe->device = device;
}
/*
* If there is a separate GX power rail, allow
* independent modification to its voltage through
@ -900,6 +972,9 @@ int kgsl_pwrscale_init(struct device *dev, const char *governor)
INIT_WORK(&pwrscale->devfreq_suspend_ws, do_devfreq_suspend);
INIT_WORK(&pwrscale->devfreq_resume_ws, do_devfreq_resume);
INIT_WORK(&pwrscale->devfreq_notify_ws, do_devfreq_notify);
if (kgsl_midframe)
INIT_WORK(&kgsl_midframe->timer_check_ws,
kgsl_pwrscale_midframe_timer_check);
pwrscale->next_governor_call = ktime_add_us(ktime_get(),
KGSL_GOVERNOR_CALL_INTERVAL);
@ -940,9 +1015,13 @@ void kgsl_pwrscale_close(struct kgsl_device *device)
pwrscale = &device->pwrscale;
if (!pwrscale->devfreqptr)
return;
kgsl_pwrscale_midframe_timer_cancel(device);
flush_workqueue(pwrscale->devfreq_wq);
destroy_workqueue(pwrscale->devfreq_wq);
devfreq_remove_device(device->pwrscale.devfreqptr);
kfree(kgsl_midframe);
kgsl_midframe = NULL;
device->pwrscale.devfreqptr = NULL;
srcu_cleanup_notifier_head(&device->pwrscale.nh);
for (i = 0; i < KGSL_PWREVENT_MAX; i++)

3
drivers/gpu/msm/kgsl_pwrscale.h
View file

@ -122,6 +122,9 @@ void kgsl_pwrscale_busy(struct kgsl_device *device);
void kgsl_pwrscale_sleep(struct kgsl_device *device);
void kgsl_pwrscale_wake(struct kgsl_device *device);
void kgsl_pwrscale_midframe_timer_restart(struct kgsl_device *device);
void kgsl_pwrscale_midframe_timer_cancel(struct kgsl_device *device);
void kgsl_pwrscale_enable(struct kgsl_device *device);
void kgsl_pwrscale_disable(struct kgsl_device *device, bool turbo);

12
drivers/i2c/busses/i2c-msm-v2.c
View file

@ -1,4 +1,4 @@
/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@ -2236,12 +2236,12 @@ static void i2c_msm_pm_xfer_end(struct i2c_msm_ctrl *ctrl)
i2c_msm_dma_free_channels(ctrl);
i2c_msm_pm_clk_disable_unprepare(ctrl);
if (pm_runtime_enabled(ctrl->dev)) {
pm_runtime_mark_last_busy(ctrl->dev);
pm_runtime_put_autosuspend(ctrl->dev);
} else {
if (!pm_runtime_enabled(ctrl->dev))
i2c_msm_pm_suspend(ctrl->dev);
}
pm_runtime_mark_last_busy(ctrl->dev);
pm_runtime_put_autosuspend(ctrl->dev);
mutex_unlock(&ctrl->xfer.mtx);
}

8
drivers/input/misc/hbtp_input.c
View file

@ -208,9 +208,13 @@ static int hbtp_input_create_input_dev(struct hbtp_input_absinfo *absinfo)
input_mt_init_slots(input_dev, HBTP_MAX_FINGER, 0);
for (i = 0; i <= ABS_MT_LAST - ABS_MT_FIRST; i++) {
abs = absinfo + i;
if (abs->active)
input_set_abs_params(input_dev, abs->code,
if (abs->active) {
if (abs->code >= 0 && abs->code < ABS_CNT)
input_set_abs_params(input_dev, abs->code,
abs->minimum, abs->maximum, 0, 0);
else
pr_err("%s: ABS code out of bound\n", __func__);
}
}
if (hbtp->override_disp_coords) {

21
drivers/input/qpnp-power-on.c
View file

@ -31,6 +31,7 @@
#include <linux/regulator/machine.h>
#include <linux/regulator/of_regulator.h>
#include <linux/qpnp/power-on.h>
#include <linux/power_supply.h>
#define PMIC_VER_8941 0x01
#define PMIC_VERSION_REG 0x0105
@ -220,6 +221,11 @@ struct qpnp_pon {
bool store_hard_reset_reason;
};
static int pon_ship_mode_en;
module_param_named(
ship_mode_en, pon_ship_mode_en, int, S_IRUSR | S_IWUSR
);
static struct qpnp_pon *sys_reset_dev;
static DEFINE_SPINLOCK(spon_list_slock);
static LIST_HEAD(spon_dev_list);
@ -523,6 +529,8 @@ int qpnp_pon_system_pwr_off(enum pon_power_off_type type)
int rc = 0;
struct qpnp_pon *pon = sys_reset_dev;
struct qpnp_pon *tmp;
struct power_supply *batt_psy;
union power_supply_propval val;
unsigned long flags;
if (!pon)
@ -557,6 +565,19 @@ int qpnp_pon_system_pwr_off(enum pon_power_off_type type)
goto out;
}
}
/* Set ship mode here if it has been requested */
if (!!pon_ship_mode_en) {
batt_psy = power_supply_get_by_name("battery");
if (batt_psy) {
pr_debug("Set ship mode!\n");
val.intval = 1;
rc = power_supply_set_property(batt_psy,
POWER_SUPPLY_PROP_SET_SHIP_MODE, &val);
if (rc)
dev_err(&pon->pdev->dev,
"Set ship-mode failed\n");
}
}
out:
spin_unlock_irqrestore(&spon_list_slock, flags);
return rc;

20
drivers/leds/leds-qpnp-wled.c
View file

@ -108,7 +108,14 @@
#define QPNP_WLED_SWITCH_FREQ_1600_KHZ 1600
#define QPNP_WLED_SWITCH_FREQ_OVERWRITE 0x80
#define QPNP_WLED_OVP_MASK GENMASK(1, 0)
#define QPNP_WLED_TEST4_EN_VREF_UP 0x32
#define QPNP_WLED_TEST4_EN_DEB_BYPASS_ILIM_BIT BIT(6)
#define QPNP_WLED_TEST4_EN_SH_FOR_SS_BIT BIT(5)
#define QPNP_WLED_TEST4_EN_CLAMP_BIT BIT(4)
#define QPNP_WLED_TEST4_EN_SOFT_START_BIT BIT(1)
#define QPNP_WLED_TEST4_EN_VREF_UP \
(QPNP_WLED_TEST4_EN_SH_FOR_SS_BIT | \
QPNP_WLED_TEST4_EN_CLAMP_BIT | \
QPNP_WLED_TEST4_EN_SOFT_START_BIT)
#define QPNP_WLED_TEST4_EN_IIND_UP 0x1
/* sink registers */
@ -167,6 +174,7 @@
#define QPNP_WLED_SINK_TEST5_HYB 0x14
#define QPNP_WLED_SINK_TEST5_DIG 0x1E
#define QPNP_WLED_SINK_TEST5_HVG_PULL_STR_BIT BIT(3)
#define QPNP_WLED_SWITCH_FREQ_800_KHZ_CODE 0x0B
#define QPNP_WLED_SWITCH_FREQ_1600_KHZ_CODE 0x05
@ -1035,7 +1043,8 @@ static int qpnp_wled_set_disp(struct qpnp_wled *wled, u16 base_addr)
/*
* enable VREF_UP to avoid false ovp on low brightness for LCD
*/
reg = QPNP_WLED_TEST4_EN_VREF_UP;
reg = QPNP_WLED_TEST4_EN_VREF_UP
| QPNP_WLED_TEST4_EN_DEB_BYPASS_ILIM_BIT;
rc = qpnp_wled_sec_write_reg(wled,
QPNP_WLED_TEST4_REG(base_addr), reg);
if (rc)
@ -1550,10 +1559,13 @@ static int qpnp_wled_config(struct qpnp_wled *wled)
return rc;
/* Configure TEST5 register */
if (wled->dim_mode == QPNP_WLED_DIM_DIGITAL)
if (wled->dim_mode == QPNP_WLED_DIM_DIGITAL) {
reg = QPNP_WLED_SINK_TEST5_DIG;
else
} else {
reg = QPNP_WLED_SINK_TEST5_HYB;
if (wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE)
reg |= QPNP_WLED_SINK_TEST5_HVG_PULL_STR_BIT;
}
rc = qpnp_wled_sec_write_reg(wled,
QPNP_WLED_SINK_TEST5_REG(wled->sink_base), reg);

6
drivers/media/platform/msm/camera_v2/common/cam_smmu_api.c
View file

@ -1102,11 +1102,11 @@ static int cam_smmu_map_secure_buffer_and_add_to_list(int idx,
}
if (table->sgl) {
CDBG("DMA buf: %p, device: %p, attach: %p, table: %p\n",
CDBG("DMA buf: %pK, device: %pK, attach: %pK, table: %pK\n",
(void *)buf,
(void *)iommu_cb_set.cb_info[idx].dev,
(void *)attach, (void *)table);
CDBG("table sgl: %p, rc: %d, dma_address: 0x%x\n",
CDBG("table sgl: %pK, rc: %d, dma_address: 0x%x\n",
(void *)table->sgl, rc,
(unsigned int)table->sgl->dma_address);
} else {
@ -1139,7 +1139,7 @@ static int cam_smmu_map_secure_buffer_and_add_to_list(int idx,
rc = -ENOSPC;
goto err_mapping_info;
}
CDBG("dev = %p, paddr= %p, len = %u\n",
CDBG("dev = %pK, paddr= %pK, len = %u\n",
(void *)iommu_cb_set.cb_info[idx].dev,
(void *)*paddr_ptr, (unsigned int)*len_ptr);

2
drivers/media/platform/msm/camera_v2/isp/msm_isp40.c
View file

@ -1099,7 +1099,7 @@ static int msm_vfe40_start_fetch_engine_multi_pass(struct vfe_device *vfe_dev,
rc = vfe_dev->buf_mgr->ops->get_buf_by_index(
vfe_dev->buf_mgr, bufq_handle, fe_cfg->buf_idx, &buf);
if (rc < 0 || !buf) {
pr_err("%s: No fetch buffer rc= %d buf= %p\n",
pr_err("%s: No fetch buffer rc= %d buf= %pK\n",
__func__, rc, buf);
return -EINVAL;
}

2
drivers/media/platform/msm/camera_v2/isp/msm_isp_axi_util.c
View file

@ -1768,7 +1768,7 @@ int msm_isp_cfg_offline_ping_pong_address(struct vfe_device *vfe_dev,
rc = vfe_dev->buf_mgr->ops->get_buf_by_index(
vfe_dev->buf_mgr, bufq_handle, buf_idx, &buf);
if (rc < 0 || !buf) {
pr_err("%s: No fetch buffer rc= %d buf= %p\n",
pr_err("%s: No fetch buffer rc= %d buf= %pK\n",
__func__, rc, buf);
return -EINVAL;
}

2
drivers/media/platform/msm/camera_v2/pproc/cpp/msm_cpp_soc.c
View file

@ -91,7 +91,7 @@ static int cpp_get_clk_freq_tbl_dt(struct cpp_device *cpp_dev)
hw_info = &cpp_dev->hw_info;
if ((hw_info == NULL) || (of_node == NULL)) {
pr_err("Invalid hw_info %p or ofnode %p\n", hw_info, of_node);
pr_err("Invalid hw_info %pK or ofnode %pK\n", hw_info, of_node);
rc = -EINVAL;
goto err;

1
drivers/media/platform/msm/camera_v2/sensor/actuator/msm_actuator.c
View file

@ -1418,6 +1418,7 @@ static int32_t msm_actuator_config(struct msm_actuator_ctrl_t *a_ctrl,
case CFG_GET_ACTUATOR_INFO:
cdata->is_af_supported = 1;
cdata->cfg.cam_name = a_ctrl->cam_name;
rc = 0;
break;
case CFG_SET_ACTUATOR_INFO:

34
drivers/misc/qseecom.c
View file

@ -4621,6 +4621,40 @@ int qseecom_set_bandwidth(struct qseecom_handle *handle, bool high)
}
EXPORT_SYMBOL(qseecom_set_bandwidth);
int qseecom_process_listener_from_smcinvoke(struct scm_desc *desc)
{
struct qseecom_registered_app_list dummy_app_entry = { {0} };
struct qseecom_dev_handle dummy_private_data = {0};
struct qseecom_command_scm_resp resp;
int ret = 0;
if (!desc) {
pr_err("desc is NULL\n");
return -EINVAL;
}
resp.result = desc->ret[0]; /*req_cmd*/
resp.resp_type = desc->ret[1]; /*app_id*/
resp.data = desc->ret[2]; /*listener_id*/
dummy_private_data.client.app_id = desc->ret[1];
dummy_app_entry.app_id = desc->ret[1];
mutex_lock(&app_access_lock);
ret = __qseecom_process_reentrancy(&resp, &dummy_app_entry,
&dummy_private_data);
mutex_unlock(&app_access_lock);
if (ret)
pr_err("Failed to req cmd %d lsnr %d on app %d, ret = %d\n",
(int)desc->ret[0], (int)desc->ret[2],
(int)desc->ret[1], ret);
desc->ret[0] = resp.result;
desc->ret[1] = resp.resp_type;
desc->ret[2] = resp.data;
return ret;
}
EXPORT_SYMBOL(qseecom_process_listener_from_smcinvoke);
static int qseecom_send_resp(void)
{
qseecom.send_resp_flag = 1;

2
drivers/misc/qseecom_kernel.h
View file

@ -14,6 +14,7 @@
#define __QSEECOM_KERNEL_H_
#include <linux/types.h>
#include <soc/qcom/scm.h>
#define QSEECOM_ALIGN_SIZE 0x40
#define QSEECOM_ALIGN_MASK (QSEECOM_ALIGN_SIZE - 1)
@ -38,5 +39,6 @@ int qseecom_shutdown_app(struct qseecom_handle **handle);
int qseecom_send_command(struct qseecom_handle *handle, void *send_buf,
uint32_t sbuf_len, void *resp_buf, uint32_t rbuf_len);
int qseecom_set_bandwidth(struct qseecom_handle *handle, bool high);
int qseecom_process_listener_from_smcinvoke(struct scm_desc *desc);
#endif /* __QSEECOM_KERNEL_H_ */

1
drivers/net/wireless/ath/wil6210/wmi.c
View file

@ -964,6 +964,7 @@ int wmi_call(struct wil6210_priv *wil, u16 cmdid, void *buf, u16 len,
wil->reply_id = reply_id;
wil->reply_buf = reply;
wil->reply_size = reply_size;
reinit_completion(&wil->wmi_call);
spin_unlock(&wil->wmi_ev_lock);
rc = __wmi_send(wil, cmdid, buf, len);

37
drivers/platform/msm/msm_11ad/msm_11ad.c
View file

@ -33,7 +33,7 @@
#define WIGIG_DEVICE (0x0310)
#define SMMU_BASE 0x10000000 /* Device address range base */
#define SMMU_SIZE 0x40000000 /* Device address range size */
#define SMMU_SIZE ((SZ_1G * 4ULL) - SMMU_BASE)
#define WIGIG_ENABLE_DELAY 50
#define PM_OPT_SUSPEND (MSM_PCIE_CONFIG_NO_CFG_RESTORE | \
@ -87,6 +87,8 @@ struct msm11ad_ctx {
/* SMMU */
bool use_smmu; /* have SMMU enabled? */
int smmu_bypass;
int smmu_fast_map;
struct dma_iommu_mapping *mapping;
/* bus frequency scaling */
@ -596,11 +598,13 @@ static int msm_11ad_smmu_init(struct msm11ad_ctx *ctx)
{
int atomic_ctx = 1;
int rc;
int bypass_enable = 1;
if (!ctx->use_smmu)
return 0;
dev_info(ctx->dev, "Initialize SMMU, bypass = %d, fastmap = %d\n",
ctx->smmu_bypass, ctx->smmu_fast_map);
ctx->mapping = arm_iommu_create_mapping(&platform_bus_type,
SMMU_BASE, SMMU_SIZE);
if (IS_ERR_OR_NULL(ctx->mapping)) {
@ -608,7 +612,6 @@ static int msm_11ad_smmu_init(struct msm11ad_ctx *ctx)
dev_err(ctx->dev, "Failed to create IOMMU mapping (%d)\n", rc);
return rc;
}
dev_info(ctx->dev, "IOMMU mapping created: %p\n", ctx->mapping);
rc = iommu_domain_set_attr(ctx->mapping->domain,
DOMAIN_ATTR_ATOMIC,
@ -619,13 +622,24 @@ static int msm_11ad_smmu_init(struct msm11ad_ctx *ctx)
goto release_mapping;
}
rc = iommu_domain_set_attr(ctx->mapping->domain,
DOMAIN_ATTR_S1_BYPASS,
&bypass_enable);
if (rc) {
dev_err(ctx->dev, "Set bypass attribute to SMMU failed (%d)\n",
rc);
goto release_mapping;
if (ctx->smmu_bypass) {
rc = iommu_domain_set_attr(ctx->mapping->domain,
DOMAIN_ATTR_S1_BYPASS,
&ctx->smmu_bypass);
if (rc) {
dev_err(ctx->dev, "Set bypass attribute to SMMU failed (%d)\n",
rc);
goto release_mapping;
}
} else if (ctx->smmu_fast_map) {
rc = iommu_domain_set_attr(ctx->mapping->domain,
DOMAIN_ATTR_FAST,
&ctx->smmu_fast_map);
if (rc) {
dev_err(ctx->dev, "Set fast attribute to SMMU failed (%d)\n",
rc);
goto release_mapping;
}
}
rc = arm_iommu_attach_device(&ctx->pcidev->dev, ctx->mapping);
@ -870,6 +884,9 @@ static int msm_11ad_probe(struct platform_device *pdev)
ctx->use_smmu = of_property_read_bool(of_node, "qcom,smmu-support");
ctx->bus_scale = msm_bus_cl_get_pdata(pdev);
ctx->smmu_bypass = 1;
ctx->smmu_fast_map = 0;
/*== execute ==*/
/* turn device on */
rc = msm_11ad_init_vregs(ctx);

1
drivers/power/power_supply_sysfs.c
View file

@ -278,6 +278,7 @@ static struct device_attribute power_supply_attrs[] = {
POWER_SUPPLY_ATTR(parallel_percent),
POWER_SUPPLY_ATTR(pe_start),
POWER_SUPPLY_ATTR(set_ship_mode),
POWER_SUPPLY_ATTR(soc_reporting_ready),
/* Local extensions of type int64_t */
POWER_SUPPLY_ATTR(charge_counter_ext),
/* Properties of type `const char *' */

1
drivers/power/qcom-charger/fg-core.h
View file

@ -335,6 +335,7 @@ struct fg_chip {
bool recharge_soc_adjusted;
bool ki_coeff_dischg_en;
bool esr_fcc_ctrl_en;
bool soc_reporting_ready;
struct completion soc_update;
struct completion soc_ready;
struct delayed_work profile_load_work;

11
drivers/power/qcom-charger/qpnp-fg-gen3.c
View file

@ -2050,6 +2050,7 @@ done:
fg_notify_charger(chip);
chip->profile_loaded = true;
chip->soc_reporting_ready = true;
fg_dbg(chip, FG_STATUS, "profile loaded successfully");
out:
vote(chip->awake_votable, PROFILE_LOAD, false, 0);
@ -2386,6 +2387,9 @@ static int fg_psy_get_property(struct power_supply *psy,
case POWER_SUPPLY_PROP_TIME_TO_EMPTY_AVG:
rc = fg_get_time_to_empty(chip, &pval->intval);
break;
case POWER_SUPPLY_PROP_SOC_REPORTING_READY:
pval->intval = chip->soc_reporting_ready;
break;
default:
pr_err("unsupported property %d\n", psp);
rc = -EINVAL;
@ -2483,6 +2487,7 @@ static enum power_supply_property fg_psy_props[] = {
POWER_SUPPLY_PROP_CHARGE_COUNTER,
POWER_SUPPLY_PROP_TIME_TO_FULL_AVG,
POWER_SUPPLY_PROP_TIME_TO_EMPTY_AVG,
POWER_SUPPLY_PROP_SOC_REPORTING_READY,
};
static const struct power_supply_desc fg_psy_desc = {
@ -2773,9 +2778,11 @@ static irqreturn_t fg_batt_missing_irq_handler(int irq, void *data)
chip->profile_available = false;
chip->profile_loaded = false;
clear_cycle_counter(chip);
chip->soc_reporting_ready = false;
} else {
rc = fg_get_batt_profile(chip);
if (rc < 0) {
chip->soc_reporting_ready = true;
pr_err("Error in getting battery profile, rc:%d\n", rc);
return IRQ_HANDLED;
}
@ -3213,9 +3220,11 @@ static int fg_parse_dt(struct fg_chip *chip)
chip->rradc_base = base;
rc = fg_get_batt_profile(chip);
if (rc < 0)
if (rc < 0) {
chip->soc_reporting_ready = true;
pr_warn("profile for batt_id=%dKOhms not found..using OTP, rc:%d\n",
chip->batt_id_ohms / 1000, rc);
}
/* Read all the optional properties below */
rc = of_property_read_u32(node, "qcom,fg-cutoff-voltage", &temp);

31
drivers/power/reset/msm-poweroff.c
View file

@ -28,6 +28,7 @@
#include <asm/cacheflush.h>
#include <asm/system_misc.h>
#include <asm/memory.h>
#include <soc/qcom/scm.h>
#include <soc/qcom/restart.h>
@ -65,11 +66,17 @@ static struct kobject dload_kobj;
#ifdef CONFIG_QCOM_DLOAD_MODE
#define EDL_MODE_PROP "qcom,msm-imem-emergency_download_mode"
#define DL_MODE_PROP "qcom,msm-imem-download_mode"
#ifdef CONFIG_RANDOMIZE_BASE
#define KASLR_OFFSET_PROP "qcom,msm-imem-kaslr_offset"
#endif
static int in_panic;
static void *dload_mode_addr;
static bool dload_mode_enabled;
static void *emergency_dload_mode_addr;
#ifdef CONFIG_RANDOMIZE_BASE
static void *kaslr_imem_addr;
#endif
static bool scm_dload_supported;
static int dload_set(const char *val, struct kernel_param *kp);
@ -510,6 +517,28 @@ static int msm_restart_probe(struct platform_device *pdev)
pr_err("unable to map imem EDLOAD mode offset\n");
}
#ifdef CONFIG_RANDOMIZE_BASE
#define KASLR_OFFSET_BIT_MASK 0x00000000FFFFFFFF
np = of_find_compatible_node(NULL, NULL, KASLR_OFFSET_PROP);
if (!np) {
pr_err("unable to find DT imem KASLR_OFFSET node\n");
} else {
kaslr_imem_addr = of_iomap(np, 0);
if (!kaslr_imem_addr)
pr_err("unable to map imem KASLR offset\n");
}
if (kaslr_imem_addr && scm_is_secure_device()) {
__raw_writel(0xdead4ead, kaslr_imem_addr);
__raw_writel(KASLR_OFFSET_BIT_MASK &
(kimage_vaddr - KIMAGE_VADDR), kaslr_imem_addr + 4);
__raw_writel(KASLR_OFFSET_BIT_MASK &
((kimage_vaddr - KIMAGE_VADDR) >> 32),
kaslr_imem_addr + 8);
iounmap(kaslr_imem_addr);
}
#endif
np = of_find_compatible_node(NULL, NULL,
"qcom,msm-imem-dload-type");
if (!np) {
@ -603,4 +632,4 @@ static int __init msm_restart_init(void)
{
return platform_driver_register(&msm_restart_driver);
}
device_initcall(msm_restart_init);
pure_initcall(msm_restart_init);

11
drivers/regulator/Kconfig
View file

@ -925,6 +925,17 @@ config REGULATOR_CPRH_KBSS
independent voltage supplies. This driver reads both initial voltage
and CPR target quotient values out of hardware fuses.
config REGULATOR_CPR4_MMSS_LDO
bool "RBCPR3 regulator for MMSS LDO"
depends on OF
select REGULATOR_CPR3
help
This driver supports Qualcomm Technologies, Inc. MMSS graphics
processor specific features. The MMSS CPR3 controller only uses one
thread to monitor the MMSS LDO voltage requirements. This driver reads
initial voltage values out of hardware fuses and CPR target quotient
values out of device tree.
config REGULATOR_KRYO
bool "Kryo regulator driver"
depends on OF

1
drivers/regulator/Makefile
View file

@ -114,6 +114,7 @@ obj-$(CONFIG_REGULATOR_CPR3_HMSS) += cpr3-hmss-regulator.o
obj-$(CONFIG_REGULATOR_CPR3_MMSS) += cpr3-mmss-regulator.o
obj-$(CONFIG_REGULATOR_CPR4_APSS) += cpr4-apss-regulator.o
obj-$(CONFIG_REGULATOR_CPRH_KBSS) += cprh-kbss-regulator.o
obj-$(CONFIG_REGULATOR_CPR4_MMSS_LDO) += cpr4-mmss-ldo-regulator.o
obj-$(CONFIG_REGULATOR_QPNP_LABIBB) += qpnp-labibb-regulator.o
obj-$(CONFIG_REGULATOR_QPNP_LCDB) += qpnp-lcdb-regulator.o
obj-$(CONFIG_REGULATOR_STUB) += stub-regulator.o

722
drivers/regulator/cpr4-mmss-ldo-regulator.c Normal file
View file

@ -0,0 +1,722 @@
/*
* Copyright (c) 2016, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#define pr_fmt(fmt) "%s: " fmt, __func__
#include <linux/bitops.h>
#include <linux/debugfs.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_opp.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/uaccess.h>
#include <linux/regulator/driver.h>
#include <linux/regulator/machine.h>
#include <linux/regulator/of_regulator.h>
#include <linux/regulator/msm-ldo-regulator.h>
#include "cpr3-regulator.h"
#define MSMFALCON_MMSS_FUSE_CORNERS 6
/**
* struct cpr4_msmfalcon_mmss_fuses - MMSS specific fuse data for MSMFALCON
* @init_voltage: Initial (i.e. open-loop) voltage fuse parameter value
* for each fuse corner (raw, not converted to a voltage)
* @offset_voltage: The closed-loop voltage margin adjustment fuse parameter
* value for each fuse corner (raw, not converted to a
* voltage)
* @cpr_fusing_rev: CPR fusing revision fuse parameter value
* @ldo_enable: The ldo enable fuse parameter for each fuse corner
* indicates that VDD_GFX can be configured to LDO mode in
* the corresponding fuse corner.
* @ldo_cpr_cl_enable: A fuse parameter indicates that GFX CPR can be
* configured to operate in closed-loop mode when VDD_GFX
* is configured for LDO sub-regulated mode.
*
* This struct holds the values for all of the fuses read from memory.
*/
struct cpr4_msmfalcon_mmss_fuses {
u64 init_voltage[MSMFALCON_MMSS_FUSE_CORNERS];
u64 offset_voltage[MSMFALCON_MMSS_FUSE_CORNERS];
u64 cpr_fusing_rev;
u64 ldo_enable[MSMFALCON_MMSS_FUSE_CORNERS];
u64 ldo_cpr_cl_enable;
};
/* Fuse combos 0 - 7 map to CPR fusing revision 0 - 7 */
#define CPR4_MSMFALCON_MMSS_FUSE_COMBO_COUNT 8
/*
* MSMFALCON MMSS fuse parameter locations:
*
* Structs are organized with the following dimensions:
* Outer: 0 to 3 for fuse corners from lowest to highest corner
* Inner: large enough to hold the longest set of parameter segments which
* fully defines a fuse parameter, +1 (for NULL termination).
* Each segment corresponds to a contiguous group of bits from a
* single fuse row. These segments are concatentated together in
* order to form the full fuse parameter value. The segments for
* a given parameter may correspond to different fuse rows.
*/
static const struct cpr3_fuse_param
msmfalcon_mmss_init_voltage_param[MSMFALCON_MMSS_FUSE_CORNERS][2] = {
{{65, 39, 43}, {} },
{{65, 39, 43}, {} },
{{65, 34, 38}, {} },
{{65, 34, 38}, {} },
{{65, 29, 33}, {} },
{{65, 24, 28}, {} },
};
static const struct cpr3_fuse_param msmfalcon_cpr_fusing_rev_param[] = {
{71, 34, 36},
{},
};
static const struct cpr3_fuse_param
msmfalcon_mmss_offset_voltage_param[MSMFALCON_MMSS_FUSE_CORNERS][2] = {
{{} },
{{} },
{{} },
{{65, 52, 55}, {} },
{{65, 48, 51}, {} },
{{65, 44, 47}, {} },
};
static const struct cpr3_fuse_param
msmfalcon_mmss_ldo_enable_param[MSMFALCON_MMSS_FUSE_CORNERS][2] = {
{{73, 62, 62}, {} },
{{73, 61, 61}, {} },
{{73, 60, 60}, {} },
{{73, 59, 59}, {} },
{{73, 58, 58}, {} },
{{73, 57, 57}, {} },
};
static const struct cpr3_fuse_param msmfalcon_ldo_cpr_cl_enable_param[] = {
{71, 38, 38},
{},
};
/* Additional MSMFALCON specific data: */
/* Open loop voltage fuse reference voltages in microvolts */
static const int msmfalcon_mmss_fuse_ref_volt[MSMFALCON_MMSS_FUSE_CORNERS] = {
584000,
644000,
724000,
788000,
868000,
924000,
};
#define MSMFALCON_MMSS_FUSE_STEP_VOLT 10000
#define MSMFALCON_MMSS_OFFSET_FUSE_STEP_VOLT 10000
#define MSMFALCON_MMSS_VOLTAGE_FUSE_SIZE 5
#define MSMFALCON_MMSS_CPR_SENSOR_COUNT 11
#define MSMFALCON_MMSS_CPR_CLOCK_RATE 19200000
/**
* cpr4_msmfalcon_mmss_read_fuse_data() - load MMSS specific fuse parameter
* values
* @vreg: Pointer to the CPR3 regulator
*
* This function allocates a cpr4_msmfalcon_mmss_fuses struct, fills it with
* values read out of hardware fuses, and finally copies common fuse values
* into the regulator struct.
*
* Return: 0 on success, errno on failure
*/
static int cpr4_msmfalcon_mmss_read_fuse_data(struct cpr3_regulator *vreg)
{
void __iomem *base = vreg->thread->ctrl->fuse_base;
struct cpr4_msmfalcon_mmss_fuses *fuse;
int i, rc;
fuse = devm_kzalloc(vreg->thread->ctrl->dev, sizeof(*fuse), GFP_KERNEL);
if (!fuse)
return -ENOMEM;
rc = cpr3_read_fuse_param(base, msmfalcon_cpr_fusing_rev_param,
&fuse->cpr_fusing_rev);
if (rc) {
cpr3_err(vreg, "Unable to read CPR fusing revision fuse, rc=%d\n",
rc);
return rc;
}
cpr3_info(vreg, "CPR fusing revision = %llu\n", fuse->cpr_fusing_rev);
rc = cpr3_read_fuse_param(base, msmfalcon_ldo_cpr_cl_enable_param,
&fuse->ldo_cpr_cl_enable);
if (rc) {
cpr3_err(vreg, "Unable to read ldo cpr closed-loop enable fuse, rc=%d\n",
rc);
return rc;
}
for (i = 0; i < MSMFALCON_MMSS_FUSE_CORNERS; i++) {
rc = cpr3_read_fuse_param(base,
msmfalcon_mmss_init_voltage_param[i],
&fuse->init_voltage[i]);
if (rc) {
cpr3_err(vreg, "Unable to read fuse-corner %d initial voltage fuse, rc=%d\n",
i, rc);
return rc;
}
rc = cpr3_read_fuse_param(base,
msmfalcon_mmss_offset_voltage_param[i],
&fuse->offset_voltage[i]);
if (rc) {
cpr3_err(vreg, "Unable to read fuse-corner %d offset voltage fuse, rc=%d\n",
i, rc);
return rc;
}
rc = cpr3_read_fuse_param(base,
msmfalcon_mmss_ldo_enable_param[i],
&fuse->ldo_enable[i]);
if (rc) {
cpr3_err(vreg, "Unable to read fuse-corner %d ldo enable fuse, rc=%d\n",
i, rc);
return rc;
}
}
vreg->fuse_combo = fuse->cpr_fusing_rev;
if (vreg->fuse_combo >= CPR4_MSMFALCON_MMSS_FUSE_COMBO_COUNT) {
cpr3_err(vreg, "invalid CPR fuse combo = %d found, not in range 0 - %d\n",
vreg->fuse_combo,
CPR4_MSMFALCON_MMSS_FUSE_COMBO_COUNT - 1);
return -EINVAL;
}
vreg->cpr_rev_fuse = fuse->cpr_fusing_rev;
vreg->fuse_corner_count = MSMFALCON_MMSS_FUSE_CORNERS;
vreg->platform_fuses = fuse;
return 0;
}
/**
* cpr3_msmfalcon_mmss_calculate_open_loop_voltages() - calculate the open-loop
* voltage for each corner of a CPR3 regulator
* @vreg: Pointer to the CPR3 regulator
*
* Return: 0 on success, errno on failure
*/
static int cpr4_msmfalcon_mmss_calculate_open_loop_voltages(
struct cpr3_regulator *vreg)
{
struct cpr4_msmfalcon_mmss_fuses *fuse = vreg->platform_fuses;
int i, rc = 0;
const int *ref_volt;
int *fuse_volt;
fuse_volt = kcalloc(vreg->fuse_corner_count, sizeof(*fuse_volt),
GFP_KERNEL);
if (!fuse_volt)
return -ENOMEM;
ref_volt = msmfalcon_mmss_fuse_ref_volt;
for (i = 0; i < vreg->fuse_corner_count; i++) {
fuse_volt[i] = cpr3_convert_open_loop_voltage_fuse(ref_volt[i],
MSMFALCON_MMSS_FUSE_STEP_VOLT, fuse->init_voltage[i],
MSMFALCON_MMSS_VOLTAGE_FUSE_SIZE);
cpr3_info(vreg, "fuse_corner[%d] open-loop=%7d uV\n",
i, fuse_volt[i]);
}
rc = cpr3_adjust_fused_open_loop_voltages(vreg, fuse_volt);
if (rc) {
cpr3_err(vreg, "fused open-loop voltage adjustment failed, rc=%d\n",
rc);
goto done;
}
for (i = 1; i < vreg->fuse_corner_count; i++) {
if (fuse_volt[i] < fuse_volt[i - 1]) {
cpr3_debug(vreg, "fuse corner %d voltage=%d uV < fuse corner %d voltage=%d uV; overriding: fuse corner %d voltage=%d\n",
i, fuse_volt[i], i - 1, fuse_volt[i - 1],
i, fuse_volt[i - 1]);
fuse_volt[i] = fuse_volt[i - 1];
}
}
for (i = 0; i < vreg->corner_count; i++)
vreg->corner[i].open_loop_volt
= fuse_volt[vreg->corner[i].cpr_fuse_corner];
cpr3_debug(vreg, "unadjusted per-corner open-loop voltages:\n");
for (i = 0; i < vreg->corner_count; i++)
cpr3_debug(vreg, "open-loop[%2d] = %d uV\n", i,
vreg->corner[i].open_loop_volt);
rc = cpr3_adjust_open_loop_voltages(vreg);
if (rc)
cpr3_err(vreg, "open-loop voltage adjustment failed, rc=%d\n",
rc);
done:
kfree(fuse_volt);
return rc;
}
/**
* cpr4_mmss_parse_ldo_mode_data() - Parse the LDO mode enable state for each
* corner of a CPR3 regulator
* @vreg: Pointer to the CPR3 regulator
*
* This function considers 2 sets of data: one set from device node and other
* set from fuses and applies set intersection to decide the final LDO mode
* enable state of each corner. If the device node configuration is not
* specified, then the function applies LDO mode disable for all corners.
*
* Return: 0 on success, errno on failure
*/
static int cpr4_mmss_parse_ldo_mode_data(struct cpr3_regulator *vreg)
{
struct cpr4_msmfalcon_mmss_fuses *fuse = vreg->platform_fuses;
int i, rc = 0;
u32 *ldo_allowed;
char *prop_str = "qcom,cpr-corner-allow-ldo-mode";
if (!of_find_property(vreg->of_node, prop_str, NULL)) {
cpr3_debug(vreg, "%s property is missing. LDO mode is disabled for all corners\n",
prop_str);
return 0;
}
ldo_allowed = kcalloc(vreg->corner_count, sizeof(*ldo_allowed),
GFP_KERNEL);
if (!ldo_allowed)
return -ENOMEM;
rc = cpr3_parse_corner_array_property(vreg, prop_str, 1, ldo_allowed);
if (rc) {
cpr3_err(vreg, "%s read failed, rc=%d\n", prop_str, rc);
goto done;
}
for (i = 0; i < vreg->corner_count; i++)
vreg->corner[i].ldo_mode_allowed
= (ldo_allowed[i] && fuse->ldo_enable[i]);
done:
kfree(ldo_allowed);
return rc;
}
/**
* cpr4_mmss_parse_corner_operating_mode() - Parse the CPR closed-loop operation
* enable state for each corner of a CPR3 regulator
* @vreg: Pointer to the CPR3 regulator
*
* This function ensures that closed-loop operation is enabled only for LDO
* mode allowed corners.
*
* Return: 0 on success, errno on failure
*/
static int cpr4_mmss_parse_corner_operating_mode(struct cpr3_regulator *vreg)
{
struct cpr4_msmfalcon_mmss_fuses *fuse = vreg->platform_fuses;
int i, rc = 0;
u32 *use_closed_loop;
char *prop_str = "qcom,cpr-corner-allow-closed-loop";
if (!of_find_property(vreg->of_node, prop_str, NULL)) {
cpr3_debug(vreg, "%s property is missing. Use open-loop for all corners\n",
prop_str);
for (i = 0; i < vreg->corner_count; i++)
vreg->corner[i].use_open_loop = true;
return 0;
}
use_closed_loop = kcalloc(vreg->corner_count, sizeof(*use_closed_loop),
GFP_KERNEL);
if (!use_closed_loop)
return -ENOMEM;
rc = cpr3_parse_corner_array_property(vreg, prop_str, 1,
use_closed_loop);
if (rc) {
cpr3_err(vreg, "%s read failed, rc=%d\n", prop_str, rc);
goto done;
}
for (i = 0; i < vreg->corner_count; i++)
vreg->corner[i].use_open_loop
= !(fuse->ldo_cpr_cl_enable && use_closed_loop[i]
&& vreg->corner[i].ldo_mode_allowed);
done:
kfree(use_closed_loop);
return rc;
}
/**
* cpr4_mmss_parse_corner_data() - parse MMSS corner data from device tree
* properties of the regulator's device node
* @vreg: Pointer to the CPR3 regulator
*
* Return: 0 on success, errno on failure
*/
static int cpr4_mmss_parse_corner_data(struct cpr3_regulator *vreg)
{
int i, rc;
u32 *temp;
rc = cpr3_parse_common_corner_data(vreg);
if (rc) {
cpr3_err(vreg, "error reading corner data, rc=%d\n", rc);
return rc;
}
temp = kcalloc(vreg->corner_count * CPR3_RO_COUNT, sizeof(*temp),
GFP_KERNEL);
if (!temp)
return -ENOMEM;
rc = cpr3_parse_corner_array_property(vreg, "qcom,cpr-target-quotients",
CPR3_RO_COUNT, temp);
if (rc) {
cpr3_err(vreg, "could not load target quotients, rc=%d\n", rc);
goto done;
}
for (i = 0; i < vreg->corner_count; i++)
memcpy(vreg->corner[i].target_quot, &temp[i * CPR3_RO_COUNT],
sizeof(*temp) * CPR3_RO_COUNT);
done:
kfree(temp);
return rc;
}
/**
* cpr4_mmss_print_settings() - print out MMSS CPR configuration settings into
* the kernel log for debugging purposes
* @vreg: Pointer to the CPR3 regulator
*/
static void cpr4_mmss_print_settings(struct cpr3_regulator *vreg)
{
struct cpr3_corner *corner;
int i;
cpr3_debug(vreg, "Corner: Frequency (Hz), Fuse Corner, Floor (uV), Open-Loop (uV), Ceiling (uV)\n");
for (i = 0; i < vreg->corner_count; i++) {
corner = &vreg->corner[i];
cpr3_debug(vreg, "%3d: %10u, %2d, %7d, %7d, %7d\n",
i, corner->proc_freq, corner->cpr_fuse_corner,
corner->floor_volt, corner->open_loop_volt,
corner->ceiling_volt);
}
}
/**
* cpr4_mmss_init_thread() - perform all steps necessary to initialize the
* configuration data for a CPR3 thread
* @thread: Pointer to the CPR3 thread
*
* Return: 0 on success, errno on failure
*/
static int cpr4_mmss_init_thread(struct cpr3_thread *thread)
{
struct cpr3_controller *ctrl = thread->ctrl;
struct cpr3_regulator *vreg = &thread->vreg[0];
int rc;
rc = cpr3_parse_common_thread_data(thread);
if (rc) {
cpr3_err(vreg, "unable to read CPR thread data from device tree, rc=%d\n",
rc);
return rc;
}
if (!of_find_property(ctrl->dev->of_node, "vdd-thread0-ldo-supply",
NULL)) {
cpr3_err(vreg, "ldo supply regulator is not specified\n");
return -EINVAL;
}
vreg->ldo_regulator = devm_regulator_get(ctrl->dev, "vdd-thread0-ldo");
if (IS_ERR(vreg->ldo_regulator)) {
rc = PTR_ERR(vreg->ldo_regulator);
if (rc != -EPROBE_DEFER)
cpr3_err(vreg, "unable to request vdd-thread0-ldo regulator, rc=%d\n",
rc);
return rc;
}
vreg->ldo_mode_allowed = !of_property_read_bool(vreg->of_node,
"qcom,ldo-disable");
vreg->ldo_regulator_bypass = BHS_MODE;
vreg->ldo_type = CPR3_LDO300;
rc = cpr4_msmfalcon_mmss_read_fuse_data(vreg);
if (rc) {
cpr3_err(vreg, "unable to read CPR fuse data, rc=%d\n", rc);
return rc;
}
rc = cpr4_mmss_parse_corner_data(vreg);
if (rc) {
cpr3_err(vreg, "unable to read CPR corner data from device tree, rc=%d\n",
rc);
return rc;
}
rc = cpr4_msmfalcon_mmss_calculate_open_loop_voltages(vreg);
if (rc) {
cpr3_err(vreg, "unable to calculate open-loop voltages, rc=%d\n",
rc);
return rc;
}
rc = cpr3_limit_open_loop_voltages(vreg);
if (rc) {
cpr3_err(vreg, "unable to limit open-loop voltages, rc=%d\n",
rc);
return rc;
}
cpr3_open_loop_voltage_as_ceiling(vreg);
rc = cpr3_limit_floor_voltages(vreg);
if (rc) {
cpr3_err(vreg, "unable to limit floor voltages, rc=%d\n", rc);
return rc;
}
rc = cpr4_mmss_parse_ldo_mode_data(vreg);
if (rc) {
cpr3_err(vreg, "unable to parse ldo mode data, rc=%d\n", rc);
return rc;
}
rc = cpr4_mmss_parse_corner_operating_mode(vreg);
if (rc) {
cpr3_err(vreg, "unable to parse closed-loop operating mode data, rc=%d\n",
rc);
return rc;
}
cpr4_mmss_print_settings(vreg);
return 0;
}
/**
* cpr4_mmss_init_controller() - perform MMSS CPR4 controller specific
* initializations
* @ctrl: Pointer to the CPR3 controller
*
* Return: 0 on success, errno on failure
*/
static int cpr4_mmss_init_controller(struct cpr3_controller *ctrl)
{
int rc;
rc = cpr3_parse_common_ctrl_data(ctrl);
if (rc) {
if (rc != -EPROBE_DEFER)
cpr3_err(ctrl, "unable to parse common controller data, rc=%d\n",
rc);
return rc;
}
ctrl->sensor_count = MSMFALCON_MMSS_CPR_SENSOR_COUNT;
/*
* MMSS only has one thread (0) so the zeroed array does not need
* further modification.
*/
ctrl->sensor_owner = devm_kcalloc(ctrl->dev, ctrl->sensor_count,
sizeof(*ctrl->sensor_owner), GFP_KERNEL);
if (!ctrl->sensor_owner)
return -ENOMEM;
ctrl->cpr_clock_rate = MSMFALCON_MMSS_CPR_CLOCK_RATE;
ctrl->ctrl_type = CPR_CTRL_TYPE_CPR4;
ctrl->support_ldo300_vreg = true;
/*
* Use fixed step quotient if specified otherwise use dynamic
* calculated per RO step quotient
*/
of_property_read_u32(ctrl->dev->of_node,
"qcom,cpr-step-quot-fixed",
&ctrl->step_quot_fixed);
ctrl->use_dynamic_step_quot = !ctrl->step_quot_fixed;
/* iface_clk is optional for msmfalcon */
ctrl->iface_clk = NULL;
ctrl->bus_clk = devm_clk_get(ctrl->dev, "bus_clk");
if (IS_ERR(ctrl->bus_clk)) {
rc = PTR_ERR(ctrl->bus_clk);
if (rc != -EPROBE_DEFER)
cpr3_err(ctrl, "unable request bus clock, rc=%d\n",
rc);
return rc;
}
return 0;
}
static int cpr4_mmss_regulator_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct cpr3_controller *ctrl;
int rc;
if (!dev->of_node) {
dev_err(dev, "Device tree node is missing\n");
return -EINVAL;
}
ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
if (!ctrl)
return -ENOMEM;
ctrl->dev = dev;
/* Set to false later if anything precludes CPR operation. */
ctrl->cpr_allowed_hw = true;
rc = of_property_read_string(dev->of_node, "qcom,cpr-ctrl-name",
&ctrl->name);
if (rc) {
cpr3_err(ctrl, "unable to read qcom,cpr-ctrl-name, rc=%d\n",
rc);
return rc;
}
rc = cpr3_map_fuse_base(ctrl, pdev);
if (rc) {
cpr3_err(ctrl, "could not map fuse base address\n");
return rc;
}
rc = cpr3_allocate_threads(ctrl, 0, 0);
if (rc) {
cpr3_err(ctrl, "failed to allocate CPR thread array, rc=%d\n",
rc);
return rc;
}
if (ctrl->thread_count != 1) {
cpr3_err(ctrl, "expected 1 thread but found %d\n",
ctrl->thread_count);
return -EINVAL;
} else if (ctrl->thread[0].vreg_count != 1) {
cpr3_err(ctrl, "expected 1 regulator but found %d\n",
ctrl->thread[0].vreg_count);
return -EINVAL;
}
rc = cpr4_mmss_init_controller(ctrl);
if (rc) {
if (rc != -EPROBE_DEFER)
cpr3_err(ctrl, "failed to initialize CPR controller parameters, rc=%d\n",
rc);
return rc;
}
rc = cpr4_mmss_init_thread(&ctrl->thread[0]);
if (rc) {
cpr3_err(&ctrl->thread[0].vreg[0], "thread initialization failed, rc=%d\n",
rc);
return rc;
}
rc = cpr3_mem_acc_init(&ctrl->thread[0].vreg[0]);
if (rc) {
cpr3_err(ctrl, "failed to initialize mem-acc configuration, rc=%d\n",
rc);
return rc;
}
platform_set_drvdata(pdev, ctrl);
return cpr3_regulator_register(pdev, ctrl);
}
static int cpr4_mmss_regulator_remove(struct platform_device *pdev)
{
struct cpr3_controller *ctrl = platform_get_drvdata(pdev);
return cpr3_regulator_unregister(ctrl);
}
static int cpr4_mmss_regulator_suspend(struct platform_device *pdev,
pm_message_t state)
{
struct cpr3_controller *ctrl = platform_get_drvdata(pdev);
return cpr3_regulator_suspend(ctrl);
}
static int cpr4_mmss_regulator_resume(struct platform_device *pdev)
{
struct cpr3_controller *ctrl = platform_get_drvdata(pdev);
return cpr3_regulator_resume(ctrl);
}
/* Data corresponds to the SoC revision */
static const struct of_device_id cpr4_mmss_regulator_match_table[] = {
{
.compatible = "qcom,cpr4-msmfalcon-mmss-ldo-regulator",
.data = (void *)NULL,
},
};
static struct platform_driver cpr4_mmss_regulator_driver = {
.driver = {
.name = "qcom,cpr4-mmss-ldo-regulator",
.of_match_table = cpr4_mmss_regulator_match_table,
.owner = THIS_MODULE,
},
.probe = cpr4_mmss_regulator_probe,
.remove = cpr4_mmss_regulator_remove,
.suspend = cpr4_mmss_regulator_suspend,
.resume = cpr4_mmss_regulator_resume,
};
static int cpr_regulator_init(void)
{
return platform_driver_register(&cpr4_mmss_regulator_driver);
}
static void cpr_regulator_exit(void)
{
platform_driver_unregister(&cpr4_mmss_regulator_driver);
}
MODULE_DESCRIPTION("CPR4 MMSS LDO regulator driver");
MODULE_LICENSE("GPL v2");
arch_initcall(cpr_regulator_init);
module_exit(cpr_regulator_exit);

14
drivers/soc/qcom/avtimer.c
View file

@ -1,4 +1,4 @@
/* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
/* Copyright (c) 2012-2016, The Linux Foundation. All rights reserved.
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@ -331,9 +331,17 @@ static long avtimer_ioctl(struct file *file, unsigned int ioctl_num,
switch (ioctl_num) {
case IOCTL_GET_AVTIMER_TICK:
{
uint64_t avtimer_tick;
uint64_t avtimer_tick = 0;
int rc;
rc = avcs_core_query_timer(&avtimer_tick);
if (rc) {
pr_err("%s: Error: Invalid AV Timer tick, rc = %d\n",
__func__, rc);
return rc;
}
avcs_core_query_timer(&avtimer_tick);
pr_debug_ratelimited("%s: AV Timer tick: time %llx\n",
__func__, avtimer_tick);
if (copy_to_user((void *) ioctl_param, &avtimer_tick,

2
drivers/soc/qcom/icnss.c
View file

@ -781,7 +781,7 @@ static int icnss_unmap_msa_permissions(struct icnss_priv *priv, u32 index)
u32 size;
u32 dest_vmids[1] = {VMID_HLOS};
int source_vmlist[3] = {VMID_MSS_MSA, VMID_WLAN, 0};
int dest_perms[1] = {PERM_READ|PERM_WRITE};
int dest_perms[1] = {PERM_READ|PERM_WRITE|PERM_EXEC};
int source_nelems = 0;
int dest_nelems = sizeof(dest_vmids)/sizeof(u32);

8
drivers/soc/qcom/smcinvoke.c
View file

@ -22,6 +22,8 @@
#include <soc/qcom/scm.h>
#include <asm/cacheflush.h>
#include "smcinvoke_object.h"
#include <soc/qcom/qseecomi.h>
#include "../../misc/qseecom_kernel.h"
#define SMCINVOKE_TZ_PARAM_ID 0x224
#define SMCINVOKE_TZ_CMD 0x32000600
@ -198,6 +200,12 @@ static int prepare_send_scm_msg(const uint8_t *in_buf, size_t in_buf_len,
dmac_flush_range(out_buf, out_buf + outbuf_flush_size);
ret = scm_call2(SMCINVOKE_TZ_CMD, &desc);
/* process listener request */
if (!ret && (desc.ret[0] == QSEOS_RESULT_INCOMPLETE ||
desc.ret[0] == QSEOS_RESULT_BLOCKED_ON_LISTENER))
ret = qseecom_process_listener_from_smcinvoke(&desc);
*smcinvoke_result = (int32_t)desc.ret[1];
if (ret || desc.ret[1] || desc.ret[2] || desc.ret[0]) {
pr_err("SCM call failed with ret val = %d %d %d %d\n",

15
drivers/soc/qcom/spcom.c
View file

@ -272,6 +272,8 @@ static struct spcom_device *spcom_dev;
static int spcom_create_channel_chardev(const char *name);
static int spcom_open(struct spcom_channel *ch, unsigned int timeout_msec);
static int spcom_close(struct spcom_channel *ch);
static void spcom_notify_rx_abort(void *handle, const void *priv,
const void *pkt_priv);
/**
* spcom_is_ready() - driver is initialized and ready.
@ -467,6 +469,13 @@ static void spcom_notify_state(void *handle, const void *priv, unsigned event)
* This may happen upon remote SSR.
*/
pr_err("GLINK_REMOTE_DISCONNECTED, ch [%s].\n", ch->name);
/*
* Abort any blocking read() operation.
* The glink notification might be after REMOTE_DISCONNECT.
*/
spcom_notify_rx_abort(NULL, ch, NULL);
/*
* after glink_close(),
* expecting notify GLINK_LOCAL_DISCONNECTED
@ -515,7 +524,7 @@ static void spcom_notify_rx_abort(void *handle, const void *priv,
pr_debug("ch [%s] pending rx aborted.\n", ch->name);
if (spcom_is_channel_connected(ch)) {
if (spcom_is_channel_connected(ch) && (!ch->rx_abort)) {
ch->rx_abort = true;
complete_all(&ch->rx_done);
}
@ -535,9 +544,9 @@ static void spcom_notify_tx_abort(void *handle, const void *priv,
pr_debug("ch [%s] pending tx aborted.\n", ch->name);
if (spcom_is_channel_connected(ch)) {
complete_all(&ch->tx_done);
if (spcom_is_channel_connected(ch) && (!ch->tx_abort)) {
ch->tx_abort = true;
complete_all(&ch->tx_done);
}
}

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