diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index 933a208392bd..6d12ddb3e245 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -935,6 +935,8 @@ static int clk_gfx3d_src_set_rate_and_parent(struct clk_hw *hw,
 }
 
 const struct clk_ops clk_gfx3d_src_ops = {
+	.enable = clk_rcg2_enable,
+	.disable = clk_rcg2_disable,
 	.is_enabled = clk_rcg2_is_enabled,
 	.get_parent = clk_rcg2_get_parent,
 	.set_parent = clk_rcg2_set_parent,
diff --git a/drivers/clk/qcom/gpucc-msmfalcon.c b/drivers/clk/qcom/gpucc-msmfalcon.c
index a2127e2629c7..f194abb471cd 100644
--- a/drivers/clk/qcom/gpucc-msmfalcon.c
+++ b/drivers/clk/qcom/gpucc-msmfalcon.c
@@ -84,12 +84,12 @@ static struct pll_vco gpu_vco[] = {
 	{ 250000000,   500000000, 3 },
 };
 
-/* 640MHz configuration */
+/* 800MHz configuration */
 static const struct pll_config gpu_pll0_config = {
-	.l = 0x21,
+	.l = 0x29,
 	.config_ctl_val = 0x4001055b,
-	.alpha = 0x55555600,
-	.alpha_u = 0x55,
+	.alpha = 0xaaaaab00,
+	.alpha_u = 0xaa,
 	.alpha_en_mask = BIT(24),
 	.vco_val = 0x2 << 20,
 	.vco_mask = 0x3 << 20,