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Merge branch 'clk-fixes' into clk-next

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* clk-fixes:
  drivers: clk: st: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x
  clk: check for invalid parent index of orphans in __clk_init()
This commit is contained in:
Stephen Boyd 2015-09-17 12:28:41 -07:00
commit ab5c342992
3 changed files with 12 additions and 11 deletions
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3
drivers/clk/clk.c
View file

@ -2437,7 +2437,8 @@ static int __clk_init(struct device *dev, struct clk *clk_user)
hlist_for_each_entry_safe(orphan, tmp2, &clk_orphan_list, child_node) { hlist_for_each_entry_safe(orphan, tmp2, &clk_orphan_list, child_node) {
if (orphan->num_parents && orphan->ops->get_parent) { if (orphan->num_parents && orphan->ops->get_parent) {
i = orphan->ops->get_parent(orphan->hw); i = orphan->ops->get_parent(orphan->hw);
if (!strcmp(core->name, orphan->parent_names[i])) if (i >= 0 && i < orphan->num_parents &&
!strcmp(core->name, orphan->parent_names[i]))
clk_core_reparent(orphan, core); clk_core_reparent(orphan, core);
continue; continue;
} }

8
drivers/clk/st/clkgen-fsyn.c
View file

@ -307,7 +307,7 @@ static const struct clkgen_quadfs_data st_fs660c32_F_416 = {
.get_rate = clk_fs660c32_dig_get_rate, .get_rate = clk_fs660c32_dig_get_rate,
}; };
static const struct clkgen_quadfs_data st_fs660c32_C_407 = { static const struct clkgen_quadfs_data st_fs660c32_C = {
.nrst_present = true, .nrst_present = true,
.nrst = { CLKGEN_FIELD(0x2f0, 0x1, 0), .nrst = { CLKGEN_FIELD(0x2f0, 0x1, 0),
CLKGEN_FIELD(0x2f0, 0x1, 1), CLKGEN_FIELD(0x2f0, 0x1, 1),
@ -350,7 +350,7 @@ static const struct clkgen_quadfs_data st_fs660c32_C_407 = {
.get_rate = clk_fs660c32_dig_get_rate, .get_rate = clk_fs660c32_dig_get_rate,
}; };
static const struct clkgen_quadfs_data st_fs660c32_D_407 = { static const struct clkgen_quadfs_data st_fs660c32_D = {
.nrst_present = true, .nrst_present = true,
.nrst = { CLKGEN_FIELD(0x2a0, 0x1, 0), .nrst = { CLKGEN_FIELD(0x2a0, 0x1, 0),
CLKGEN_FIELD(0x2a0, 0x1, 1), CLKGEN_FIELD(0x2a0, 0x1, 1),
@ -1077,11 +1077,11 @@ static const struct of_device_id quadfs_of_match[] = {
}, },
{ {
.compatible = "st,stih407-quadfs660-C", .compatible = "st,stih407-quadfs660-C",
.data = &st_fs660c32_C_407 .data = &st_fs660c32_C
}, },
{ {
.compatible = "st,stih407-quadfs660-D", .compatible = "st,stih407-quadfs660-D",
.data = &st_fs660c32_D_407 .data = &st_fs660c32_D
}, },
{} {}
}; };

12
drivers/clk/st/clkgen-pll.c
View file

@ -193,7 +193,7 @@ static const struct clkgen_pll_data st_pll3200c32_407_a0 = {
.ops = &stm_pll3200c32_ops, .ops = &stm_pll3200c32_ops,
}; };
static const struct clkgen_pll_data st_pll3200c32_407_c0_0 = { static const struct clkgen_pll_data st_pll3200c32_cx_0 = {
/* 407 C0 PLL0 */ /* 407 C0 PLL0 */
.pdn_status = CLKGEN_FIELD(0x2a0, 0x1, 8), .pdn_status = CLKGEN_FIELD(0x2a0, 0x1, 8),
.locked_status = CLKGEN_FIELD(0x2a0, 0x1, 24), .locked_status = CLKGEN_FIELD(0x2a0, 0x1, 24),
@ -205,7 +205,7 @@ static const struct clkgen_pll_data st_pll3200c32_407_c0_0 = {
.ops = &stm_pll3200c32_ops, .ops = &stm_pll3200c32_ops,
}; };
static const struct clkgen_pll_data st_pll3200c32_407_c0_1 = { static const struct clkgen_pll_data st_pll3200c32_cx_1 = {
/* 407 C0 PLL1 */ /* 407 C0 PLL1 */
.pdn_status = CLKGEN_FIELD(0x2c8, 0x1, 8), .pdn_status = CLKGEN_FIELD(0x2c8, 0x1, 8),
.locked_status = CLKGEN_FIELD(0x2c8, 0x1, 24), .locked_status = CLKGEN_FIELD(0x2c8, 0x1, 24),
@ -624,12 +624,12 @@ static const struct of_device_id c32_pll_of_match[] = {
.data = &st_pll3200c32_407_a0, .data = &st_pll3200c32_407_a0,
}, },
{ {
.compatible = "st,stih407-plls-c32-c0_0", .compatible = "st,plls-c32-cx_0",
.data = &st_pll3200c32_407_c0_0, .data = &st_pll3200c32_cx_0,
}, },
{ {
.compatible = "st,stih407-plls-c32-c0_1", .compatible = "st,plls-c32-cx_1",
.data = &st_pll3200c32_407_c0_1, .data = &st_pll3200c32_cx_1,
}, },
{ {
.compatible = "st,stih407-plls-c32-a9", .compatible = "st,stih407-plls-c32-a9",