ARM: dts: msm: specify UART configuration on msmfalcon.
Initial support for all BLSP UARTs with default configuration and disabled state such that clients can overwrite and enable respective UART instance as per need. Change-Id: I15ef73049cee76c6ea5b3916d9281bbd9fdfc563 Signed-off-by: Mukesh Kumar Savaliya <msavaliy@codeaurora.org>
This commit is contained in:
Mukesh Kumar Savaliya
parent
1e17007652
commit
abcf426a00
2 changed files with 253 additions and 0 deletions
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@ -226,4 +226,152 @@
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<&clock_gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>;
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status = "disabled";
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};
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blsp1_uart1_hs: uart@c16f000 { /* BLSP1 UART1 */
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compatible = "qcom,msm-hsuart-v14";
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reg = <0xc16f000 0x200>,
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<0xc144000 0x1f000>;
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reg-names = "core_mem", "bam_mem";
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interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
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#address-cells = <0>;
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interrupt-parent = <&blsp1_uart1_hs>;
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interrupts = <0 1 2>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0xffffffff>;
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interrupt-map = <0 &intc 0 0 107 0
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1 &intc 0 0 238 0
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2 &tlmm 1 0>;
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qcom,inject-rx-on-wakeup;
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qcom,rx-char-to-inject = <0xfd>;
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qcom,bam-tx-ep-pipe-index = <0>;
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qcom,bam-rx-ep-pipe-index = <1>;
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qcom,master-id = <86>;
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clock-names = "core_clk", "iface_clk";
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clocks = <&clock_gcc GCC_BLSP1_UART1_APPS_CLK>,
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<&clock_gcc GCC_BLSP1_AHB_CLK>;
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pinctrl-names = "sleep", "default";
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pinctrl-0 = <&blsp1_uart1_sleep>;
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pinctrl-1 = <&blsp1_uart1_active>;
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qcom,msm-bus,name = "buart1";
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qcom,msm-bus,num-cases = <2>;
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qcom,msm-bus,num-paths = <1>;
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qcom,msm-bus,vectors-KBps =
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<86 512 0 0>,
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<86 512 500 800>;
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status = "disabled";
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};
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blsp1_uart2_hs: uart@c170000 { /* BLSP1 UART2 */
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compatible = "qcom,msm-hsuart-v14";
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reg = <0xc170000 0x200>,
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<0xc144000 0x1f000>;
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reg-names = "core_mem", "bam_mem";
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interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
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#address-cells = <0>;
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interrupt-parent = <&blsp1_uart2_hs>;
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interrupts = <0 1 2>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0xffffffff>;
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interrupt-map = <0 &intc 0 0 108 0
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1 &intc 0 0 238 0
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2 &tlmm 5 0>;
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qcom,inject-rx-on-wakeup;
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qcom,rx-char-to-inject = <0xfd>;
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qcom,bam-tx-ep-pipe-index = <2>;
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qcom,bam-rx-ep-pipe-index = <3>;
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qcom,master-id = <86>;
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clock-names = "core_clk", "iface_clk";
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clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>,
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<&clock_gcc GCC_BLSP1_AHB_CLK>;
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pinctrl-names = "sleep", "default";
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pinctrl-0 = <&blsp1_uart2_sleep>;
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pinctrl-1 = <&blsp1_uart2_active>;
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qcom,msm-bus,name = "buart2";
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qcom,msm-bus,num-cases = <2>;
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qcom,msm-bus,num-paths = <1>;
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qcom,msm-bus,vectors-KBps =
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<86 512 0 0>,
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<86 512 500 800>;
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status = "disabled";
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};
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blsp2_uart1_hs: uart@c1af000 { /* BLSP2 UART1 */
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compatible = "qcom,msm-hsuart-v14";
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reg = <0xc1af000 0x200>,
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<0xc184000 0x1f000>;
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reg-names = "core_mem", "bam_mem";
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interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
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#address-cells = <0>;
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interrupt-parent = <&blsp2_uart1_hs>;
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interrupts = <0 1 2>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0xffffffff>;
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interrupt-map = <0 &intc 0 0 113 0
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1 &intc 0 0 239 0
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2 &tlmm 17 0>;
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qcom,inject-rx-on-wakeup;
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qcom,rx-char-to-inject = <0xfd>;
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qcom,bam-tx-ep-pipe-index = <0>;
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qcom,bam-rx-ep-pipe-index = <1>;
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qcom,master-id = <84>;
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clock-names = "core_clk", "iface_clk";
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clocks = <&clock_gcc GCC_BLSP2_UART1_APPS_CLK>,
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<&clock_gcc GCC_BLSP2_AHB_CLK>;
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pinctrl-names = "sleep", "default";
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pinctrl-0 = <&blsp2_uart1_sleep>;
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pinctrl-1 = <&blsp2_uart1_active>;
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qcom,msm-bus,name = "buart3";
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qcom,msm-bus,num-cases = <2>;
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qcom,msm-bus,num-paths = <1>;
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qcom,msm-bus,vectors-KBps =
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<84 512 0 0>,
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<84 512 500 800>;
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status = "disabled";
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};
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blsp2_uart2_hs: uart@c1b0000 { /* BLSP2 UART2 */
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compatible = "qcom,msm-hsuart-v14";
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reg = <0xc1b0000 0x200>,
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<0xc184000 0x1f000>;
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reg-names = "core_mem", "bam_mem";
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interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
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#address-cells = <0>;
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interrupt-parent = <&blsp2_uart2_hs>;
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interrupts = <0 1 2>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0xffffffff>;
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interrupt-map = <0 &intc 0 0 114 0
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1 &intc 0 0 239 0
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2 &tlmm 25 0>;
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qcom,inject-rx-on-wakeup;
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qcom,rx-char-to-inject = <0xfd>;
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qcom,bam-tx-ep-pipe-index = <2>;
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qcom,bam-rx-ep-pipe-index = <3>;
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qcom,master-id = <84>;
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clock-names = "core_clk", "iface_clk";
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clocks = <&clock_gcc GCC_BLSP2_UART2_APPS_CLK>,
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<&clock_gcc GCC_BLSP2_AHB_CLK>;
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pinctrl-names = "sleep", "default";
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pinctrl-0 = <&blsp2_uart2_sleep>;
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pinctrl-1 = <&blsp2_uart2_active>;
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qcom,msm-bus,name = "buart4";
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qcom,msm-bus,num-cases = <2>;
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qcom,msm-bus,num-paths = <1>;
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qcom,msm-bus,vectors-KBps =
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<84 512 0 0>,
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<84 512 500 800>;
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status = "disabled";
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};
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};
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@ -369,5 +369,110 @@
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};
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};
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};
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/* HS UART CONFIGURATION */
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blsp1_uart1_active: blsp1_uart1_active {
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mux {
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pins = "gpio0", "gpio1", "gpio2", "gpio3";
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function = "blsp_uart1";
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};
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config {
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pins = "gpio0", "gpio1", "gpio2", "gpio3";
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drive-strength = <2>;
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bias-disable;
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};
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};
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blsp1_uart1_sleep: blsp1_uart1_sleep {
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mux {
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pins = "gpio0", "gpio1", "gpio2", "gpio3";
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function = "gpio";
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};
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config {
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pins = "gpio0", "gpio1", "gpio2", "gpio3";
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drive-strength = <2>;
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bias-disable;
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};
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};
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blsp1_uart2_active: blsp1_uart2_active {
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mux {
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pins = "gpio4", "gpio5", "gpio6", "gpio7";
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function = "blsp_uart2 ";
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};
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config {
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pins = "gpio4", "gpio5", "gpio6", "gpio7";
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drive-strength = <2>;
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bias-disable;
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};
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};
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blsp1_uart2_sleep: blsp1_uart2_sleep {
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mux {
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pins = "gpio4", "gpio5", "gpio6", "gpio7";
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function = "gpio";
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};
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config {
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pins = "gpio4", "gpio5", "gpio6", "gpio7";
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drive-strength = <2>;
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bias-disable;
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};
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};
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blsp2_uart1_active: blsp2_uart1_active {
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mux {
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pins = "gpio16", "gpio17", "gpio18", "gpio19";
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function = "blsp_uart5";
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};
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config {
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pins = "gpio16", "gpio17", "gpio18", "gpio19";
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drive-strength = <2>;
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bias-disable;
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};
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};
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blsp2_uart1_sleep: blsp2_uart1_sleep {
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mux {
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pins = "gpio16", "gpio17", "gpio18", "gpio19";
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function = "gpio";
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};
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config {
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pins = "gpio16", "gpio17", "gpio18", "gpio19";
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drive-strength = <2>;
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bias-disable;
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};
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};
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blsp2_uart2_active: blsp2_uart2_active {
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mux {
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pins = "gpio24", "gpio25", "gpio26", "gpio27";
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function = "blsp_uart6_a";
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};
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config {
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pins = "gpio24", "gpio25", "gpio26", "gpio27";
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drive-strength = <2>;
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bias-disable;
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};
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};
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blsp2_uart2_sleep: blsp2_uart2_sleep {
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mux {
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pins = "gpio24", "gpio25", "gpio26", "gpio27";
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function = "gpio";
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};
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config {
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pins = "gpio24", "gpio25", "gpio26", "gpio27";
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drive-strength = <2>;
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bias-disable;
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};
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};
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};
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};
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