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ARM: dts: msm: Move sdcc and ufs ice nodes

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As sdcc and ufs ice nodes are common between sdm660
and sdm630, move sdcc and ufs ice nodes to common
device tree file to avoid duplication of nodes.

Change-Id: I1e018ef44759e8cc3ce201e19a1e99ba6bb601bd
Signed-off-by: Brahmaji K <bkomma@codeaurora.org>
This commit is contained in:
Brahmaji K 2017-02-14 17:29:59 +05:30
parent 3a7e752617
commit ae4aca0324
2 changed files with 47 additions and 45 deletions
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47
arch/arm/boot/dts/qcom/sdm660-common.dtsi
View file

@ -25,12 +25,58 @@
status = "disabled";
};
ufs_ice: ufsice@1db0000 {
compatible = "qcom,ice";
reg = <0x1db0000 0x8000>;
qcom,enable-ice-clk;
clock-names = "ufs_core_clk", "bus_clk",
"iface_clk", "ice_core_clk";
clocks = <&clock_gcc GCC_UFS_AXI_CLK>,
<&clock_gcc GCC_UFS_CLKREF_CLK>,
<&clock_gcc GCC_UFS_AHB_CLK>,
<&clock_gcc GCC_UFS_ICE_CORE_CLK>;
qcom,op-freq-hz = <0>, <0>, <0>, <300000000>;
vdd-hba-supply = <&gdsc_ufs>;
qcom,msm-bus,name = "ufs_ice_noc";
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<1 650 0 0>, /* No vote */
<1 650 1000 0>; /* Max. bandwidth */
qcom,bus-vector-names = "MIN",
"MAX";
qcom,instance-type = "ufs";
};
sdcc1_ice: sdcc1ice@c0c8000 {
compatible = "qcom,ice";
reg = <0xc0c8000 0x8000>;
qcom,enable-ice-clk;
clock-names = "ice_core_clk_src", "ice_core_clk",
"bus_clk", "iface_clk";
clocks = <&clock_gcc SDCC1_ICE_CORE_CLK_SRC>,
<&clock_gcc GCC_SDCC1_ICE_CORE_CLK>,
<&clock_gcc GCC_SDCC1_APPS_CLK>,
<&clock_gcc GCC_SDCC1_AHB_CLK>;
qcom,op-freq-hz = <300000000>, <0>, <0>, <0>;
qcom,msm-bus,name = "sdcc_ice_noc";
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<78 512 0 0>, /* No vote */
<78 512 1000 0>; /* Max. bandwidth */
qcom,bus-vector-names = "MIN",
"MAX";
qcom,instance-type = "sdcc";
};
ufs1: ufshc@1da4000 {
compatible = "qcom,ufshc";
reg = <0x1da4000 0x3000>;
interrupts = <0 265 0>;
phys = <&ufsphy1>;
phy-names = "ufsphy";
ufs-qcom-crypto = <&ufs_ice>;
clock-names =
"core_clk",
@ -415,6 +461,7 @@
qcom,bus-width = <8>;
qcom,large-address-bus;
sdhc-msm-crypto = <&sdcc1_ice>;
qcom,devfreq,freq-table = <50000000 200000000>;

45
arch/arm/boot/dts/qcom/sdm660.dtsi
View file

@ -1307,51 +1307,6 @@
< 2457600 >;
};
ufs_ice: ufsice@1db0000 {
compatible = "qcom,ice";
reg = <0x1db0000 0x8000>;
qcom,enable-ice-clk;
clock-names = "ufs_core_clk", "bus_clk",
"iface_clk", "ice_core_clk";
clocks = <&clock_gcc GCC_UFS_AXI_CLK>,
<&clock_gcc GCC_UFS_CLKREF_CLK>,
<&clock_gcc GCC_UFS_AHB_CLK>,
<&clock_gcc GCC_UFS_ICE_CORE_CLK>;
qcom,op-freq-hz = <0>, <0>, <0>, <300000000>;
vdd-hba-supply = <&gdsc_ufs>;
qcom,msm-bus,name = "ufs_ice_noc";
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<1 650 0 0>, /* No vote */
<1 650 1000 0>; /* Max. bandwidth */
qcom,bus-vector-names = "MIN",
"MAX";
qcom,instance-type = "ufs";
};
sdcc1_ice: sdcc1ice@c0c8000 {
compatible = "qcom,ice";
reg = <0xc0c8000 0x8000>;
qcom,enable-ice-clk;
clock-names = "ice_core_clk_src", "ice_core_clk",
"bus_clk", "iface_clk";
clocks = <&clock_gcc SDCC1_ICE_CORE_CLK_SRC>,
<&clock_gcc GCC_SDCC1_ICE_CORE_CLK>,
<&clock_gcc GCC_SDCC1_APPS_CLK>,
<&clock_gcc GCC_SDCC1_AHB_CLK>;
qcom,op-freq-hz = <300000000>, <0>, <0>, <0>;
qcom,msm-bus,name = "sdcc_ice_noc";
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<78 512 0 0>, /* No vote */
<78 512 1000 0>; /* Max. bandwidth */
qcom,bus-vector-names = "MIN",
"MAX";
qcom,instance-type = "sdcc";
};
sdhc_1: sdhci@c0c4000 {
compatible = "qcom,sdhci-msm-v5";
reg = <0xc0c4000 0x1000>, <0xc0c5000 0x1000>;