cnss2: Add QMI updates for Genoa PCIe

Add qmi updates to pass the msi config for copy engine and
host memory information for CE to update the read index.

Change-Id: I8861659e54cfb25ae64a23a3f02f1e0fce6d372d
Signed-off-by: Jayachandran Sreekumaran <jsreekum@codeaurora.org>
This commit is contained in:
Jayachandran Sreekumaran 2018-07-04 14:24:26 +05:30 committed by Gerrit - the friendly Code Review server
parent a5a34b69d4
commit b00eda857b
3 changed files with 155 additions and 1 deletions

View file

@ -37,6 +37,7 @@
#define FW_READY_TIMEOUT 20000
#define FW_ASSERT_TIMEOUT 5000
#define CNSS_EVENT_PENDING 2989
#define CE_MSI_NAME "CE"
static struct cnss_plat_data *plat_env;
@ -249,7 +250,7 @@ int cnss_wlan_enable(struct device *dev,
{
struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
struct wlfw_wlan_cfg_req_msg_v01 req;
u32 i;
u32 i, ce_id, num_vectors, user_base_data, base_vector;
int ret = 0;
if (plat_priv->device_id == QCA6174_DEVICE_ID)
@ -299,6 +300,19 @@ int cnss_wlan_enable(struct device *dev,
req.svc_cfg[i].pipe_num = config->ce_svc_cfg[i].pipe_num;
}
if (config->num_shadow_reg_cfg) {
req.shadow_reg_valid = 1;
if (config->num_shadow_reg_cfg >
QMI_WLFW_MAX_NUM_SHADOW_REG_V01)
req.shadow_reg_len = QMI_WLFW_MAX_NUM_SHADOW_REG_V01;
else
req.shadow_reg_len = config->num_shadow_reg_cfg;
memcpy(req.shadow_reg, config->shadow_reg_cfg,
sizeof(struct wlfw_shadow_reg_cfg_s_v01)
* req.shadow_reg_len);
}
req.shadow_reg_v2_valid = 1;
if (config->num_shadow_reg_v2_cfg >
QMI_WLFW_MAX_NUM_SHADOW_REG_V2_V01)
@ -310,6 +324,30 @@ int cnss_wlan_enable(struct device *dev,
sizeof(struct wlfw_shadow_reg_v2_cfg_s_v01)
* req.shadow_reg_v2_len);
if (config->rri_over_ddr_cfg_valid) {
req.rri_over_ddr_cfg_valid = 1;
req.rri_over_ddr_cfg.base_addr_low =
config->rri_over_ddr_cfg.base_addr_low;
req.rri_over_ddr_cfg.base_addr_high =
config->rri_over_ddr_cfg.base_addr_high;
}
if (plat_priv->device_id == QCN7605_DEVICE_ID) {
ret = cnss_get_user_msi_assignment(dev, CE_MSI_NAME,
&num_vectors,
&user_base_data,
&base_vector);
if (!ret) {
req.msi_cfg_valid = 1;
req.msi_cfg_len = QMI_WLFW_MAX_NUM_CE_V01;
for (ce_id = 0; ce_id < QMI_WLFW_MAX_NUM_CE_V01;
ce_id++) {
req.msi_cfg[ce_id].ce_id = ce_id;
req.msi_cfg[ce_id].msi_vector =
(ce_id % num_vectors) + base_vector;
}
}
}
ret = cnss_wlfw_wlan_cfg_send_sync(plat_priv, &req);
if (ret)
goto out;

View file

@ -144,6 +144,60 @@ static struct elem_info wlfw_shadow_reg_v2_cfg_s_v01_ei[] = {
},
};
static struct elem_info wlfw_rri_over_ddr_cfg_s_v01_ei[] = {
{
.data_type = QMI_UNSIGNED_4_BYTE,
.elem_len = 1,
.elem_size = sizeof(u32),
.is_array = NO_ARRAY,
.tlv_type = 0,
.offset = offsetof(struct
wlfw_rri_over_ddr_cfg_s_v01,
base_addr_low),
},
{
.data_type = QMI_UNSIGNED_4_BYTE,
.elem_len = 1,
.elem_size = sizeof(u32),
.is_array = NO_ARRAY,
.tlv_type = 0,
.offset = offsetof(struct
wlfw_rri_over_ddr_cfg_s_v01,
base_addr_high),
},
{
.data_type = QMI_EOTI,
.is_array = NO_ARRAY,
.tlv_type = QMI_COMMON_TLV_TYPE,
},
};
static struct elem_info wlfw_msi_cfg_s_v01_ei[] = {
{
.data_type = QMI_UNSIGNED_2_BYTE,
.elem_len = 1,
.elem_size = sizeof(u16),
.is_array = NO_ARRAY,
.tlv_type = 0,
.offset = offsetof(struct wlfw_msi_cfg_s_v01,
ce_id),
},
{
.data_type = QMI_UNSIGNED_2_BYTE,
.elem_len = 1,
.elem_size = sizeof(u16),
.is_array = NO_ARRAY,
.tlv_type = 0,
.offset = offsetof(struct wlfw_msi_cfg_s_v01,
msi_vector),
},
{
.data_type = QMI_EOTI,
.is_array = NO_ARRAY,
.tlv_type = QMI_COMMON_TLV_TYPE,
},
};
static struct elem_info wlfw_memory_region_info_s_v01_ei[] = {
{
.data_type = QMI_UNSIGNED_8_BYTE,
@ -921,6 +975,53 @@ struct elem_info wlfw_wlan_cfg_req_msg_v01_ei[] = {
shadow_reg_v2),
.ei_array = wlfw_shadow_reg_v2_cfg_s_v01_ei,
},
{
.data_type = QMI_OPT_FLAG,
.elem_len = 1,
.elem_size = sizeof(u8),
.is_array = NO_ARRAY,
.tlv_type = 0x15,
.offset = offsetof(struct wlfw_wlan_cfg_req_msg_v01,
rri_over_ddr_cfg_valid),
},
{
.data_type = QMI_STRUCT,
.elem_len = 1,
.elem_size = sizeof(struct wlfw_rri_over_ddr_cfg_s_v01),
.is_array = NO_ARRAY,
.tlv_type = 0x15,
.offset = offsetof(struct wlfw_wlan_cfg_req_msg_v01,
rri_over_ddr_cfg),
.ei_array = wlfw_rri_over_ddr_cfg_s_v01_ei,
},
{
.data_type = QMI_OPT_FLAG,
.elem_len = 1,
.elem_size = sizeof(u8),
.is_array = NO_ARRAY,
.tlv_type = 0x16,
.offset = offsetof(struct wlfw_wlan_cfg_req_msg_v01,
msi_cfg_valid),
},
{
.data_type = QMI_DATA_LEN,
.elem_len = 1,
.elem_size = sizeof(u8),
.is_array = NO_ARRAY,
.tlv_type = 0x16,
.offset = offsetof(struct wlfw_wlan_cfg_req_msg_v01,
msi_cfg_len),
},
{
.data_type = QMI_STRUCT,
.elem_len = QMI_WLFW_MAX_NUM_CE_V01,
.elem_size = sizeof(struct wlfw_msi_cfg_s_v01),
.is_array = VAR_LEN_ARRAY,
.tlv_type = 0x16,
.offset = offsetof(struct wlfw_wlan_cfg_req_msg_v01,
msi_cfg),
.ei_array = wlfw_msi_cfg_s_v01_ei,
},
{
.data_type = QMI_EOTI,
.is_array = NO_ARRAY,

View file

@ -170,6 +170,16 @@ struct wlfw_shadow_reg_v2_cfg_s_v01 {
u32 addr;
};
struct wlfw_rri_over_ddr_cfg_s_v01 {
u32 base_addr_low;
u32 base_addr_high;
};
struct wlfw_msi_cfg_s_v01 {
u16 ce_id;
u16 msi_vector;
};
struct wlfw_memory_region_info_s_v01 {
u64 region_addr;
u32 size;
@ -312,6 +322,11 @@ struct wlfw_wlan_cfg_req_msg_v01 {
u32 shadow_reg_v2_len;
struct wlfw_shadow_reg_v2_cfg_s_v01
shadow_reg_v2[QMI_WLFW_MAX_NUM_SHADOW_REG_V2_V01];
u8 rri_over_ddr_cfg_valid;
struct wlfw_rri_over_ddr_cfg_s_v01 rri_over_ddr_cfg;
u8 msi_cfg_valid;
u32 msi_cfg_len;
struct wlfw_msi_cfg_s_v01 msi_cfg[QMI_WLFW_MAX_NUM_CE_V01];
};
#define WLFW_WLAN_CFG_REQ_MSG_V01_MAX_MSG_LEN 803