evie/android_kernel_oneplus_msm8998
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msm: mdss: wait4vsync required for DFPS

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There is possibility that the time of mdp flush bit set
and the time of dsi flush bit are cross vsync boundary.
Therefore wait4vsync is needed to guarantee both flush
bits are set within same vsync period regardless of mdp
revision.

CRs-Fixed: 766349
Change-Id: I5fd1b7c94f119d8e5f1fdd2ceb5476ed27a730fc
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
This commit is contained in:
Kuogee Hsieh 2014-12-02 10:40:41 -08:00 • committed by David Keitel
parent 24794eeebd
commit b088d2f6a0
1 changed files with 13 additions and 17 deletions
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30
drivers/video/fbdev/msm/mdss_mdp_intf_video.c
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@ -902,7 +902,6 @@ static int mdss_mdp_video_config_fps(struct mdss_mdp_ctl *ctl,
== DFPS_IMMEDIATE_PORCH_UPDATE_MODE_VFP || == DFPS_IMMEDIATE_PORCH_UPDATE_MODE_VFP ||
pdata->panel_info.dfps_update pdata->panel_info.dfps_update
== DFPS_IMMEDIATE_PORCH_UPDATE_MODE_HFP) { == DFPS_IMMEDIATE_PORCH_UPDATE_MODE_HFP) {
bool wait4vsync;
unsigned long flags; unsigned long flags;
if (!ctx->timegen_en) { if (!ctx->timegen_en) {
pr_err("TG is OFF. DFPS mode invalid\n"); pr_err("TG is OFF. DFPS mode invalid\n");
@ -910,27 +909,24 @@ static int mdss_mdp_video_config_fps(struct mdss_mdp_ctl *ctl,
} }
/* /*
* MDP INTF registers are double buffered starting from * there is possibility that the time of mdp flush
* MDP v1.5. No need to wait for vsync on these targets. * bit set and the time of dsi flush bit are cross
* vsync boundary. therefore wait4vsync is needed
* to guarantee both flush bits are set within same
* vsync period regardless of mdp revision.
*/ */
wait4vsync = (mdata->mdp_rev < MDSS_MDP_HW_REV_105); rc = mdss_mdp_video_dfps_wait4vsync(ctl);
if (rc < 0) {
if (wait4vsync) { pr_err("Error during wait4vsync\n");
rc = mdss_mdp_video_dfps_wait4vsync(ctl); return rc;
if (rc < 0) {
pr_err("Error during wait4vsync\n");
return rc;
}
} }
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_ON); mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_ON);
spin_lock_irqsave(&ctx->dfps_lock, flags); spin_lock_irqsave(&ctx->dfps_lock, flags);
if (wait4vsync) { rc = mdss_mdp_video_dfps_check_line_cnt(ctl);
rc = mdss_mdp_video_dfps_check_line_cnt(ctl); if (rc < 0)
if (rc < 0) goto exit_dfps;
goto exit_dfps;
}
rc = mdss_mdp_video_fps_update(ctx, pdata, new_fps); rc = mdss_mdp_video_fps_update(ctx, pdata, new_fps);
if (rc < 0) { if (rc < 0) {
@ -959,7 +955,7 @@ static int mdss_mdp_video_config_fps(struct mdss_mdp_ctl *ctl,
* MDP INTF registers support DB on targets * MDP INTF registers support DB on targets
* starting from MDP v1.5. * starting from MDP v1.5.
*/ */
if (!wait4vsync) if (mdata->mdp_rev >= MDSS_MDP_HW_REV_105)
mdss_mdp_video_timegen_flush(ctl, sctx); mdss_mdp_video_timegen_flush(ctl, sctx);
exit_dfps: exit_dfps: