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arm64: Rework alternate sequence for ARM erratum 845719

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The workaround for erratum 845719 is currently using
a branch between two alternate sequences, which is
quite fragile, and that we are going to break as we
rework the alternative code.

This patch reworks the workaround to fit in a single
alternative sequence. The generated code itself is
unchanged.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This commit is contained in:
Marc Zyngier 2015-06-03 14:36:23 +01:00 • committed by Catalin Marinas
parent 10b48f7ef2
commit b0dd9c02d4
1 changed files with 15 additions and 12 deletions
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27
arch/arm64/kernel/entry.S
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@ -124,21 +124,24 @@
msr sp_el0, x23 msr sp_el0, x23
#ifdef CONFIG_ARM64_ERRATUM_845719 #ifdef CONFIG_ARM64_ERRATUM_845719
alternative_insn \
"nop", \ #undef SEQUENCE_ORG
"tbz x22, #4, 1f", \ #undef SEQUENCE_ALT
ARM64_WORKAROUND_845719
#ifdef CONFIG_PID_IN_CONTEXTIDR #ifdef CONFIG_PID_IN_CONTEXTIDR
alternative_insn \
"nop; nop", \ #define SEQUENCE_ORG "nop ; nop ; nop"
"mrs x29, contextidr_el1; msr contextidr_el1, x29; 1:", \ #define SEQUENCE_ALT "tbz x22, #4, 1f ; mrs x29, contextidr_el1; msr contextidr_el1, x29; 1:"
ARM64_WORKAROUND_845719
#else #else
alternative_insn \
"nop", \ #define SEQUENCE_ORG "nop ; nop"
"msr contextidr_el1, xzr; 1:", \ #define SEQUENCE_ALT "tbz x22, #4, 1f ; msr contextidr_el1, xzr; 1:"
ARM64_WORKAROUND_845719
#endif #endif
alternative_insn SEQUENCE_ORG, SEQUENCE_ALT, ARM64_WORKAROUND_845719
#endif #endif
.endif .endif
msr elr_el1, x21 // set up the return data msr elr_el1, x21 // set up the return data