ath9k_hw: Add a function to read sqsum_dvc.
Add a function to observe the delta VC of BB_PLL. For a good chip, the sqsum_dvc is below 2000. Signed-off-by: Vivek Natarajan <vnatarajan@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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3 changed files with 20 additions and 0 deletions
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@ -668,6 +668,19 @@ static void ath9k_hw_init_qos(struct ath_hw *ah)
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REGWRITE_BUFFER_FLUSH(ah);
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REGWRITE_BUFFER_FLUSH(ah);
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}
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}
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unsigned long ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
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{
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REG_WRITE(ah, PLL3, (REG_READ(ah, PLL3) & ~(PLL3_DO_MEAS_MASK)));
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udelay(100);
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REG_WRITE(ah, PLL3, (REG_READ(ah, PLL3) | PLL3_DO_MEAS_MASK));
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while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0)
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udelay(100);
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return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
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}
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EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
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static void ath9k_hw_init_pll(struct ath_hw *ah,
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static void ath9k_hw_init_pll(struct ath_hw *ah,
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struct ath9k_channel *chan)
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struct ath9k_channel *chan)
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{
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{
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@ -928,6 +928,7 @@ void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
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void ath9k_hw_reset_tsf(struct ath_hw *ah);
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void ath9k_hw_reset_tsf(struct ath_hw *ah);
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void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
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void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
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void ath9k_hw_init_global_settings(struct ath_hw *ah);
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void ath9k_hw_init_global_settings(struct ath_hw *ah);
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unsigned long ar9003_get_pll_sqsum_dvc(struct ath_hw *ah);
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void ath9k_hw_set11nmac2040(struct ath_hw *ah);
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void ath9k_hw_set11nmac2040(struct ath_hw *ah);
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void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
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void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
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void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
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void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
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@ -1129,6 +1129,12 @@ enum {
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#define AR_RTC_PLL_CLKSEL 0x00000300
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#define AR_RTC_PLL_CLKSEL 0x00000300
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#define AR_RTC_PLL_CLKSEL_S 8
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#define AR_RTC_PLL_CLKSEL_S 8
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#define PLL3 0x16188
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#define PLL3_DO_MEAS_MASK 0x40000000
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#define PLL4 0x1618c
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#define PLL4_MEAS_DONE 0x8
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#define SQSUM_DVC_MASK 0x007ffff8
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#define AR_RTC_RESET \
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#define AR_RTC_RESET \
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((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0040) : 0x7040)
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((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0040) : 0x7040)
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#define AR_RTC_RESET_EN (0x00000001)
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#define AR_RTC_RESET_EN (0x00000001)
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