From b1c51424b14ec2bf4900eb32323166c3e17d110a Mon Sep 17 00:00:00 2001 From: Mayank Rana Date: Tue, 29 Mar 2016 11:11:28 -0700 Subject: [PATCH] usb: qmp: phy: Make sure QMP PHY reset write is completed Add explicit memory barrier after programming USB3_PHY_SW_RESET register which makes sure that above write is not cached. If this register write is cached, then phy driver is timing out with checking PCS status. In some cases, L2 cache memory error is seen when that register write is flushed whereas usb phy clock is turned off. CRs-Fixed: 990963 Change-Id: Iebe8cb4034721e76fa5ea63e33304b9dc0243797 Signed-off-by: Mayank Rana --- drivers/usb/phy/phy-msm-ssusb-qmp.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/usb/phy/phy-msm-ssusb-qmp.c b/drivers/usb/phy/phy-msm-ssusb-qmp.c index 9af1a75c724e..cacb46378c94 100644 --- a/drivers/usb/phy/phy-msm-ssusb-qmp.c +++ b/drivers/usb/phy/phy-msm-ssusb-qmp.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. + * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -274,6 +274,9 @@ static int msm_ssphy_qmp_init(struct usb_phy *uphy) writel_relaxed(0x03, phy->base + phy->phy_reg[USB3_PHY_START]); writel_relaxed(0x00, phy->base + phy->phy_reg[USB3_PHY_SW_RESET]); + /* Make sure above write completed to bring PHY out of reset */ + mb(); + /* Wait for PHY initialization to be done */ do { if (readl_relaxed(phy->base +