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staging: comedi: ni_stc.h: tidy up NI_M_PLL_STATUS_REG bits

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Rename the CamelCase and convert the enum into defines. Use the BIT()
macro to define the bits.

Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Reviewed-by: Ian Abbott <abbotti@mev.co.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
H Hartley Sweeten 2015-05-01 14:58:38 -07:00 • committed by Greg Kroah-Hartman
parent b965e6a4ab
commit b1c7064528
2 changed files with 2 additions and 5 deletions
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2
drivers/staging/comedi/drivers/ni_mio_common.c
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@ -4740,7 +4740,7 @@ static int ni_mseries_set_pll_master_clock(struct comedi_device *dev,
devpriv->clock_source = source; devpriv->clock_source = source;
/* it seems to typically take a few hundred microseconds for PLL to lock */ /* it seems to typically take a few hundred microseconds for PLL to lock */
for (i = 0; i < timeout; ++i) { for (i = 0; i < timeout; ++i) {
if (ni_readw(dev, NI_M_PLL_STATUS_REG) & MSeries_PLL_Locked_Bit) if (ni_readw(dev, NI_M_PLL_STATUS_REG) & NI_M_PLL_STATUS_LOCKED)
break; break;
udelay(1); udelay(1);
} }

5
drivers/staging/comedi/drivers/ni_stc.h
View file

@ -991,6 +991,7 @@ static const struct comedi_lrange range_ni_E_ao_ext;
#define NI_M_PLL_MAX_MULTIPLIER 0x100 #define NI_M_PLL_MAX_MULTIPLIER 0x100
#define NI_M_PLL_CTRL_MULTIPLIER(x) (((x) & 0xff) << 0) #define NI_M_PLL_CTRL_MULTIPLIER(x) (((x) & 0xff) << 0)
#define NI_M_PLL_STATUS_REG 0x1c8 #define NI_M_PLL_STATUS_REG 0x1c8
#define NI_M_PLL_STATUS_LOCKED BIT(0)
#define NI_M_PFI_OUT_SEL_REG(x) (0x1d0 + ((x) * 2)) #define NI_M_PFI_OUT_SEL_REG(x) (0x1d0 + ((x) * 2))
#define NI_M_PFI_DI_REG 0x1dc #define NI_M_PFI_DI_REG 0x1dc
#define NI_M_PFI_DO_REG 0x1de #define NI_M_PFI_DO_REG 0x1de
@ -1007,10 +1008,6 @@ static const struct comedi_lrange range_ni_E_ao_ext;
#define NI_M_STATIC_AI_CTRL_REG(x) ((x) ? (0x260 + (x)) : 0x064) #define NI_M_STATIC_AI_CTRL_REG(x) ((x) ? (0x260 + (x)) : 0x064)
#define NI_M_AO_REF_ATTENUATION_REG(x) (0x264 + (x)) #define NI_M_AO_REF_ATTENUATION_REG(x) (0x264 + (x))
enum MSeries_PLL_Status {
MSeries_PLL_Locked_Bit = 0x1
};
enum MSeries_AI_Config_FIFO_Bypass_Bits { enum MSeries_AI_Config_FIFO_Bypass_Bits {
MSeries_AI_Bypass_Channel_Mask = 0x7, MSeries_AI_Bypass_Channel_Mask = 0x7,
MSeries_AI_Bypass_Bank_Mask = 0x78, MSeries_AI_Bypass_Bank_Mask = 0x78,