msm: mdss: fix pll stop sequence for msm8996 target

Turning off pll digital block before link clocks leads
to clock status stuck ON. Ideally, DSI driver should
first stop the lanes, followed by link clock stop
and pll disable. This change implements these
recommended sequence for both DSI controllers.

Change-Id: Ibe3061a65bad2dbfdffd9505d469f10f62a6e39d
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>

drivers/clk/msm/mdss/mdss-dsi-pll-8996-util.c

@@ -272,6 +272,7 @@ static void dsi_pll_disable(struct clk *c)
 {
 	struct dsi_pll_vco_clk *vco = to_vco_clk(c);
 	struct mdss_pll_resources *pll = vco->priv;
+	struct mdss_pll_resources *slave;
 
 	if (!pll->pll_on &&
 		mdss_pll_resource_enable(pll, true)) {
@@ -280,14 +281,25 @@ static void dsi_pll_disable(struct clk *c)
 	}
 
 	pll->handoff_resources = false;
+	slave = pll->slave;
 
 	dsi_pll_stop_8996(pll->pll_base);
 
 	/* stop pll output */
 	MDSS_PLL_REG_W(pll->pll_base, DSIPHY_PLL_CLKBUFLR_EN, 0);
-
 	/* stop clk */
 	MDSS_PLL_REG_W(pll->pll_base, DSIPHY_CMN_GLBL_TEST_CTRL, 0);
+	/* stop digital block */
+	MDSS_PLL_REG_W(pll->pll_base, DSIPHY_CMN_CTRL_0, 0x0);
+
+	if (slave) {
+		/* stop pll output */
+		MDSS_PLL_REG_W(pll->pll_base, DSIPHY_PLL_CLKBUFLR_EN, 0);
+		/* stop clk */
+		MDSS_PLL_REG_W(pll->pll_base, DSIPHY_CMN_GLBL_TEST_CTRL, 0);
+		/* stop digital block */
+		MDSS_PLL_REG_W(pll->pll_base, DSIPHY_CMN_CTRL_0, 0x0);
+	}
 
 	mdss_pll_resource_enable(pll, false);
 

drivers/video/fbdev/msm/msm_mdss_io_8974.c

@@ -120,7 +120,7 @@ static void mdss_dsi_phy_lane_shutdown(struct mdss_dsi_ctrl_pdata *ctrl)
 	}
 
 	if (IS_MDSS_MAJOR_MINOR_SAME(ctrl->hw_rev, MDSS_DSI_HW_REV_104))
-		MIPI_OUTP(ctrl->phy_io.base + DSIPHY_CMN_CTRL_0, 0x0000);
+		MIPI_OUTP(ctrl->phy_io.base + DSIPHY_CMN_CTRL_0, ~0x1F);
 	else
 		MIPI_OUTP(ctrl->phy_io.base + MDSS_DSI_DSIPHY_CTRL_0, 0x000);