From fd9d991551a2530be7e4718fac1f0c8a310d210d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Emilio=20L=C3=B3pez?= Date: Tue, 26 Mar 2013 23:39:18 -0300 Subject: [PATCH 01/11] arm: sunxi: rename clock compatible strings MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit During the introduction of the Allwinner SoC platforms, sunxi was initially meant as a generic name for all the variants of the Allwinner SoC. It was ok at the time of the support of only the A10 and A13 that look pretty much the same; but it's beginning to be troublesome with the future addition of the Allwinner A31 (sun6i) that is quite different, and would introduce some weird logic, where sunxi would actually mean in some case sun4i and sun5i but without sun6i... Moreover, it makes the compatible strings naming scheme not consistent with other architectures, where usually for this kind of compability, we just use the oldest SoC name that has this IP, so let's do just this. Signed-off-by: Emilio López Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sunxi.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/sunxi.dtsi b/arch/arm/boot/dts/sunxi.dtsi index acf7777cf61f..dfbb98bbc4c2 100644 --- a/arch/arm/boot/dts/sunxi.dtsi +++ b/arch/arm/boot/dts/sunxi.dtsi @@ -47,7 +47,7 @@ osc24M: osc24M@01c20050 { #clock-cells = <0>; - compatible = "allwinner,sunxi-osc-clk"; + compatible = "allwinner,sun4i-osc-clk"; reg = <0x01c20050 0x4>; clocks = <&osc24M_fixed>; }; @@ -60,7 +60,7 @@ pll1: pll1@01c20000 { #clock-cells = <0>; - compatible = "allwinner,sunxi-pll1-clk"; + compatible = "allwinner,sun4i-pll1-clk"; reg = <0x01c20000 0x4>; clocks = <&osc24M>; }; @@ -68,28 +68,28 @@ /* dummy is 200M */ cpu: cpu@01c20054 { #clock-cells = <0>; - compatible = "allwinner,sunxi-cpu-clk"; + compatible = "allwinner,sun4i-cpu-clk"; reg = <0x01c20054 0x4>; clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; }; axi: axi@01c20054 { #clock-cells = <0>; - compatible = "allwinner,sunxi-axi-clk"; + compatible = "allwinner,sun4i-axi-clk"; reg = <0x01c20054 0x4>; clocks = <&cpu>; }; ahb: ahb@01c20054 { #clock-cells = <0>; - compatible = "allwinner,sunxi-ahb-clk"; + compatible = "allwinner,sun4i-ahb-clk"; reg = <0x01c20054 0x4>; clocks = <&axi>; }; apb0: apb0@01c20054 { #clock-cells = <0>; - compatible = "allwinner,sunxi-apb0-clk"; + compatible = "allwinner,sun4i-apb0-clk"; reg = <0x01c20054 0x4>; clocks = <&ahb>; }; @@ -97,14 +97,14 @@ /* dummy is pll62 */ apb1_mux: apb1_mux@01c20058 { #clock-cells = <0>; - compatible = "allwinner,sunxi-apb1-mux-clk"; + compatible = "allwinner,sun4i-apb1-mux-clk"; reg = <0x01c20058 0x4>; clocks = <&osc24M>, <&dummy>, <&osc32k>; }; apb1: apb1@01c20058 { #clock-cells = <0>; - compatible = "allwinner,sunxi-apb1-clk"; + compatible = "allwinner,sun4i-apb1-clk"; reg = <0x01c20058 0x4>; clocks = <&apb1_mux>; }; From 4498578623148a27bb9683359fcd09746e109dfa Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 20 Feb 2013 17:41:33 -0800 Subject: [PATCH 02/11] ARM: sunxi: dt: Use clocks property instead of clock-frequency for the UARTs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It will be especially useful when we will have the clock definitions in the device tree. Signed-off-by: Maxime Ripard Acked-by: Emilio López Tested-by: Emilio López --- arch/arm/boot/dts/sunxi.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/sunxi.dtsi b/arch/arm/boot/dts/sunxi.dtsi index dfbb98bbc4c2..287deb79e515 100644 --- a/arch/arm/boot/dts/sunxi.dtsi +++ b/arch/arm/boot/dts/sunxi.dtsi @@ -142,7 +142,7 @@ interrupts = <1>; reg-shift = <2>; reg-io-width = <4>; - clock-frequency = <24000000>; + clocks = <&osc>; status = "disabled"; }; @@ -152,7 +152,7 @@ interrupts = <2>; reg-shift = <2>; reg-io-width = <4>; - clock-frequency = <24000000>; + clocks = <&osc>; status = "disabled"; }; }; From b00adbe07181a4ae265e8d757b3ad5e0a56e194c Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Mon, 18 Mar 2013 10:54:49 +0100 Subject: [PATCH 03/11] ARM: sunxi: Rename uart nodes to serial The other architecture use serial@address for their uart nodes, so rename our uart dt nodes to be consistent Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 4 ++-- arch/arm/boot/dts/sun4i-a10-hackberry.dts | 2 +- arch/arm/boot/dts/sun5i-a13-olinuxino.dts | 2 +- arch/arm/boot/dts/sunxi.dtsi | 4 ++-- 4 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts index 88e2dc13fd4d..cd06a3ca2196 100644 --- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts +++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts @@ -36,11 +36,11 @@ }; }; - uart0: uart@01c28000 { + uart0: serial@01c28000 { status = "okay"; }; - uart1: uart@01c28400 { + uart1: serial@01c28400 { status = "okay"; }; }; diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts b/arch/arm/boot/dts/sun4i-a10-hackberry.dts index f84549ad791e..9ab6875600bd 100644 --- a/arch/arm/boot/dts/sun4i-a10-hackberry.dts +++ b/arch/arm/boot/dts/sun4i-a10-hackberry.dts @@ -23,7 +23,7 @@ }; soc { - uart0: uart@01c28000 { + uart0: serial@01c28000 { status = "okay"; }; }; diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts index 33d1c7e71f25..f1579a831f90 100644 --- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts +++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts @@ -32,7 +32,7 @@ }; }; - uart1: uart@01c28400 { + uart1: serial@01c28400 { pinctrl-names = "default"; pinctrl-0 = <&uart1_pins_b>; status = "okay"; diff --git a/arch/arm/boot/dts/sunxi.dtsi b/arch/arm/boot/dts/sunxi.dtsi index 287deb79e515..5b1893fb7eb2 100644 --- a/arch/arm/boot/dts/sunxi.dtsi +++ b/arch/arm/boot/dts/sunxi.dtsi @@ -136,7 +136,7 @@ #interrupt-cells = <1>; }; - uart0: uart@01c28000 { + uart0: serial@01c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; interrupts = <1>; @@ -146,7 +146,7 @@ status = "disabled"; }; - uart1: uart@01c28400 { + uart1: serial@01c28400 { compatible = "snps,dw-apb-uart"; reg = <0x01c28400 0x400>; interrupts = <2>; From 89b3c99fd9e7a95c8920f16092e639269fe48378 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 20 Feb 2013 17:25:03 -0800 Subject: [PATCH 04/11] ARM: sunxi: dt: Move uart0 to sun4i-a10.dtsi MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The UART0 is only available on the Allwinner A10 SoCs, and not on the A13, so move the uart0 node to sun4i-a10.dtsi. Signed-off-by: Maxime Ripard Acked-by: Emilio López Tested-by: Emilio López --- arch/arm/boot/dts/sun4i-a10.dtsi | 10 ++++++++++ arch/arm/boot/dts/sunxi.dtsi | 10 ---------- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index 03d2b532a077..b605672424ac 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -47,5 +47,15 @@ allwinner,pull = <0>; }; }; + + uart0: serial@01c28000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28000 0x400>; + interrupts = <1>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&osc>; + status = "disabled"; + }; }; }; diff --git a/arch/arm/boot/dts/sunxi.dtsi b/arch/arm/boot/dts/sunxi.dtsi index 5b1893fb7eb2..eb6f77025b73 100644 --- a/arch/arm/boot/dts/sunxi.dtsi +++ b/arch/arm/boot/dts/sunxi.dtsi @@ -136,16 +136,6 @@ #interrupt-cells = <1>; }; - uart0: serial@01c28000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28000 0x400>; - interrupts = <1>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&osc>; - status = "disabled"; - }; - uart1: serial@01c28400 { compatible = "snps,dw-apb-uart"; reg = <0x01c28400 0x400>; From c08f4252a66bd89751bbba4c6fdfb181dc269486 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 20 Feb 2013 17:27:50 -0800 Subject: [PATCH 05/11] ARM: sunxi: dt: Add uart3 dt node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Both A10 and A13 Allwinner SoCs have a Synopsys APB uart3 device available, so add it to the sunxi.dtsi file Signed-off-by: Maxime Ripard Acked-by: Emilio López --- arch/arm/boot/dts/sunxi.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/sunxi.dtsi b/arch/arm/boot/dts/sunxi.dtsi index eb6f77025b73..40392dee9d7e 100644 --- a/arch/arm/boot/dts/sunxi.dtsi +++ b/arch/arm/boot/dts/sunxi.dtsi @@ -145,5 +145,15 @@ clocks = <&osc>; status = "disabled"; }; + + uart3: serial@01c28c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28c00 0x400>; + interrupts = <4>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&osc>; + status = "disabled"; + }; }; }; From 76f14d0a70a664d15243b065d1926a54677b3449 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 20 Feb 2013 17:38:27 -0800 Subject: [PATCH 06/11] ARM: sunxi: dt: Add A10 UARTs to the dtsi. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Allwinner A10 SoC has 8 available UARTs, which is 6 more than on the A13, so add the missing UARTs to the sun4i-a10 dtsi. Signed-off-by: Maxime Ripard Acked-by: Emilio López --- arch/arm/boot/dts/sun4i-a10.dtsi | 50 ++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index b605672424ac..68a27fc4491f 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -57,5 +57,55 @@ clocks = <&osc>; status = "disabled"; }; + + uart2: serial@01c28800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28800 0x400>; + interrupts = <3>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&osc>; + status = "disabled"; + }; + + uart4: serial@01c29000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c29000 0x400>; + interrupts = <17>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&osc>; + status = "disabled"; + }; + + uart5: serial@01c29400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c29400 0x400>; + interrupts = <18>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&osc>; + status = "disabled"; + }; + + uart6: serial@01c29800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c29800 0x400>; + interrupts = <19>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&osc>; + status = "disabled"; + }; + + uart7: serial@01c29c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c29c00 0x400>; + interrupts = <20>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&osc>; + status = "disabled"; + }; }; }; From 0dfd1dfc96dee8ac1aacfc836de11ec52300218d Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Tue, 5 Mar 2013 22:18:03 +0100 Subject: [PATCH 07/11] ARM: sunxi: hackberry: Add UART muxing MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We previously relied on the bootloader to do the muxing of the UART for the Hackberry. Don't rely on it anymore and use pinctrl. Signed-off-by: Maxime Ripard Acked-by: Emilio López --- arch/arm/boot/dts/sun4i-a10-hackberry.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts b/arch/arm/boot/dts/sun4i-a10-hackberry.dts index 9ab6875600bd..20460007a89f 100644 --- a/arch/arm/boot/dts/sun4i-a10-hackberry.dts +++ b/arch/arm/boot/dts/sun4i-a10-hackberry.dts @@ -24,6 +24,8 @@ soc { uart0: serial@01c28000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; status = "okay"; }; }; From 23b5cf31fe5fd1f787f0101ede4ab4fb43e12371 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Emilio=20L=C3=B3pez?= Date: Fri, 8 Mar 2013 08:18:56 -0300 Subject: [PATCH 08/11] ARM: sunxi: cubieboard: Add UART muxing MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We previously relied on the bootloader to do the muxing of the UART for the Cubieboard. Don't rely on it anymore and use pinctrl. Also remove uart1, as it is not enabled by default and it's not exposed on the board headers. Signed-off-by: Emilio López Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts index cd06a3ca2196..99558f624554 100644 --- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts +++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts @@ -37,10 +37,8 @@ }; uart0: serial@01c28000 { - status = "okay"; - }; - - uart1: serial@01c28400 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; status = "okay"; }; }; From 07c60ef775568d2190f93786c464e30696c10b95 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Emilio=20L=C3=B3pez?= Date: Wed, 27 Mar 2013 18:20:38 -0300 Subject: [PATCH 09/11] arm: sunxi: Add clock definitions for AXI, AHB, APB0, APB1 gates MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit adds the corresponding DT bindings for all the AXI, AHB, APB0 and APB1 gates. Signed-off-by: Emilio López Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sunxi.dtsi | 49 ++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/arch/arm/boot/dts/sunxi.dtsi b/arch/arm/boot/dts/sunxi.dtsi index 40392dee9d7e..87b2cce11b1f 100644 --- a/arch/arm/boot/dts/sunxi.dtsi +++ b/arch/arm/boot/dts/sunxi.dtsi @@ -80,6 +80,14 @@ clocks = <&cpu>; }; + axi_gates: axi_gates@01c2005c { + #clock-cells = <1>; + compatible = "allwinner,sun4i-axi-gates-clk"; + reg = <0x01c2005c 0x4>; + clocks = <&axi>; + clock-output-names = "axi_dram"; + }; + ahb: ahb@01c20054 { #clock-cells = <0>; compatible = "allwinner,sun4i-ahb-clk"; @@ -87,6 +95,24 @@ clocks = <&axi>; }; + ahb_gates: ahb_gates@01c20060 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-ahb-gates-clk"; + reg = <0x01c20060 0x8>; + clocks = <&ahb>; + clock-output-names = "ahb_usb0", "ahb_ehci0", + "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss", + "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1", + "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand", + "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts", + "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3", + "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve", + "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0", + "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi", + "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0", + "ahb_de_fe1", "ahb_mp", "ahb_mali400"; + }; + apb0: apb0@01c20054 { #clock-cells = <0>; compatible = "allwinner,sun4i-apb0-clk"; @@ -94,6 +120,16 @@ clocks = <&ahb>; }; + apb0_gates: apb0_gates@01c20068 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-apb0-gates-clk"; + reg = <0x01c20068 0x4>; + clocks = <&apb0>; + clock-output-names = "apb0_codec", "apb0_spdif", + "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0", + "apb0_ir1", "apb0_keypad"; + }; + /* dummy is pll62 */ apb1_mux: apb1_mux@01c20058 { #clock-cells = <0>; @@ -108,6 +144,19 @@ reg = <0x01c20058 0x4>; clocks = <&apb1_mux>; }; + + apb1_gates: apb1_gates@01c2006c { + #clock-cells = <1>; + compatible = "allwinner,sun4i-apb1-gates-clk"; + reg = <0x01c2006c 0x4>; + clocks = <&apb1>; + clock-output-names = "apb1_i2c0", "apb1_i2c1", + "apb1_i2c2", "apb1_can", "apb1_scr", + "apb1_ps20", "apb1_ps21", "apb1_uart0", + "apb1_uart1", "apb1_uart2", "apb1_uart3", + "apb1_uart4", "apb1_uart5", "apb1_uart6", + "apb1_uart7"; + }; }; soc { From 9ff49ec75ee2b8d4dc2b92d24d5587a5b731f0e3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Emilio=20L=C3=B3pez?= Date: Wed, 27 Mar 2013 18:20:39 -0300 Subject: [PATCH 10/11] arm: sunxi: use the right clock phandles for UARTs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All the UARTs are connected to clock gates; now that our clock driver is able to handle them, make the switch. Signed-off-by: Emilio López Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10.dtsi | 12 ++++++------ arch/arm/boot/dts/sunxi.dtsi | 4 ++-- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index 68a27fc4491f..6b3a6b25f1f8 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -54,7 +54,7 @@ interrupts = <1>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&osc>; + clocks = <&apb1_gates 16>; status = "disabled"; }; @@ -64,7 +64,7 @@ interrupts = <3>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&osc>; + clocks = <&apb1_gates 18>; status = "disabled"; }; @@ -74,7 +74,7 @@ interrupts = <17>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&osc>; + clocks = <&apb1_gates 20>; status = "disabled"; }; @@ -84,7 +84,7 @@ interrupts = <18>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&osc>; + clocks = <&apb1_gates 21>; status = "disabled"; }; @@ -94,7 +94,7 @@ interrupts = <19>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&osc>; + clocks = <&apb1_gates 22>; status = "disabled"; }; @@ -104,7 +104,7 @@ interrupts = <20>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&osc>; + clocks = <&apb1_gates 23>; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/sunxi.dtsi b/arch/arm/boot/dts/sunxi.dtsi index 87b2cce11b1f..a8d47e200f87 100644 --- a/arch/arm/boot/dts/sunxi.dtsi +++ b/arch/arm/boot/dts/sunxi.dtsi @@ -191,7 +191,7 @@ interrupts = <2>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&osc>; + clocks = <&apb1_gates 17>; status = "disabled"; }; @@ -201,7 +201,7 @@ interrupts = <4>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&osc>; + clocks = <&apb1_gates 19>; status = "disabled"; }; }; From 36386d6e54d0ebcd5b2e0869f837800293d94c3c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Emilio=20L=C3=B3pez?= Date: Wed, 27 Mar 2013 18:20:41 -0300 Subject: [PATCH 11/11] arm: sunxi: Add clock to pinctrl node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The port controller needs the apb0_pio clock enabled to be able to work. This commit declares that on the device tree. Signed-off-by: Emilio López Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10.dtsi | 1 + arch/arm/boot/dts/sun5i-a13.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index 6b3a6b25f1f8..f6405204e7e2 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -21,6 +21,7 @@ pio: pinctrl@01c20800 { compatible = "allwinner,sun4i-a10-pinctrl"; reg = <0x01c20800 0x400>; + clocks = <&apb0_gates 5>; gpio-controller; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi index 945bfacb0561..10ee8eedd36b 100644 --- a/arch/arm/boot/dts/sun5i-a13.dtsi +++ b/arch/arm/boot/dts/sun5i-a13.dtsi @@ -22,6 +22,7 @@ pio: pinctrl@01c20800 { compatible = "allwinner,sun5i-a13-pinctrl"; reg = <0x01c20800 0x400>; + clocks = <&apb0_gates 5>; gpio-controller; #address-cells = <1>; #size-cells = <0>;