ARM: dts: msm: add mdss node for msmfalcon target
Add mdss node for msmfalcon target which is used by display driver. Change-Id: I49efddea0228e3129d36eabc102d6df0fcd53d12 Signed-off-by: Raviteja Tamatam <travitej@codeaurora.org> Signed-off-by: Sandeep Panda <spanda@codeaurora.org> Signed-off-by: Vishnuvardhan Prodduturi <vproddut@codeaurora.org>
This commit is contained in:
Raviteja Tamatam
Vishnuvardhan Prodduturi
parent
f9bf3dd7e9
commit
b2dcc0a3b1
7 changed files with 892 additions and 0 deletions
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@ -42,6 +42,52 @@
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status = "ok";
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};
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&mdss_mdp {
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qcom,mdss-pref-prim-intf = "dsi";
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};
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&mdss_dsi {
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hw-config = "split_dsi";
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};
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&mdss_dsi0 {
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qcom,dsi-pref-prim-pan = <&dsi_dual_nt35597_truly_video>;
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pinctrl-names = "mdss_default", "mdss_sleep";
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pinctrl-0 = <&mdss_dsi_active &mdss_te_active>;
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pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>;
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qcom,platform-reset-gpio = <&tlmm 53 0>;
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qcom,platform-te-gpio = <&tlmm 59 0>;
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};
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&mdss_dsi1 {
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qcom,dsi-pref-prim-pan = <&dsi_dual_nt35597_truly_video>;
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pinctrl-names = "mdss_default", "mdss_sleep";
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pinctrl-0 = <&mdss_dsi_active &mdss_te_active>;
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pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>;
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qcom,platform-reset-gpio = <&tlmm 53 0>;
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qcom,platform-te-gpio = <&tlmm 59 0>;
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};
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&pm2falcon_wled {
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qcom,led-strings-list = [01 02];
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};
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&dsi_dual_nt35597_truly_video {
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
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qcom,mdss-dsi-bl-min-level = <1>;
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qcom,mdss-dsi-bl-max-level = <4095>;
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qcom,mdss-dsi-mode-sel-gpio-state = "dual_port";
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qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
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};
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&dsi_dual_nt35597_truly_cmd {
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
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qcom,mdss-dsi-bl-min-level = <1>;
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qcom,mdss-dsi-bl-max-level = <4095>;
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qcom,mdss-dsi-mode-sel-gpio-state = "dual_port";
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qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
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};
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&soc {
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qcom,msm-ssc-sensors {
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compatible = "qcom,msm-ssc-sensors";
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83
arch/arm/boot/dts/qcom/msmfalcon-mdss-panels.dtsi
Normal file
83
arch/arm/boot/dts/qcom/msmfalcon-mdss-panels.dtsi
Normal file
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@ -0,0 +1,83 @@
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/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "dsi-panel-sim-video.dtsi"
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#include "dsi-panel-sim-dualmipi-video.dtsi"
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#include "dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi"
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#include "dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi"
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&soc {
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dsi_panel_pwr_supply: dsi_panel_pwr_supply {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,panel-supply-entry@0 {
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reg = <0>;
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qcom,supply-name = "wqhd-vddio";
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qcom,supply-min-voltage = <1880000>;
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qcom,supply-max-voltage = <1950000>;
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qcom,supply-enable-load = <32000>;
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qcom,supply-disable-load = <80>;
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};
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qcom,panel-supply-entry@1 {
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reg = <1>;
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qcom,supply-name = "lab";
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qcom,supply-min-voltage = <4600000>;
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qcom,supply-max-voltage = <6000000>;
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qcom,supply-enable-load = <100000>;
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qcom,supply-disable-load = <100>;
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};
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qcom,panel-supply-entry@2 {
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reg = <2>;
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qcom,supply-name = "ibb";
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qcom,supply-min-voltage = <4600000>;
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qcom,supply-max-voltage = <6000000>;
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qcom,supply-enable-load = <100000>;
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qcom,supply-disable-load = <100>;
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qcom,supply-post-on-sleep = <10>;
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};
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};
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};
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&soc {
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dsi_panel_pwr_supply_no_labibb: dsi_panel_pwr_supply_no_labibb {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,panel-supply-entry@0 {
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reg = <0>;
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qcom,supply-name = "wqhd-vddio";
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qcom,supply-min-voltage = <1880000>;
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qcom,supply-max-voltage = <1950000>;
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qcom,supply-enable-load = <32000>;
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qcom,supply-disable-load = <80>;
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};
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};
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};
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&dsi_dual_nt35597_truly_video {
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qcom,mdss-dsi-panel-timings-8996 = [23 1e 07 08 05 03 04 a0
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23 1e 07 08 05 03 04 a0
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23 1e 07 08 05 03 04 a0
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23 1e 07 08 05 03 04 a0
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23 18 07 08 04 03 04 a0];
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};
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&dsi_dual_nt35597_truly_cmd {
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qcom,mdss-dsi-panel-timings-8996 = [23 1e 07 08 05 03 04 a0
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23 1e 07 08 05 03 04 a0
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23 1e 07 08 05 03 04 a0
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23 1e 07 08 05 03 04 a0
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23 18 07 08 04 03 04 a0];
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};
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82
arch/arm/boot/dts/qcom/msmfalcon-mdss-pll.dtsi
Normal file
82
arch/arm/boot/dts/qcom/msmfalcon-mdss-pll.dtsi
Normal file
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@ -0,0 +1,82 @@
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/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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&soc {
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mdss_dsi0_pll: qcom,mdss_dsi_pll@c994400 {
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compatible = "qcom,mdss_dsi_pll_msmfalcon";
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status = "ok";
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label = "MDSS DSI 0 PLL";
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cell-index = <0>;
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#clock-cells = <1>;
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reg = <0xc994400 0x588>,
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<0xc8c2300 0x8>;
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reg-names = "pll_base", "gdsc_base";
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gdsc-supply = <&gdsc_mdss>;
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clocks = <&clock_mmss MMSS_MDSS_AHB_CLK>;
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clock-names = "iface_clk";
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clock-rate = <0>;
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qcom,dsi-pll-ssc-en;
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qcom,dsi-pll-ssc-mode = "down-spread";
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qcom,platform-supply-entries {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,platform-supply-entry@0 {
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reg = <0>;
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qcom,supply-name = "gdsc";
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qcom,supply-min-voltage = <0>;
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qcom,supply-max-voltage = <0>;
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qcom,supply-enable-load = <0>;
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qcom,supply-disable-load = <0>;
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};
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};
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};
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mdss_dsi1_pll: qcom,mdss_dsi_pll@c996400 {
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compatible = "qcom,mdss_dsi_pll_msmfalcon";
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status = "ok";
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label = "MDSS DSI 1 PLL";
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cell-index = <1>;
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#clock-cells = <1>;
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reg = <0xc996400 0x588>,
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<0xc8c2300 0x8>;
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reg-names = "pll_base", "gdsc_base";
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gdsc-supply = <&gdsc_mdss>;
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clocks = <&clock_mmss MMSS_MDSS_AHB_CLK>;
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clock-names = "iface_clk";
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clock-rate = <0>;
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qcom,dsi-pll-ssc-en;
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qcom,dsi-pll-ssc-mode = "down-spread";
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qcom,platform-supply-entries {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,platform-supply-entry@0 {
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reg = <0>;
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qcom,supply-name = "gdsc";
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qcom,supply-min-voltage = <0>;
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qcom,supply-max-voltage = <0>;
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qcom,supply-enable-load = <0>;
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qcom,supply-disable-load = <0>;
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};
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};
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};
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};
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579
arch/arm/boot/dts/qcom/msmfalcon-mdss.dtsi
Normal file
579
arch/arm/boot/dts/qcom/msmfalcon-mdss.dtsi
Normal file
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@ -0,0 +1,579 @@
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/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <dt-bindings/clock/mdss-pll-clk.h>
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&soc {
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mdss_mdp: qcom,mdss_mdp@c900000 {
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compatible = "qcom,mdss_mdp";
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status = "ok";
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reg = <0x0c900000 0x90000>,
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<0x0c9b0000 0x1040>;
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reg-names = "mdp_phys", "vbif_phys";
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interrupts = <0 83 0>;
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interrupt-controller;
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#interrupt-cells = <1>;
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vdd-supply = <&gdsc_mdss>;
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/* Bus Scale Settings */
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qcom,msm-bus,name = "mdss_mdp";
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qcom,msm-bus,num-cases = <3>;
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qcom,msm-bus,num-paths = <2>;
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qcom,msm-bus,vectors-KBps =
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<22 512 0 0>, <23 512 0 0>,
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<22 512 0 6400000>, <23 512 0 6400000>,
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<22 512 0 6400000>, <23 512 0 6400000>;
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/* Fudge factors */
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qcom,mdss-ab-factor = <1 1>; /* 1 time */
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qcom,mdss-ib-factor = <1 1>; /* 1 time */
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qcom,mdss-clk-factor = <105 100>; /* 1.05 times */
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qcom,max-mixer-width = <2560>;
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qcom,max-pipe-width = <2560>;
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qcom,max-dest-scaler-input-width = <2048>;
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qcom,max-dest-scaler-output-width = <2560>;
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/* VBIF QoS remapper settings*/
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qcom,mdss-vbif-qos-rt-setting = <1 2 2 2>;
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qcom,vbif-settings = <0x00ac 0x00000040>,
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<0x00d0 0x00001010>; /* v1 only */
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qcom,mdss-has-panic-ctrl;
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qcom,mdss-per-pipe-panic-luts = <0x000f>,
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<0xffff>,
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<0xfffc>,
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<0xff00>;
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qcom,mdss-mdp-reg-offset = <0x00001000>;
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qcom,max-bandwidth-low-kbps = <6600000>;
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qcom,max-bandwidth-high-kbps = <6600000>;
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qcom,max-bandwidth-per-pipe-kbps = <3100000>;
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qcom,max-clk-rate = <412500000>;
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qcom,mdss-default-ot-rd-limit = <32>;
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qcom,mdss-default-ot-wr-limit = <40>;
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qcom,mdss-dram-channels = <2>;
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/* Bandwidth limit settings */
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qcom,max-bw-settings = <1 6600000>, /* Default */
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<2 4500000>; /* Camera */
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qcom,mdss-pipe-vig-off = <0x00005000 0x00007000>;
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qcom,mdss-pipe-dma-off = <0x00025000 0x00027000
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0x00029000>;
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qcom,mdss-pipe-cursor-off = <0x00035000>;
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qcom,mdss-pipe-vig-xin-id = <0 4>;
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qcom,mdss-pipe-dma-xin-id = <1 5 9>;
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qcom,mdss-pipe-cursor-xin-id = <2>;
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/* These Offsets are relative to
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* "mdp_phys + mdp-reg-offset" address
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*/
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qcom,mdss-pipe-vig-clk-ctrl-offsets = <0x2ac 0 0>,
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<0x2b4 0 0>;
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qcom,mdss-pipe-dma-clk-ctrl-offsets = <0x2ac 8 12>,
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<0x2b4 8 12>,
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<0x2c4 8 12>;
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qcom,mdss-pipe-cursor-clk-ctrl-offsets = <0x3a8 16 15>;
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qcom,mdss-ctl-off = <0x00002000 0x00002200 0x00002400
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0x00002600 0x00002800>;
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qcom,mdss-mixer-intf-off = <0x00045000 0x00046000
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0x00047000 0x0004a000>;
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qcom,mdss-dspp-off = <0x00055000 0x00057000>;
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qcom,mdss-wb-off = <0x00066000>;
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qcom,mdss-intf-off = <0x0006b000 0x0006b800
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0x0006c000 0x0006c800>;
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qcom,mdss-pingpong-off = <0x00071000 0x00071800
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0x00072000 0x00072800>;
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qcom,mdss-slave-pingpong-off = <0x00073000>;
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qcom,mdss-ppb-ctl-off = <0x00000330 0x00000338 0x00000370
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0x00000374> ;
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qcom,mdss-ppb-cfg-off = <0x00000334 0x0000033C>;
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qcom,mdss-has-pingpong-split;
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qcom,mdss-has-separate-rotator;
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qcom,mdss-ad-off = <0x0079000 0x00079800>;
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qcom,mdss-cdm-off = <0x0007a200>;
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qcom,mdss-dsc-off = <0x00081000 0x00081400>;
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qcom,mdss-wfd-mode = "intf";
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qcom,mdss-has-source-split;
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qcom,mdss-highest-bank-bit = <0x1>;
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qcom,mdss-has-decimation;
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qcom,mdss-idle-power-collapse-enabled;
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clocks = <&clock_mmss MMSS_MNOC_AHB_CLK>,
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<&clock_mmss MMSS_MDSS_AHB_CLK>,
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<&clock_mmss MMSS_MDSS_AXI_CLK>,
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<&clock_mmss MDP_CLK_SRC>,
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<&clock_mmss MMSS_MDSS_MDP_CLK>,
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<&clock_mmss MMSS_MDSS_VSYNC_CLK>,
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<&clock_mmss MDP_CLK_SRC>;
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clock-names = "mnoc_clk", "iface_clk", "bus_clk",
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"core_clk_src", "core_clk", "vsync_clk",
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"lut_clk";
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qcom,mdp-settings = <0x01190 0x00000000>,
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<0x012ac 0xc0000ccc>,
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<0x012b4 0xc0000ccc>,
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<0x012bc 0x00cccccc>,
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<0x012c4 0x000000cc>,
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<0x013a8 0x0cccc0c0>,
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<0x013b0 0xccccc0c0>,
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<0x013b8 0xcccc0000>,
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<0x013d0 0x00cc0000>,
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<0x0506c 0x00000000>,
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<0x0706c 0x00000000>,
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<0x0906c 0x00000000>,
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<0x0b06c 0x00000000>,
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<0x1506c 0x00000000>,
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<0x1706c 0x00000000>,
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<0x1906c 0x00000000>,
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<0x1b06c 0x00000000>,
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<0x2506c 0x00000000>,
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<0x2706c 0x00000000>;
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qcom,regs-dump-mdp = <0x01000 0x01458>,
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<0x02000 0x02094>,
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<0x02200 0x02294>,
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<0x02400 0x02494>,
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<0x02600 0x02694>,
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<0x02800 0x02894>,
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<0x05000 0x05154>,
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<0x05a00 0x05b00>,
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<0x07000 0x07154>,
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<0x07a00 0x07b00>,
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<0x25000 0x25184>,
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<0x27000 0x27184>,
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<0x29000 0x29184>,
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<0x35000 0x35150>,
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<0x45000 0x452bc>,
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<0x46000 0x462bc>,
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<0x47000 0x472bc>,
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<0x4a000 0x4a2bc>,
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<0x55000 0x5522c>,
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<0x57000 0x5722c>,
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<0x66000 0x662c0>,
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<0x6b000 0x6b268>,
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<0x6b800 0x6ba68>,
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<0x6c000 0x6c268>,
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<0x71000 0x710d4>,
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<0x71800 0x718d4>,
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||||
<0x73000 0x730d4>,
|
||||
<0x81000 0x81140>,
|
||||
<0x81400 0x81540>;
|
||||
|
||||
qcom,regs-dump-names-mdp = "MDP",
|
||||
"CTL_0", "CTL_1", "CTL_2", "CTL_3", "CTL_4",
|
||||
"VIG0_SSPP", "VIG0", "VIG1_SSPP", "VIG1",
|
||||
"DMA0_SSPP", "DMA1_SSPP","DMA2_SSPP",
|
||||
"CURSOR0_SSPP",
|
||||
"LAYER_0", "LAYER_1", "LAYER_2",
|
||||
"LAYER_5",
|
||||
"DSPP_0", "DSPP_1",
|
||||
"WB_2",
|
||||
"INTF_0", "INTF_1", "INTF_2",
|
||||
"PP_0", "PP_1", "PP_4",
|
||||
"DSC_0", "DSC_1";
|
||||
|
||||
/* buffer parameters to calculate prefill bandwidth */
|
||||
qcom,mdss-prefill-outstanding-buffer-bytes = <0>;
|
||||
qcom,mdss-prefill-y-buffer-bytes = <0>;
|
||||
qcom,mdss-prefill-scaler-buffer-lines-bilinear = <2>;
|
||||
qcom,mdss-prefill-scaler-buffer-lines-caf = <4>;
|
||||
qcom,mdss-prefill-post-scaler-buffer-pixels = <2560>;
|
||||
qcom,mdss-prefill-pingpong-buffer-pixels = <5120>;
|
||||
|
||||
qcom,mdss-pp-offsets {
|
||||
qcom,mdss-sspp-mdss-igc-lut-off = <0x2000>;
|
||||
qcom,mdss-sspp-vig-pcc-off = <0x1b00>;
|
||||
qcom,mdss-sspp-rgb-pcc-off = <0x380>;
|
||||
qcom,mdss-sspp-dma-pcc-off = <0x380>;
|
||||
qcom,mdss-lm-pgc-off = <0x3c0>;
|
||||
qcom,mdss-dspp-gamut-off = <0x1600>;
|
||||
qcom,mdss-dspp-pcc-off = <0x1700>;
|
||||
qcom,mdss-dspp-pgc-off = <0x17c0>;
|
||||
};
|
||||
|
||||
qcom,mdss-scaler-offsets {
|
||||
qcom,mdss-vig-scaler-off = <0xa00>;
|
||||
qcom,mdss-vig-scaler-lut-off = <0xb00>;
|
||||
qcom,mdss-has-dest-scaler;
|
||||
qcom,mdss-dest-block-off = <0x00061000>;
|
||||
qcom,mdss-dest-scaler-off = <0x800 0x1000>;
|
||||
qcom,mdss-dest-scaler-lut-off = <0x900 0x1100>;
|
||||
};
|
||||
|
||||
smmu_mdp_unsec: qcom,smmu_mdp_unsec_cb {
|
||||
compatible = "qcom,smmu_mdp_unsec";
|
||||
iommus = <&mmss_bimc_smmu 0>;
|
||||
gdsc-mmagic-mdss-supply = <&gdsc_bimc_smmu>;
|
||||
clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>,
|
||||
<&clock_mmss MMSS_MNOC_AHB_CLK>,
|
||||
<&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>,
|
||||
<&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>;
|
||||
clock-names = "mmss_noc_axi_clk",
|
||||
"mmss_noc_ahb_clk",
|
||||
"mmss_smmu_ahb_clk",
|
||||
"mmss_smmu_axi_clk";
|
||||
};
|
||||
|
||||
smmu_mdp_sec: qcom,smmu_mdp_sec_cb {
|
||||
compatible = "qcom,smmu_mdp_sec";
|
||||
iommus = <&mmss_bimc_smmu 1>;
|
||||
gdsc-mmagic-mdss-supply = <&gdsc_bimc_smmu>;
|
||||
clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>,
|
||||
<&clock_mmss MMSS_MNOC_AHB_CLK>,
|
||||
<&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>,
|
||||
<&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>;
|
||||
clock-names = "mmss_noc_axi_clk",
|
||||
"mmss_noc_ahb_clk",
|
||||
"mmss_smmu_ahb_clk",
|
||||
"mmss_smmu_axi_clk";
|
||||
};
|
||||
|
||||
mdss_fb0: qcom,mdss_fb_primary {
|
||||
cell-index = <0>;
|
||||
compatible = "qcom,mdss-fb";
|
||||
};
|
||||
|
||||
mdss_fb1: qcom,mdss_fb_wfd {
|
||||
cell-index = <1>;
|
||||
compatible = "qcom,mdss-fb";
|
||||
};
|
||||
|
||||
mdss_fb2: qcom,mdss_fb_dp {
|
||||
cell-index = <2>;
|
||||
compatible = "qcom,mdss-fb";
|
||||
qcom,mdss-intf = <&mdss_dp_ctrl>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
mdss_dsi: qcom,mdss_dsi@0 {
|
||||
compatible = "qcom,mdss-dsi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
gdsc-supply = <&gdsc_mdss>;
|
||||
vdda-1p2-supply = <&pmfalcon_l1>;
|
||||
vdda-0p9-supply = <&pm2falcon_l1>;
|
||||
ranges = <0xc994000 0xc994000 0x400
|
||||
0xc994400 0xc994400 0x588
|
||||
0xc828000 0xc828000 0xac
|
||||
0xc996000 0xc996000 0x400
|
||||
0xc996400 0xc996400 0x588
|
||||
0xc828000 0xc828000 0xac>;
|
||||
|
||||
/* Bus Scale Settings */
|
||||
qcom,msm-bus,name = "mdss_dsi";
|
||||
qcom,msm-bus,num-cases = <2>;
|
||||
qcom,msm-bus,num-paths = <1>;
|
||||
qcom,msm-bus,vectors-KBps =
|
||||
<22 512 0 0>,
|
||||
<22 512 0 1000>;
|
||||
|
||||
qcom,mmss-ulp-clamp-ctrl-offset = <0x14>;
|
||||
|
||||
clocks = <&clock_mmss MMSS_MDSS_MDP_CLK>,
|
||||
<&clock_mmss MMSS_MNOC_AHB_CLK>,
|
||||
<&clock_mmss MMSS_MDSS_AHB_CLK>,
|
||||
<&clock_mmss MMSS_MDSS_AXI_CLK>,
|
||||
<&clock_mmss MMSS_MISC_AHB_CLK>,
|
||||
<&mdss_dsi0_pll BYTE0_MUX_CLK>,
|
||||
<&mdss_dsi1_pll BYTE1_MUX_CLK>,
|
||||
<&mdss_dsi0_pll PIX0_MUX_CLK>,
|
||||
<&mdss_dsi1_pll PIX1_MUX_CLK>;
|
||||
clock-names = "mdp_core_clk",
|
||||
"mnoc_clk", "iface_clk",
|
||||
"bus_clk", "core_mmss_clk",
|
||||
"ext_byte0_clk", "ext_byte1_clk",
|
||||
"ext_pixel0_clk", "ext_pixel1_clk";
|
||||
|
||||
qcom,core-supply-entries {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,core-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "gdsc";
|
||||
qcom,supply-min-voltage = <0>;
|
||||
qcom,supply-max-voltage = <0>;
|
||||
qcom,supply-enable-load = <0>;
|
||||
qcom,supply-disable-load = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,ctrl-supply-entries {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,ctrl-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "vdda-1p2";
|
||||
qcom,supply-min-voltage = <1200000>;
|
||||
qcom,supply-max-voltage = <1250000>;
|
||||
qcom,supply-enable-load = <12560>;
|
||||
qcom,supply-disable-load = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,phy-supply-entries {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,phy-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "vdda-0p9";
|
||||
qcom,supply-min-voltage = <880000>;
|
||||
qcom,supply-max-voltage = <925000>;
|
||||
qcom,supply-enable-load = <73400>;
|
||||
qcom,supply-disable-load = <32>;
|
||||
};
|
||||
};
|
||||
|
||||
mdss_dsi0: qcom,mdss_dsi_ctrl0@c994000 {
|
||||
compatible = "qcom,mdss-dsi-ctrl";
|
||||
label = "MDSS DSI CTRL->0";
|
||||
cell-index = <0>;
|
||||
reg = <0xc994000 0x400>,
|
||||
<0xc994400 0x588>,
|
||||
<0xc828000 0xac>;
|
||||
reg-names = "dsi_ctrl", "dsi_phy", "mmss_misc_phys";
|
||||
|
||||
qcom,timing-db-mode;
|
||||
wqhd-vddio-supply = <&pmfalcon_l11>;
|
||||
lab-supply = <&lcdb_ldo_vreg>;
|
||||
ibb-supply = <&lcdb_ncp_vreg>;
|
||||
qcom,mdss-mdp = <&mdss_mdp>;
|
||||
qcom,mdss-fb-map = <&mdss_fb0>;
|
||||
|
||||
clocks = <&clock_mmss MMSS_MDSS_BYTE0_CLK>,
|
||||
<&clock_mmss MMSS_MDSS_PCLK0_CLK>,
|
||||
<&clock_mmss MMSS_MDSS_ESC0_CLK>,
|
||||
<&clock_mmss BYTE0_CLK_SRC>,
|
||||
<&clock_mmss PCLK0_CLK_SRC>,
|
||||
<&clock_mmss MMSS_MDSS_BYTE0_INTF_CLK>;
|
||||
clock-names = "byte_clk", "pixel_clk", "core_clk",
|
||||
"byte_clk_rcg", "pixel_clk_rcg",
|
||||
"byte_intf_clk";
|
||||
|
||||
qcom,platform-strength-ctrl = [ff 06
|
||||
ff 06
|
||||
ff 06
|
||||
ff 06
|
||||
ff 00];
|
||||
qcom,platform-regulator-settings = [1d
|
||||
1d 1d 1d 1d];
|
||||
qcom,platform-lane-config = [00 00 10 0f
|
||||
00 00 10 0f
|
||||
00 00 10 0f
|
||||
00 00 10 0f
|
||||
00 00 10 8f];
|
||||
};
|
||||
|
||||
mdss_dsi1: qcom,mdss_dsi_ctrl1@c996000 {
|
||||
compatible = "qcom,mdss-dsi-ctrl";
|
||||
label = "MDSS DSI CTRL->1";
|
||||
cell-index = <1>;
|
||||
reg = <0xc996000 0x400>,
|
||||
<0xc996400 0x588>,
|
||||
<0xc828000 0xac>;
|
||||
reg-names = "dsi_ctrl", "dsi_phy", "mmss_misc_phys";
|
||||
|
||||
qcom,timing-db-mode;
|
||||
wqhd-vddio-supply = <&pmfalcon_l11>;
|
||||
lab-supply = <&lcdb_ldo_vreg>;
|
||||
ibb-supply = <&lcdb_ncp_vreg>;
|
||||
qcom,mdss-mdp = <&mdss_mdp>;
|
||||
qcom,mdss-fb-map = <&mdss_fb0>;
|
||||
|
||||
clocks = <&clock_mmss MMSS_MDSS_BYTE1_CLK>,
|
||||
<&clock_mmss MMSS_MDSS_PCLK1_CLK>,
|
||||
<&clock_mmss MMSS_MDSS_ESC1_CLK>,
|
||||
<&clock_mmss BYTE1_CLK_SRC>,
|
||||
<&clock_mmss PCLK1_CLK_SRC>,
|
||||
<&clock_mmss MMSS_MDSS_BYTE1_INTF_CLK>;
|
||||
clock-names = "byte_clk", "pixel_clk", "core_clk",
|
||||
"byte_clk_rcg", "pixel_clk_rcg",
|
||||
"byte_intf_clk";
|
||||
|
||||
qcom,platform-strength-ctrl = [ff 06
|
||||
ff 06
|
||||
ff 06
|
||||
ff 06
|
||||
ff 00];
|
||||
qcom,platform-regulator-settings = [1d
|
||||
1d 1d 1d 1d];
|
||||
qcom,platform-lane-config = [00 00 10 0f
|
||||
00 00 10 0f
|
||||
00 00 10 0f
|
||||
00 00 10 0f
|
||||
00 00 10 8f];
|
||||
};
|
||||
};
|
||||
|
||||
qcom,mdss_wb_panel {
|
||||
compatible = "qcom,mdss_wb";
|
||||
qcom,mdss_pan_res = <640 480>;
|
||||
qcom,mdss_pan_bpp = <24>;
|
||||
qcom,mdss-fb-map = <&mdss_fb1>;
|
||||
};
|
||||
|
||||
msm_ext_disp: qcom,msm_ext_disp {
|
||||
status = "disabled";
|
||||
compatible = "qcom,msm-ext-disp";
|
||||
|
||||
ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx {
|
||||
compatible = "qcom,msm-ext-disp-audio-codec-rx";
|
||||
qcom,msm_ext_disp = <&msm_ext_disp>;
|
||||
};
|
||||
};
|
||||
|
||||
mdss_dp_ctrl: qcom,dp_ctrl@c990000 {
|
||||
status = "disabled";
|
||||
cell-index = <0>;
|
||||
compatible = "qcom,mdss-dp";
|
||||
qcom,mdss-fb-map = <&mdss_fb2>;
|
||||
|
||||
gdsc-supply = <&gdsc_mdss>;
|
||||
vdda-1p2-supply = <&pmfalcon_l1>;
|
||||
vdda-0p9-supply = <&pm2falcon_l1>;
|
||||
|
||||
reg = <0xc990000 0xa84>,
|
||||
<0xc011000 0x910>,
|
||||
<0x1fcb200 0x050>,
|
||||
<0xc8c2200 0x1a0>,
|
||||
<0x780000 0x621c>,
|
||||
<0xc9e1000 0x02c>;
|
||||
reg-names = "dp_ctrl", "dp_phy", "tcsr_regs", "dp_mmss_cc",
|
||||
"qfprom_physical","hdcp_physical";
|
||||
|
||||
qcom,msm_ext_disp = <&msm_ext_disp>;
|
||||
|
||||
qcom,core-supply-entries {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,core-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "gdsc";
|
||||
qcom,supply-min-voltage = <0>;
|
||||
qcom,supply-max-voltage = <0>;
|
||||
qcom,supply-enable-load = <0>;
|
||||
qcom,supply-disable-load = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,ctrl-supply-entries {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,ctrl-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "vdda-1p2";
|
||||
qcom,supply-min-voltage = <1200000>;
|
||||
qcom,supply-max-voltage = <1250000>;
|
||||
qcom,supply-enable-load = <12560>;
|
||||
qcom,supply-disable-load = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,phy-supply-entries {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,phy-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "vdda-0p9";
|
||||
qcom,supply-min-voltage = <880000>;
|
||||
qcom,supply-max-voltage = <925000>;
|
||||
qcom,supply-enable-load = <73400>;
|
||||
qcom,supply-disable-load = <32>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdss_rotator: qcom,mdss_rotator {
|
||||
compatible = "qcom,sde_rotator";
|
||||
reg = <0x0c900000 0xab100>,
|
||||
<0x0c9b0000 0x1040>;
|
||||
reg-names = "mdp_phys",
|
||||
"rot_vbif_phys";
|
||||
|
||||
qcom,mdss-rot-mode = <1>;
|
||||
qcom,mdss-highest-bank-bit = <0x2>;
|
||||
|
||||
/* Bus Scale Settings */
|
||||
qcom,msm-bus,name = "mdss_rotator";
|
||||
qcom,msm-bus,num-cases = <3>;
|
||||
qcom,msm-bus,num-paths = <1>;
|
||||
qcom,msm-bus,vectors-KBps =
|
||||
<22 512 0 0>,
|
||||
<22 512 0 6400000>,
|
||||
<22 512 0 6400000>;
|
||||
|
||||
rot-vdd-supply = <&gdsc_mdss>;
|
||||
qcom,supply-names = "rot-vdd";
|
||||
|
||||
clocks = <&clock_mmss MMSS_MNOC_AHB_CLK>,
|
||||
<&clock_mmss MMSS_MDSS_AHB_CLK>,
|
||||
<&clock_mmss ROT_CLK_SRC>,
|
||||
<&clock_mmss MMSS_MDSS_ROT_CLK>,
|
||||
<&clock_mmss MMSS_MDSS_AXI_CLK>;
|
||||
clock-names = "mnoc_clk",
|
||||
"iface_clk", "rot_core_clk",
|
||||
"rot_clk", "axi_clk";
|
||||
|
||||
interrupt-parent = <&mdss_mdp>;
|
||||
interrupts = <2 0>;
|
||||
|
||||
/* VBIF QoS remapper settings*/
|
||||
qcom,mdss-rot-vbif-qos-setting = <1 1 1 1>;
|
||||
|
||||
qcom,mdss-default-ot-rd-limit = <32>;
|
||||
qcom,mdss-default-ot-wr-limit = <40>;
|
||||
|
||||
smmu_rot_unsec: qcom,smmu_rot_unsec_cb {
|
||||
compatible = "qcom,smmu_sde_rot_unsec";
|
||||
iommus = <&mmss_bimc_smmu 0xe00>;
|
||||
gdsc-mdss-supply = <&gdsc_bimc_smmu>;
|
||||
|
||||
clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>,
|
||||
<&clock_mmss MMSS_MNOC_AHB_CLK>,
|
||||
<&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>,
|
||||
<&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>;
|
||||
clock-names = "mmss_noc_axi_clk",
|
||||
"mmss_noc_ahb_clk",
|
||||
"mmss_smmu_ahb_clk",
|
||||
"mmss_smmu_axi_clk";
|
||||
};
|
||||
|
||||
smmu_rot_sec: qcom,smmu_rot_sec_cb {
|
||||
compatible = "qcom,smmu_sde_rot_sec";
|
||||
iommus = <&mmss_bimc_smmu 0xe01>;
|
||||
gdsc-mdss-supply = <&gdsc_bimc_smmu>;
|
||||
|
||||
clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>,
|
||||
<&clock_mmss MMSS_MNOC_AHB_CLK>,
|
||||
<&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>,
|
||||
<&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>;
|
||||
clock-names = "mmss_noc_axi_clk",
|
||||
"mmss_noc_ahb_clk",
|
||||
"mmss_smmu_ahb_clk",
|
||||
"mmss_smmu_axi_clk";
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
#include "msmfalcon-mdss-panels.dtsi"
|
||||
|
|
@ -42,6 +42,52 @@
|
|||
status = "ok";
|
||||
};
|
||||
|
||||
&mdss_mdp {
|
||||
qcom,mdss-pref-prim-intf = "dsi";
|
||||
};
|
||||
|
||||
&mdss_dsi {
|
||||
hw-config = "split_dsi";
|
||||
};
|
||||
|
||||
&mdss_dsi0 {
|
||||
qcom,dsi-pref-prim-pan = <&dsi_dual_nt35597_truly_video>;
|
||||
pinctrl-names = "mdss_default", "mdss_sleep";
|
||||
pinctrl-0 = <&mdss_dsi_active &mdss_te_active>;
|
||||
pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>;
|
||||
qcom,platform-reset-gpio = <&tlmm 53 0>;
|
||||
qcom,platform-te-gpio = <&tlmm 59 0>;
|
||||
};
|
||||
|
||||
&mdss_dsi1 {
|
||||
qcom,dsi-pref-prim-pan = <&dsi_dual_nt35597_truly_video>;
|
||||
pinctrl-names = "mdss_default", "mdss_sleep";
|
||||
pinctrl-0 = <&mdss_dsi_active &mdss_te_active>;
|
||||
pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>;
|
||||
qcom,platform-reset-gpio = <&tlmm 53 0>;
|
||||
qcom,platform-te-gpio = <&tlmm 59 0>;
|
||||
};
|
||||
|
||||
&pm2falcon_wled {
|
||||
qcom,led-strings-list = [01 02];
|
||||
};
|
||||
|
||||
&dsi_dual_nt35597_truly_video {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
|
||||
qcom,mdss-dsi-bl-min-level = <1>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-dsi-mode-sel-gpio-state = "dual_port";
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
};
|
||||
|
||||
&dsi_dual_nt35597_truly_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
|
||||
qcom,mdss-dsi-bl-min-level = <1>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-dsi-mode-sel-gpio-state = "dual_port";
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
};
|
||||
|
||||
&soc {
|
||||
qcom,msm-ssc-sensors {
|
||||
compatible = "qcom,msm-ssc-sensors";
|
||||
|
|
|
|||
|
|
@ -1196,6 +1196,59 @@
|
|||
};
|
||||
};
|
||||
|
||||
pmx_mdss: pmx_mdss {
|
||||
mdss_dsi_active: mdss_dsi_active {
|
||||
mux {
|
||||
pins = "gpio53";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio53";
|
||||
drive-strength = <8>; /* 8 mA */
|
||||
bias-disable = <0>; /* no pull */
|
||||
};
|
||||
};
|
||||
mdss_dsi_suspend: mdss_dsi_suspend {
|
||||
mux {
|
||||
pins = "gpio53";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio53";
|
||||
drive-strength = <2>; /* 2 mA */
|
||||
bias-pull-down; /* pull down */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pmx_mdss_te {
|
||||
mdss_te_active: mdss_te_active {
|
||||
mux {
|
||||
pins = "gpio59";
|
||||
function = "mdp_vsync_p";
|
||||
};
|
||||
config {
|
||||
pins = "gpio59";
|
||||
drive-strength = <2>; /* 8 mA */
|
||||
bias-pull-down; /* pull down*/
|
||||
};
|
||||
};
|
||||
|
||||
mdss_te_suspend: mdss_te_suspend {
|
||||
mux {
|
||||
pins = "gpio59";
|
||||
function = "mdp_vsync_p";
|
||||
};
|
||||
config {
|
||||
pins = "gpio59";
|
||||
drive-strength = <2>; /* 2 mA */
|
||||
bias-pull-down; /* pull down */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ts_mux {
|
||||
ts_active: ts_active {
|
||||
mux {
|
||||
|
|
|
|||
|
|
@ -2047,3 +2047,6 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
#include "msmfalcon-mdss.dtsi"
|
||||
#include "msmfalcon-mdss-pll.dtsi"
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue