From b3c7e19b7430a014e670f1494c6b92a818758095 Mon Sep 17 00:00:00 2001 From: Sandeep Panda Date: Wed, 28 Jun 2017 18:31:35 +0530 Subject: [PATCH] msm: mdss: fix the pixel clock calculation for fb modes In the current implementation, if panel is configured in split mode and supports multiple resolutions, then the pixel clock calculation for the supported modes does not take split mode into consideration. This causes issues when recovery or charger application try to configure display. So fix the same by recalculating the pixel clock with taking care of proper width in case of split mode panel. Change-Id: Ie6b50bcd67d3e283610f8b04ac0a974b3527e552 Signed-off-by: Sandeep Panda --- drivers/video/fbdev/msm/mdss_fb.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/video/fbdev/msm/mdss_fb.c b/drivers/video/fbdev/msm/mdss_fb.c index 31cba148ad28..fa8496714280 100644 --- a/drivers/video/fbdev/msm/mdss_fb.c +++ b/drivers/video/fbdev/msm/mdss_fb.c @@ -1192,11 +1192,24 @@ static int mdss_fb_init_panel_modes(struct msm_fb_data_type *mfd, if (pdata->next) { spt = mdss_panel_get_timing_by_name(pdata->next, modedb[i].name); - if (!IS_ERR_OR_NULL(spt)) + /* for split config, recalculate xres and pixel clock */ + if (!IS_ERR_OR_NULL(spt)) { + unsigned long pclk, h_total, v_total; modedb[i].xres += spt->xres; - else + h_total = modedb[i].xres + + modedb[i].left_margin + + modedb[i].right_margin + + modedb[i].hsync_len; + v_total = modedb[i].yres + + modedb[i].lower_margin + + modedb[i].upper_margin + + modedb[i].vsync_len; + pclk = h_total * v_total * modedb[i].refresh; + modedb[i].pixclock = KHZ2PICOS(pclk / 1000); + } else { pr_debug("no matching split config for %s\n", modedb[i].name); + } /* * if no panel timing found for current, need to