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ARM: dts: msm: Modify csiphy timer clock rate on msmcobalt

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Set csiphy timer clock rate to SVS for normal data rate
operations.

CRs-Fixed: 1043041
Change-Id: Ia6fc2dcfa7b5fd23eb2af5baf0acb9fd161fdd09
Signed-off-by: Viswanadha Raju Thotakura <viswanad@codeaurora.org>
This commit is contained in:
Viswanadha Raju Thotakura 2016-07-27 14:52:58 -07:00
parent f600d8b9ec
commit b43b062f24
1 changed files with 3 additions and 3 deletions
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6
arch/arm/boot/dts/qcom/msmcobalt-camera.dtsi
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@ -48,7 +48,7 @@
"csi_src_clk", "csi_clk", "cphy_csid_clk",
"csiphy_timer_src_clk", "csiphy_timer_clk",
"camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk";
qcom,clock-rates = <0 0 0 0 0 0 256000000 0 0 269333333 0
qcom,clock-rates = <0 0 0 0 0 0 256000000 0 0 200000000 0
0 256000000 0>;
status = "ok";
};
@ -80,7 +80,7 @@
"csi_src_clk", "csi_clk", "cphy_csid_clk",
"csiphy_timer_src_clk", "csiphy_timer_clk",
"camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk";
qcom,clock-rates = <0 0 0 0 0 0 256000000 0 0 269333333 0
qcom,clock-rates = <0 0 0 0 0 0 256000000 0 0 200000000 0
0 256000000 0>;
status = "ok";
};
@ -112,7 +112,7 @@
"csi_src_clk", "csi_clk", "cphy_csid_clk",
"csiphy_timer_src_clk", "csiphy_timer_clk",
"camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk";
qcom,clock-rates = <0 0 0 0 0 0 256000000 0 0 269333333 0
qcom,clock-rates = <0 0 0 0 0 0 256000000 0 0 200000000 0
0 256000000 0>;
status = "ok";
};