Merge "clk: msm: hdmi: correct the precision when calculating HDMI PLL"
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1 changed files with 177 additions and 69 deletions
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@ -21,6 +21,7 @@
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#include <linux/clk/msm-clk.h>
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#include <linux/clk/msm-clock-generic.h>
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#include <dt-bindings/clock/msm-clocks-8998.h>
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#include <linux/math64.h>
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#include "mdss-pll.h"
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#include "mdss-hdmi-pll.h"
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@ -29,6 +30,7 @@
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#define _R(x, y) MDSS_PLL_REG_R(x, y)
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/* PLL REGISTERS */
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#define FREQ_UPDATE (0x008)
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#define BIAS_EN_CLKBUFLR_EN (0x034)
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#define CLK_ENABLE1 (0x038)
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#define SYS_CLK_CTRL (0x03C)
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@ -77,9 +79,12 @@
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#define PHY_CMN_CTRL (0x68)
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#define PHY_STATUS (0xB4)
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#define HDMI_VCO_MAX_FREQ 12000000000
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#define HDMI_VCO_MIN_FREQ 8000000000
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#define HDMI_BIT_CLK_TO_PIX_CLK_RATIO 10
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#define HDMI_MHZ_TO_HZ 1000000
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#define HDMI_HZ_TO_MHZ 1000000
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#define HDMI_KHZ_TO_HZ 1000
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#define HDMI_REF_CLOCK_MHZ 19.2
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#define HDMI_REF_CLOCK_HZ (HDMI_REF_CLOCK_MHZ * 1000000)
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#define HDMI_VCO_MIN_RATE_HZ 25000000
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@ -109,7 +114,7 @@ struct hdmi_8998_reg_cfg {
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u32 core_clk_en;
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u32 coreclk_div_mode0;
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u32 phy_mode;
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u32 vco_freq;
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u64 vco_freq;
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u32 hsclk_divsel;
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u32 vco_ratio;
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u32 ssc_en_center;
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@ -142,17 +147,19 @@ static void hdmi_8998_get_div(struct hdmi_8998_reg_cfg *cfg, unsigned long pclk)
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u32 const band_list[] = {0, 1, 2, 3};
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u32 const sz_ratio = ARRAY_SIZE(ratio_list);
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u32 const sz_band = ARRAY_SIZE(band_list);
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u32 const min_freq = 8000, max_freq = 12000;
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u32 const cmp_cnt = 1024;
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u32 const th_min = 500, th_max = 1000;
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u64 bit_clk = ((u64)pclk) * HDMI_BIT_CLK_TO_PIX_CLK_RATIO;
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u32 half_rate_mode = 0;
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u32 freq_optimal, list_elements;
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u32 list_elements;
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int optimal_index;
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u32 i, j, k;
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u32 freq_list[sz_ratio * sz_band];
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u32 found_hsclk_divsel = 0, found_vco_ratio;
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u32 found_tx_band_sel, found_vco_freq;
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u32 found_tx_band_sel;
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u64 const min_freq = HDMI_VCO_MIN_FREQ, max_freq = HDMI_VCO_MAX_FREQ;
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u64 const bit_clk = ((u64)pclk) * HDMI_BIT_CLK_TO_PIX_CLK_RATIO;
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u64 freq_list[sz_ratio * sz_band];
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u64 found_vco_freq;
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u64 freq_optimal;
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find_optimal_index:
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freq_optimal = max_freq;
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@ -164,7 +171,6 @@ find_optimal_index:
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u64 freq = div_u64(bit_clk, (1 << half_rate_mode));
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freq *= (ratio_list[i] * (1 << band_list[j]));
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do_div(freq, (u64) HDMI_MHZ_TO_HZ);
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freq_list[list_elements++] = freq;
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}
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}
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@ -172,23 +178,23 @@ find_optimal_index:
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for (k = 0; k < ARRAY_SIZE(freq_list); k++) {
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u32 const clks_pll_div = 2, core_clk_div = 5;
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u32 const rng1 = 16, rng2 = 8;
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u32 core_clk, rvar1;
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u32 th1, th2;
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u64 core_clk, rvar1, rem;
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core_clk = (((freq_list[k] /
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ratio_list[k / sz_band]) /
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clks_pll_div) / core_clk_div);
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rvar1 = HDMI_REF_CLOCK_HZ / cmp_cnt;
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rvar1 *= rng1;
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rvar1 /= core_clk;
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rvar1 = HDMI_REF_CLOCK_HZ * rng1 * HDMI_MHZ_TO_HZ;
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rvar1 = div64_u64_rem(rvar1, (cmp_cnt * core_clk), &rem);
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if (rem > ((cmp_cnt * core_clk) >> 1))
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rvar1++;
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th1 = rvar1;
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rvar1 = HDMI_REF_CLOCK_HZ / cmp_cnt;
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rvar1 *= rng2;
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rvar1 /= core_clk;
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rvar1 = HDMI_REF_CLOCK_HZ * rng2 * HDMI_MHZ_TO_HZ;
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rvar1 = div64_u64_rem(rvar1, (cmp_cnt * core_clk), &rem);
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if (rem > ((cmp_cnt * core_clk) >> 1))
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rvar1++;
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th2 = rvar1;
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if (freq_list[k] >= min_freq &&
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@ -257,7 +263,7 @@ find_optimal_index:
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break;
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};
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pr_debug("found_vco_freq=%d\n", found_vco_freq);
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pr_debug("found_vco_freq=%llu\n", found_vco_freq);
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pr_debug("found_hsclk_divsel=%d\n", found_hsclk_divsel);
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pr_debug("found_vco_ratio=%d\n", found_vco_ratio);
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pr_debug("found_tx_band_sel=%d\n", found_tx_band_sel);
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@ -278,9 +284,9 @@ static int hdmi_8998_config_phy(unsigned long rate,
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u64 const mid_freq_bit_clk_threshold = 750000000;
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int rc = 0;
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u64 fdata, tmds_clk;
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u64 pll_div = 4 * HDMI_REF_CLOCK_HZ;
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u32 pll_div = 4 * HDMI_REF_CLOCK_HZ;
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u64 bclk;
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u64 vco_freq_mhz;
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u64 vco_freq;
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u64 hsclk_sel, dec_start, div_frac_start;
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u64 rem;
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u64 cpctrl, rctrl, cctrl;
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@ -302,15 +308,15 @@ static int hdmi_8998_config_phy(unsigned long rate,
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hdmi_8998_get_div(cfg, rate);
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vco_freq_mhz = cfg->vco_freq * (u64) HDMI_HZ_TO_MHZ;
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vco_freq = cfg->vco_freq;
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fdata = cfg->vco_freq;
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do_div(fdata, cfg->vco_ratio);
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hsclk_sel = cfg->hsclk_divsel;
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dec_start = vco_freq_mhz;
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dec_start = vco_freq;
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do_div(dec_start, pll_div);
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div_frac_start = vco_freq_mhz * (1 << 20);
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div_frac_start = vco_freq * (1 << 20);
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rem = do_div(div_frac_start, pll_div);
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div_frac_start -= (dec_start * (1 << 20));
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if (rem > (pll_div >> 1))
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@ -330,19 +336,19 @@ static int hdmi_8998_config_phy(unsigned long rate,
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integloop_gain = ((div_frac_start != 0) ||
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(gen_ssc == true)) ? 0x3F : 0xC4;
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integloop_gain <<= digclk_divsel;
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integloop_gain <<= (digclk_divsel == 2 ? 1 : 0);
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integloop_gain = (integloop_gain <= 2046 ? integloop_gain : 0x7FE);
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cmp_rng = gen_ssc ? 0x40 : 0x10;
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pll_cmp = cmp_cnt * fdata;
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rem = do_div(pll_cmp, (u64)(HDMI_REF_CLOCK_MHZ * 10));
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if (rem > ((u64)(HDMI_REF_CLOCK_MHZ * 10) >> 1))
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rem = do_div(pll_cmp, (u32)(HDMI_REF_CLOCK_HZ * 10));
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if (rem > ((u64)(HDMI_REF_CLOCK_HZ * 10) >> 1))
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pll_cmp++;
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pll_cmp = pll_cmp - 1;
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pr_debug("VCO_FREQ = %u\n", cfg->vco_freq);
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pr_debug("VCO_FREQ = %llu\n", cfg->vco_freq);
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pr_debug("FDATA = %llu\n", fdata);
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pr_debug("DEC_START = %llu\n", dec_start);
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pr_debug("DIV_FRAC_START = %llu\n", div_frac_start);
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@ -609,49 +615,6 @@ static int hdmi_8998_phy_ready_status(struct mdss_pll_resources *io)
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return rc;
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}
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static int hdmi_8998_vco_set_rate(struct clk *c, unsigned long rate)
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{
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int rc = 0;
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struct hdmi_pll_vco_clk *vco = to_hdmi_vco_clk(c);
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struct mdss_pll_resources *io = vco->priv;
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rc = mdss_pll_resource_enable(io, true);
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if (rc) {
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pr_err("pll resource enable failed, rc=%d\n", rc);
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return rc;
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}
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if (io->pll_on)
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goto error;
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rc = hdmi_8998_pll_set_clk_rate(c, rate);
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if (rc) {
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pr_err("failed to set clk rate, rc=%d\n", rc);
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goto error;
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}
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vco->rate = rate;
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vco->rate_set = true;
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error:
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(void)mdss_pll_resource_enable(io, false);
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return rc;
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}
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static long hdmi_8998_vco_round_rate(struct clk *c, unsigned long rate)
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{
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unsigned long rrate = rate;
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struct hdmi_pll_vco_clk *vco = to_hdmi_vco_clk(c);
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if (rate < vco->min_rate)
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rrate = vco->min_rate;
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if (rate > vco->max_rate)
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rrate = vco->max_rate;
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return rrate;
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}
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static int hdmi_8998_pll_enable(struct clk *c)
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{
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int rc = 0;
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@ -700,6 +663,151 @@ static int hdmi_8998_pll_enable(struct clk *c)
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return rc;
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}
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/*
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* Get the clock range allowed in atomic update. If clock rate
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* goes beyond this range, a full tear down is required to set
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* the new pixel clock.
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*/
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static int hdmi_8998_vco_get_lock_range(struct clk *c,
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unsigned long pixel_clk)
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{
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const u32 rng = 64, cmp_cnt = 1024;
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const u32 coreclk_div = 5, clks_pll_divsel = 2;
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u32 vco_freq, vco_ratio, ppm_range;
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struct hdmi_8998_reg_cfg cfg = {0};
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pr_debug("rate=%ld\n", pixel_clk);
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hdmi_8998_get_div(&cfg, pixel_clk);
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if (cfg.vco_ratio <= 0 || cfg.vco_freq <= 0) {
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pr_err("couldn't get post div\n");
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return -EINVAL;
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}
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do_div(cfg.vco_freq, HDMI_KHZ_TO_HZ * HDMI_KHZ_TO_HZ);
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vco_freq = (u32) cfg.vco_freq;
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vco_ratio = (u32) cfg.vco_ratio;
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pr_debug("freq %d, ratio %d\n", vco_freq, vco_ratio);
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ppm_range = (rng * HDMI_REF_CLOCK_HZ) / cmp_cnt;
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ppm_range /= vco_freq / vco_ratio;
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ppm_range *= coreclk_div * clks_pll_divsel;
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pr_debug("ppm range: %d\n", ppm_range);
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return ppm_range;
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}
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static int hdmi_8998_vco_rate_atomic_update(struct clk *c,
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unsigned long rate)
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{
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struct hdmi_pll_vco_clk *vco = to_hdmi_vco_clk(c);
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struct mdss_pll_resources *io = vco->priv;
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void __iomem *pll;
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struct hdmi_8998_reg_cfg cfg = {0};
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int rc = 0;
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rc = hdmi_8998_config_phy(rate, &cfg);
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if (rc) {
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pr_err("rate calculation failed\n, rc=%d", rc);
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goto end;
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}
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pll = io->pll_base;
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_W(pll, DEC_START_MODE0, cfg.dec_start_mode0);
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_W(pll, DIV_FRAC_START1_MODE0, cfg.div_frac_start1_mode0);
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_W(pll, DIV_FRAC_START2_MODE0, cfg.div_frac_start2_mode0);
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_W(pll, DIV_FRAC_START3_MODE0, cfg.div_frac_start3_mode0);
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_W(pll, FREQ_UPDATE, 0x01);
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_W(pll, FREQ_UPDATE, 0x00);
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pr_debug("updated to rate %ld\n", rate);
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end:
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return rc;
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}
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static int hdmi_8998_vco_set_rate(struct clk *c, unsigned long rate)
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{
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struct hdmi_pll_vco_clk *vco = to_hdmi_vco_clk(c);
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struct mdss_pll_resources *io = vco->priv;
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unsigned int set_power_dwn = 0;
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bool atomic_update = false;
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int pll_lock_range = 0;
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int rc = 0;
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rc = mdss_pll_resource_enable(io, true);
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if (rc) {
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pr_err("pll resource enable failed, rc=%d\n", rc);
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return rc;
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}
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pr_debug("rate %ld, vco_rate %ld\n", rate, vco->rate);
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if (_R(io->pll_base, C_READY_STATUS) & BIT(0) &&
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_R(io->phy_base, PHY_STATUS) & BIT(0)) {
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pll_lock_range = hdmi_8998_vco_get_lock_range(c, vco->rate);
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if (pll_lock_range > 0 && vco->rate) {
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u32 range_limit;
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range_limit = pll_lock_range *
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(vco->rate / HDMI_KHZ_TO_HZ);
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range_limit /= HDMI_KHZ_TO_HZ;
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pr_debug("range limit %d\n", range_limit);
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if (abs(rate - vco->rate) < range_limit)
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atomic_update = true;
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}
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}
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if (io->pll_on && !atomic_update)
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set_power_dwn = 1;
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if (atomic_update)
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rc = hdmi_8998_vco_rate_atomic_update(c, rate);
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else
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rc = hdmi_8998_pll_set_clk_rate(c, rate);
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if (rc) {
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pr_err("failed to set clk rate\n");
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goto error;
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}
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if (set_power_dwn) {
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rc = hdmi_8998_pll_enable(c);
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if (rc) {
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pr_err("failed to enable pll, rc=%d\n", rc);
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goto error;
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}
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}
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vco->rate = rate;
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vco->rate_set = true;
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error:
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(void)mdss_pll_resource_enable(io, false);
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return rc;
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}
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static long hdmi_8998_vco_round_rate(struct clk *c, unsigned long rate)
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{
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unsigned long rrate = rate;
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struct hdmi_pll_vco_clk *vco = to_hdmi_vco_clk(c);
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if (rate < vco->min_rate)
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rrate = vco->min_rate;
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if (rate > vco->max_rate)
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rrate = vco->max_rate;
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return rrate;
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}
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static int hdmi_8998_vco_prepare(struct clk *c)
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{
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struct hdmi_pll_vco_clk *vco = to_hdmi_vco_clk(c);
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