evie/android_kernel_oneplus_msm8998
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msm: mdss: program the correct MDP_STREAM_CTRL/TOTAL parameters

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While coming out of static screen on command mode panels, we
initialize the DSI host as part of DSI clock control. When partial
update is enabled, we need to program the correct ROI parameters
to DSI controller. Otherwise, issues will be seen if the first
update after the static screen has same ROI parameters as the last
update before static screen. Hence, update the existing ROI
parameters properly to MDP_STREAM_CTRL and MDP_STREAM_TOTAL
registers.

Change-Id: Id6ec179e42592bc4fbaa85d45ad4459036a4faf3
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
This commit is contained in:
Padmanabhan Komanduru 2014-10-18 00:00:49 +05:30 • committed by David Keitel
parent 0334ed1fc3
commit b59e3ba92e
1 changed files with 18 additions and 7 deletions
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25
drivers/video/fbdev/msm/mdss_dsi_host.c
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@ -923,7 +923,8 @@ static void mdss_dsi_mode_setup(struct mdss_panel_data *pdata)
struct mipi_panel_info *mipi; struct mipi_panel_info *mipi;
u32 clk_rate; u32 clk_rate;
u32 hbp, hfp, vbp, vfp, hspw, vspw, width, height; u32 hbp, hfp, vbp, vfp, hspw, vspw, width, height;
u32 ystride, bpp, data, dst_bpp; u32 ystride, bpp, dst_bpp;
u32 stream_ctrl, stream_total;
u32 dummy_xres = 0, dummy_yres = 0; u32 dummy_xres = 0, dummy_yres = 0;
u32 hsync_period, vsync_period; u32 hsync_period, vsync_period;
@ -987,15 +988,25 @@ static void mdss_dsi_mode_setup(struct mdss_panel_data *pdata)
ystride = width * bpp + 1; ystride = width * bpp + 1;
if (pinfo->partial_update_enabled &&
mdss_dsi_is_panel_on(pdata) && pinfo->roi.w &&
pinfo->roi.h) {
stream_ctrl = (((pinfo->roi.w * bpp) + 1) << 16) |
(mipi->vc << 8) | DTYPE_DCS_LWRITE;
stream_total = pinfo->roi.h << 16 | pinfo->roi.w;
} else {
stream_ctrl = (ystride << 16) | (mipi->vc << 8) |
DTYPE_DCS_LWRITE;
stream_total = height << 16 | width;
}
/* DSI_COMMAND_MODE_MDP_STREAM_CTRL */ /* DSI_COMMAND_MODE_MDP_STREAM_CTRL */
data = (ystride << 16) | (mipi->vc << 8) | DTYPE_DCS_LWRITE; MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x60, stream_ctrl);
MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x60, data); MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x58, stream_ctrl);
MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x58, data);
/* DSI_COMMAND_MODE_MDP_STREAM_TOTAL */ /* DSI_COMMAND_MODE_MDP_STREAM_TOTAL */
data = height << 16 | width; MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x64, stream_total);
MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x64, data); MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x5C, stream_total);
MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x5C, data);
} }
} }