From b6729deb26a131083add5b7238c7b7478ef6b502 Mon Sep 17 00:00:00 2001
From: Eric Miao <eric.miao@marvell.com>
Date: Mon, 19 Jan 2009 11:42:32 +0800
Subject: [PATCH] [ARM] pxa: make more SSCR0 bit definitions visible on
 multiple processors

The only exclusive definitions are SSCR0_SCR and SSCR0_SerClkDiv(), loosen
that exclusive #ifdef .. #else .. #endif to allow other definitions to be
visible when slected multiple processors. This helps to pass the building
of pxa-ssp.c.

Signed-off-by: Eric Miao <eric.miao@marvell.com>
---
 arch/arm/mach-pxa/include/mach/regs-ssp.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/mach-pxa/include/mach/regs-ssp.h b/arch/arm/mach-pxa/include/mach/regs-ssp.h
index 3c04cde2cf1f..cf31986f6f05 100644
--- a/arch/arm/mach-pxa/include/mach/regs-ssp.h
+++ b/arch/arm/mach-pxa/include/mach/regs-ssp.h
@@ -41,6 +41,9 @@
 #elif defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
 #define SSCR0_SCR	(0x000fff00)	/* Serial Clock Rate (mask) */
 #define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */
+#endif
+
+#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
 #define SSCR0_EDSS	(1 << 20)	/* Extended data size select */
 #define SSCR0_NCS	(1 << 21)	/* Network clock select */
 #define SSCR0_RIM	(1 << 22)	/* Receive FIFO overrrun interrupt mask */