evie/android_kernel_oneplus_msm8998
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

staging: comedi: ni_mio_common: remove disabled GPCT functions

Browse source 
The GPCT (general purpose counter timer) is handled by the ni_tio and
ni_tiocmd modules. Remove the old disabled code in this file.

Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Reviewed-by: Ian Abbott <abbotti@mev.co.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
H Hartley Sweeten 2015-05-01 14:58:53 -07:00 • committed by Greg Kroah-Hartman
parent 793b193606
commit b81ddcc3c9
1 changed files with 0 additions and 82 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

82
drivers/staging/comedi/drivers/ni_mio_common.c
View file

@ -5018,88 +5018,6 @@ static int ni_gpct_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
} }
#endif #endif
#if 0
/*
* Read the GPCTs current value.
*/
static int GPCT_G_Watch(struct comedi_device *dev, int chan)
{
unsigned int hi1, hi2, lo;
devpriv->gpct_command[chan] &= ~G_Save_Trace;
ni_stc_writew(dev, devpriv->gpct_command[chan],
G_Command_Register(chan));
devpriv->gpct_command[chan] |= G_Save_Trace;
ni_stc_writew(dev, devpriv->gpct_command[chan],
G_Command_Register(chan));
/* This procedure is used because the two registers cannot
* be read atomically. */
do {
hi1 = ni_stc_readw(dev, G_Save_Register_High(chan));
lo = ni_stc_readw(dev, G_Save_Register_Low(chan));
hi2 = ni_stc_readw(dev, G_Save_Register_High(chan));
} while (hi1 != hi2);
return (hi1 << 16) | lo;
}
static void GPCT_Reset(struct comedi_device *dev, int chan)
{
int temp_ack_reg = 0;
devpriv->gpct_cur_operation[chan] = GPCT_RESET;
switch (chan) {
case 0:
ni_stc_writew(dev, G0_Reset, Joint_Reset_Register);
ni_set_bits(dev, Interrupt_A_Enable_Register,
G0_TC_Interrupt_Enable, 0);
ni_set_bits(dev, Interrupt_A_Enable_Register,
G0_Gate_Interrupt_Enable, 0);
temp_ack_reg |= G0_Gate_Error_Confirm;
temp_ack_reg |= G0_TC_Error_Confirm;
temp_ack_reg |= G0_TC_Interrupt_Ack;
temp_ack_reg |= G0_Gate_Interrupt_Ack;
ni_stc_writew(dev, temp_ack_reg, Interrupt_A_Ack_Register);
/* problem...this interferes with the other ctr... */
devpriv->an_trig_etc_reg |= GPFO_0_Output_Enable;
ni_stc_writew(dev, devpriv->an_trig_etc_reg,
Analog_Trigger_Etc_Register);
break;
case 1:
ni_stc_writew(dev, G1_Reset, Joint_Reset_Register);
ni_set_bits(dev, Interrupt_B_Enable_Register,
G1_TC_Interrupt_Enable, 0);
ni_set_bits(dev, Interrupt_B_Enable_Register,
G0_Gate_Interrupt_Enable, 0);
temp_ack_reg |= G1_Gate_Error_Confirm;
temp_ack_reg |= G1_TC_Error_Confirm;
temp_ack_reg |= G1_TC_Interrupt_Ack;
temp_ack_reg |= G1_Gate_Interrupt_Ack;
ni_stc_writew(dev, temp_ack_reg, Interrupt_B_Ack_Register);
devpriv->an_trig_etc_reg |= GPFO_1_Output_Enable;
ni_stc_writew(dev, devpriv->an_trig_etc_reg,
Analog_Trigger_Etc_Register);
break;
}
devpriv->gpct_mode[chan] = 0;
devpriv->gpct_input_select[chan] = 0;
devpriv->gpct_command[chan] = 0;
devpriv->gpct_command[chan] |= G_Synchronized_Gate;
ni_stc_writew(dev, devpriv->gpct_mode[chan], G_Mode_Register(chan));
ni_stc_writew(dev, devpriv->gpct_input_select[chan],
G_Input_Select_Register(chan));
ni_stc_writew(dev, 0, G_Autoincrement_Register(chan));
}
#endif
static irqreturn_t ni_E_interrupt(int irq, void *d) static irqreturn_t ni_E_interrupt(int irq, void *d)
{ {
struct comedi_device *dev = d; struct comedi_device *dev = d;