clk: qcom: mmcc: Update the DSI PLL parent names
The byte and pixel clocks RCG sources from their dsi byte/pixel PLLs, update the parent names so that those parents could be requested. Change-Id: Ie92df31a5cdfa176e872d721a84475a37172a2dd Signed-off-by: Taniya Das <tdas@codeaurora.org>
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1 changed files with 4 additions and 4 deletions
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@ -112,8 +112,8 @@ static const struct parent_map mmcc_parent_map_1[] = {
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static const char * const mmcc_parent_names_1[] = {
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"xo",
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"dsi0_phy_pll_out_byteclk",
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"dsi1_phy_pll_out_byteclk",
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"dsi0pll_byte_clk_mux",
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"dsi1pll_byte_clk_mux",
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"core_bi_pll_test_se",
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};
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@ -240,8 +240,8 @@ static const struct parent_map mmcc_parent_map_8[] = {
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static const char * const mmcc_parent_names_8[] = {
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"xo",
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"dsi0_phy_pll_out_dsiclk",
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"dsi1_phy_pll_out_dsiclk",
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"dsi0pll_pixel_clk_mux",
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"dsi1pll_pixel_clk_mux",
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"core_bi_pll_test_se",
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};
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