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qcom: scm: Support register x6 to pass the session id

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Non-atomic scm call which could be interrupted, trustzone will store
the session id in a register(x6) which will be used when trustzone resumes
the call.
To avoid x6 being used by compiler, HLOS now uses it to send a zero before
making scm call.
This is the same change as in the 32bit scm call.

Change-Id: If7a3ee28bdbf22acf447531603819a6f4f1603ca
Signed-off-by: Se Wang (Patrick) Oh <sewango@codeaurora.org>
This commit is contained in:
Se Wang (Patrick) Oh 2015-07-30 15:48:39 -07:00 • committed by Rohit Vaswani
parent eb590b4075
commit b8708eb232
1 changed files with 9 additions and 4 deletions
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13
drivers/soc/qcom/scm.c
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@ -108,6 +108,7 @@ struct scm_response {
#define R3_STR "x3" #define R3_STR "x3"
#define R4_STR "x4" #define R4_STR "x4"
#define R5_STR "x5" #define R5_STR "x5"
#define R6_STR "x6"
/* Outer caches unsupported on ARM64 platforms */ /* Outer caches unsupported on ARM64 platforms */
#define outer_inv_range(x, y) #define outer_inv_range(x, y)
@ -376,6 +377,7 @@ static int __scm_call_armv8_64(u64 x0, u64 x1, u64 x2, u64 x3, u64 x4, u64 x5,
register u64 r3 asm("r3") = x3; register u64 r3 asm("r3") = x3;
register u64 r4 asm("r4") = x4; register u64 r4 asm("r4") = x4;
register u64 r5 asm("r5") = x5; register u64 r5 asm("r5") = x5;
register u64 r6 asm("r6") = 0;
do { do {
asm volatile( asm volatile(
@ -389,14 +391,15 @@ static int __scm_call_armv8_64(u64 x0, u64 x1, u64 x2, u64 x3, u64 x4, u64 x5,
__asmeq("%7", R3_STR) __asmeq("%7", R3_STR)
__asmeq("%8", R4_STR) __asmeq("%8", R4_STR)
__asmeq("%9", R5_STR) __asmeq("%9", R5_STR)
__asmeq("%10", R6_STR)
#ifdef REQUIRES_SEC #ifdef REQUIRES_SEC
".arch_extension sec\n" ".arch_extension sec\n"
#endif #endif
"smc #0\n" "smc #0\n"
: "=r" (r0), "=r" (r1), "=r" (r2), "=r" (r3) : "=r" (r0), "=r" (r1), "=r" (r2), "=r" (r3)
: "r" (r0), "r" (r1), "r" (r2), "r" (r3), "r" (r4), : "r" (r0), "r" (r1), "r" (r2), "r" (r3), "r" (r4),
"r" (r5) "r" (r5), "r" (r6)
: "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", : "x7", "x8", "x9", "x10", "x11", "x12", "x13",
"x14", "x15", "x16", "x17"); "x14", "x15", "x16", "x17");
} while (r0 == SCM_INTERRUPTED); } while (r0 == SCM_INTERRUPTED);
@ -419,6 +422,7 @@ static int __scm_call_armv8_32(u32 w0, u32 w1, u32 w2, u32 w3, u32 w4, u32 w5,
register u32 r3 asm("r3") = w3; register u32 r3 asm("r3") = w3;
register u32 r4 asm("r4") = w4; register u32 r4 asm("r4") = w4;
register u32 r5 asm("r5") = w5; register u32 r5 asm("r5") = w5;
register u32 r6 asm("r6") = 0;
do { do {
asm volatile( asm volatile(
@ -432,14 +436,15 @@ static int __scm_call_armv8_32(u32 w0, u32 w1, u32 w2, u32 w3, u32 w4, u32 w5,
__asmeq("%7", R3_STR) __asmeq("%7", R3_STR)
__asmeq("%8", R4_STR) __asmeq("%8", R4_STR)
__asmeq("%9", R5_STR) __asmeq("%9", R5_STR)
__asmeq("%10", R6_STR)
#ifdef REQUIRES_SEC #ifdef REQUIRES_SEC
".arch_extension sec\n" ".arch_extension sec\n"
#endif #endif
"smc #0\n" "smc #0\n"
: "=r" (r0), "=r" (r1), "=r" (r2), "=r" (r3) : "=r" (r0), "=r" (r1), "=r" (r2), "=r" (r3)
: "r" (r0), "r" (r1), "r" (r2), "r" (r3), "r" (r4), : "r" (r0), "r" (r1), "r" (r2), "r" (r3), "r" (r4),
"r" (r5) "r" (r5), "r" (r6)
: "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", : "x7", "x8", "x9", "x10", "x11", "x12", "x13",
"x14", "x15", "x16", "x17"); "x14", "x15", "x16", "x17");
} while (r0 == SCM_INTERRUPTED); } while (r0 == SCM_INTERRUPTED);